* [PATCH v3 05/16] dt-bindings: net: phy: The interrupt property is not mandatory
From: Maxime Ripard @ 2019-06-19 9:47 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, David S . Miller,
Chen-Yu Tsai, Maxime Ripard
Cc: Maxime Coquelin, Alexandre Torgue, netdev, linux-arm-kernel,
devicetree, linux-stm32, Maxime Chevallier, Antoine Ténart,
Andrew Lunn, Florian Fainelli, Heiner Kallweit, Rob Herring
In-Reply-To: <27aeb33cf5b896900d5d11bd6957eda268014f0c.1560937626.git-series.maxime.ripard@bootlin.com>
Unlike what was initially claimed in the PHY binding, the interrupt
property of a PHY can be omitted, and the OS will turn to polling instead.
Document that.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
Documentation/devicetree/bindings/net/ethernet-phy.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
index 81d2016d7232..c77f97cbd54b 100644
--- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
@@ -156,7 +156,6 @@ properties:
required:
- reg
- - interrupts
examples:
- |
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v3 04/16] MAINTAINERS: Add Ethernet PHY YAML file
From: Maxime Ripard @ 2019-06-19 9:47 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, David S . Miller,
Chen-Yu Tsai, Maxime Ripard
Cc: Maxime Coquelin, Alexandre Torgue, netdev, linux-arm-kernel,
devicetree, linux-stm32, Maxime Chevallier, Antoine Ténart,
Andrew Lunn, Florian Fainelli, Heiner Kallweit
In-Reply-To: <27aeb33cf5b896900d5d11bd6957eda268014f0c.1560937626.git-series.maxime.ripard@bootlin.com>
While the Ethernet PHY framework was marked as maintained, the device tree
bindings associated to that framework was not listed under the maintained
files. Fix that.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
Changes from v1:
- New patch
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 731b8879bce9..9f629ed4624f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6000,6 +6000,7 @@ M: Heiner Kallweit <hkallweit1@gmail.com>
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/ABI/testing/sysfs-bus-mdio
+F: Documentation/devicetree/bindings/net/ethernet-phy.yaml
F: Documentation/devicetree/bindings/net/mdio*
F: Documentation/networking/phy.rst
F: drivers/net/phy/
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v3 03/16] dt-bindings: net: Add a YAML schemas for the generic MDIO options
From: Maxime Ripard @ 2019-06-19 9:47 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, David S . Miller,
Chen-Yu Tsai, Maxime Ripard
Cc: Maxime Coquelin, Alexandre Torgue, netdev, linux-arm-kernel,
devicetree, linux-stm32, Maxime Chevallier, Antoine Ténart,
Andrew Lunn, Florian Fainelli, Heiner Kallweit
In-Reply-To: <27aeb33cf5b896900d5d11bd6957eda268014f0c.1560937626.git-series.maxime.ripard@bootlin.com>
The MDIO buses have a number of available device tree properties that can
be used in their device tree node. Add a YAML schemas for those.
Suggested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
Changes from v2:
- New patch
---
Documentation/devicetree/bindings/net/mdio.txt | 38 +-------------
Documentation/devicetree/bindings/net/mdio.yaml | 51 ++++++++++++++++++-
2 files changed, 52 insertions(+), 37 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/mdio.yaml
diff --git a/Documentation/devicetree/bindings/net/mdio.txt b/Documentation/devicetree/bindings/net/mdio.txt
index e3e1603f256c..cf8a0105488e 100644
--- a/Documentation/devicetree/bindings/net/mdio.txt
+++ b/Documentation/devicetree/bindings/net/mdio.txt
@@ -1,37 +1 @@
-Common MDIO bus properties.
-
-These are generic properties that can apply to any MDIO bus.
-
-Optional properties:
-- reset-gpios: One GPIO that control the RESET lines of all PHYs on that MDIO
- bus.
-- reset-delay-us: RESET pulse width in microseconds.
-
-A list of child nodes, one per device on the bus is expected. These
-should follow the generic phy.txt, or a device specific binding document.
-
-The 'reset-delay-us' indicates the RESET signal pulse width in microseconds and
-applies to all PHY devices. It must therefore be appropriately determined based
-on all PHY requirements (maximum value of all per-PHY RESET pulse widths).
-
-Example :
-This example shows these optional properties, plus other properties
-required for the TI Davinci MDIO driver.
-
- davinci_mdio: ethernet@5c030000 {
- compatible = "ti,davinci_mdio";
- reg = <0x5c030000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2>;
-
- ethphy0: ethernet-phy@1 {
- reg = <1>;
- };
-
- ethphy1: ethernet-phy@3 {
- reg = <3>;
- };
- };
+This file has moved to mdio.yaml.
diff --git a/Documentation/devicetree/bindings/net/mdio.yaml b/Documentation/devicetree/bindings/net/mdio.yaml
new file mode 100644
index 000000000000..8f4f9d0a2882
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mdio.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/mdio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MDIO Bus Generic Binding
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+ - Florian Fainelli <f.fainelli@gmail.com>
+ - Heiner Kallweit <hkallweit1@gmail.com>
+
+description:
+ These are generic properties that can apply to any MDIO bus. Any
+ MDIO bus must have a list of child nodes, one per device on the
+ bus. These should follow the generic ethernet-phy.yaml document, or
+ a device specific binding document.
+
+properties:
+ reset-gpios:
+ maxItems: 1
+ description:
+ The phandle and specifier for the GPIO that controls the RESET
+ lines of all PHYs on that MDIO bus.
+
+ reset-delay-us:
+ description:
+ RESET pulse width in microseconds. It applies to all PHY devices
+ and must therefore be appropriately determined based on all PHY
+ requirements (maximum value of all per-PHY RESET pulse widths).
+
+examples:
+ - |
+ davinci_mdio: ethernet@5c030000 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x5c030000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reset-gpios = <&gpio2 5 1>;
+ reset-delay-us = <2>;
+
+ ethphy0: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ ethphy1: ethernet-phy@3 {
+ reg = <3>;
+ };
+ };
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v3 02/16] dt-bindings: net: Add a YAML schemas for the generic PHY options
From: Maxime Ripard @ 2019-06-19 9:47 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, David S . Miller,
Chen-Yu Tsai, Maxime Ripard
Cc: Maxime Coquelin, Alexandre Torgue, netdev, linux-arm-kernel,
devicetree, linux-stm32, Maxime Chevallier, Antoine Ténart,
Andrew Lunn, Florian Fainelli, Heiner Kallweit, Rob Herring
In-Reply-To: <27aeb33cf5b896900d5d11bd6957eda268014f0c.1560937626.git-series.maxime.ripard@bootlin.com>
The networking PHYs have a number of available device tree properties that
can be used in their device tree node. Add a YAML schemas for those.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
Changes from v1:
- Add missing compatible options
- add missing phy speeds
- Fix the maintainers entry
- Add a custom select clause to make it validate all phy nodes, and not
just the ones with a compatible
---
Documentation/devicetree/bindings/net/ethernet-phy.yaml | 179 +++++++++-
Documentation/devicetree/bindings/net/phy.txt | 80 +----
2 files changed, 180 insertions(+), 79 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/ethernet-phy.yaml
diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
new file mode 100644
index 000000000000..81d2016d7232
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
@@ -0,0 +1,179 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ethernet PHY Generic Binding
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+ - Florian Fainelli <f.fainelli@gmail.com>
+ - Heiner Kallweit <hkallweit1@gmail.com>
+
+# The dt-schema tools will generate a select statement first by using
+# the compatible, and second by using the node name if any. In our
+# case, the node name is the one we want to match on, while the
+# compatible is optional.
+select:
+ properties:
+ $nodename:
+ pattern: "^ethernet-phy(@[a-f0-9]+)?$"
+
+ required:
+ - $nodename
+
+properties:
+ $nodename:
+ pattern: "^ethernet-phy(@[a-f0-9]+)?$"
+
+ compatible:
+ oneOf:
+ - const: ethernet-phy-ieee802.3-c22
+ description: PHYs that implement IEEE802.3 clause 22
+ - const: ethernet-phy-ieee802.3-c45
+ description: PHYs that implement IEEE802.3 clause 45
+ - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
+ description:
+ If the PHY reports an incorrect ID (or none at all) then the
+ compatible list may contain an entry with the correct PHY ID
+ in the above form.
+ The first group of digits is the 16 bit Phy Identifier 1
+ register, this is the chip vendor OUI bits 3:18. The
+ second group of digits is the Phy Identifier 2 register,
+ this is the chip vendor OUI bits 19:24, followed by 10
+ bits of a vendor specific ID.
+ - items:
+ - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
+ - const: ethernet-phy-ieee802.3-c45
+
+ reg:
+ maxItems: 1
+ minimum: 0
+ maximum: 31
+ description:
+ The ID number for the PHY.
+
+ interrupts:
+ maxItems: 1
+
+ max-speed:
+ enum:
+ - 10
+ - 100
+ - 1000
+ - 2500
+ - 5000
+ - 10000
+ - 20000
+ - 25000
+ - 40000
+ - 50000
+ - 56000
+ - 100000
+ - 200000
+ description:
+ Maximum PHY supported speed in Mbits / seconds.
+
+ broken-turn-around:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ If set, indicates the PHY device does not correctly release
+ the turn around line low at the end of a MDIO transaction.
+
+ enet-phy-lane-swap:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ If set, indicates the PHY will swap the TX/RX lanes to
+ compensate for the board being designed with the lanes
+ swapped.
+
+ eee-broken-100tx:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ Mark the corresponding energy efficient ethernet mode as
+ broken and request the ethernet to stop advertising it.
+
+ eee-broken-1000t:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ Mark the corresponding energy efficient ethernet mode as
+ broken and request the ethernet to stop advertising it.
+
+ eee-broken-10gt:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ Mark the corresponding energy efficient ethernet mode as
+ broken and request the ethernet to stop advertising it.
+
+ eee-broken-1000kx:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ Mark the corresponding energy efficient ethernet mode as
+ broken and request the ethernet to stop advertising it.
+
+ eee-broken-10gkx4:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ Mark the corresponding energy efficient ethernet mode as
+ broken and request the ethernet to stop advertising it.
+
+ eee-broken-10gkr:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ Mark the corresponding energy efficient ethernet mode as
+ broken and request the ethernet to stop advertising it.
+
+ phy-is-integrated:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ If set, indicates that the PHY is integrated into the same
+ physical package as the Ethernet MAC. If needed, muxers
+ should be configured to ensure the integrated PHY is
+ used. The absence of this property indicates the muxers
+ should be configured so that the external PHY is used.
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: phy
+
+ reset-gpios:
+ maxItems: 1
+ description:
+ The GPIO phandle and specifier for the PHY reset signal.
+
+ reset-assert-us:
+ description:
+ Delay after the reset was asserted in microseconds. If this
+ property is missing the delay will be skipped.
+
+ reset-deassert-us:
+ description:
+ Delay after the reset was deasserted in microseconds. If
+ this property is missing the delay will be skipped.
+
+required:
+ - reg
+ - interrupts
+
+examples:
+ - |
+ ethernet {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&PIC>;
+ interrupts = <35 1>;
+ reg = <0>;
+
+ resets = <&rst 8>;
+ reset-names = "phy";
+ reset-gpios = <&gpio1 4 1>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <2000>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt
index 9b9e5b1765dd..2399ee60caed 100644
--- a/Documentation/devicetree/bindings/net/phy.txt
+++ b/Documentation/devicetree/bindings/net/phy.txt
@@ -1,79 +1 @@
-PHY nodes
-
-Required properties:
-
- - interrupts : interrupt specifier for the sole interrupt.
- - reg : The ID number for the phy, usually a small integer
-
-Optional Properties:
-
-- compatible: Compatible list, may contain
- "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
- PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45
- specifications. If neither of these are specified, the default is to
- assume clause 22.
-
- If the PHY reports an incorrect ID (or none at all) then the
- "compatible" list may contain an entry with the correct PHY ID in the
- form: "ethernet-phy-idAAAA.BBBB" where
- AAAA - The value of the 16 bit Phy Identifier 1 register as
- 4 hex digits. This is the chip vendor OUI bits 3:18
- BBBB - The value of the 16 bit Phy Identifier 2 register as
- 4 hex digits. This is the chip vendor OUI bits 19:24,
- followed by 10 bits of a vendor specific ID.
-
- The compatible list should not contain other values than those
- listed here.
-
-- max-speed: Maximum PHY supported speed (10, 100, 1000...)
-
-- broken-turn-around: If set, indicates the PHY device does not correctly
- release the turn around line low at the end of a MDIO transaction.
-
-- enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to
- compensate for the board being designed with the lanes swapped.
-
-- enet-phy-lane-no-swap: If set, indicates that PHY will disable swap of the
- TX/RX lanes. This property allows the PHY to work correcly after e.g. wrong
- bootstrap configuration caused by issues in PCB layout design.
-
-- eee-broken-100tx:
-- eee-broken-1000t:
-- eee-broken-10gt:
-- eee-broken-1000kx:
-- eee-broken-10gkx4:
-- eee-broken-10gkr:
- Mark the corresponding energy efficient ethernet mode as broken and
- request the ethernet to stop advertising it.
-
-- phy-is-integrated: If set, indicates that the PHY is integrated into the same
- physical package as the Ethernet MAC. If needed, muxers should be configured
- to ensure the integrated PHY is used. The absence of this property indicates
- the muxers should be configured so that the external PHY is used.
-
-- resets: The reset-controller phandle and specifier for the PHY reset signal.
-
-- reset-names: Must be "phy" for the PHY reset signal.
-
-- reset-gpios: The GPIO phandle and specifier for the PHY reset signal.
-
-- reset-assert-us: Delay after the reset was asserted in microseconds.
- If this property is missing the delay will be skipped.
-
-- reset-deassert-us: Delay after the reset was deasserted in microseconds.
- If this property is missing the delay will be skipped.
-
-Example:
-
-ethernet-phy@0 {
- compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <&PIC>;
- interrupts = <35 IRQ_TYPE_EDGE_RISING>;
- reg = <0>;
-
- resets = <&rst 8>;
- reset-names = "phy";
- reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- reset-assert-us = <1000>;
- reset-deassert-us = <2000>;
-};
+This file has moved to ethernet-phy.yaml.
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v3 11/16] dt-bindings: net: dwmac: Deprecate the PHY reset properties
From: Maxime Ripard @ 2019-06-19 9:47 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, David S . Miller,
Chen-Yu Tsai, Maxime Ripard
Cc: Maxime Coquelin, Alexandre Torgue, netdev, linux-arm-kernel,
devicetree, linux-stm32, Maxime Chevallier, Antoine Ténart,
Andrew Lunn, Florian Fainelli, Heiner Kallweit,
Martin Blumenstingl
In-Reply-To: <27aeb33cf5b896900d5d11bd6957eda268014f0c.1560937626.git-series.maxime.ripard@bootlin.com>
Even though the DWMAC driver uses some driver specific properties, the PHY
core has a bunch of generic properties and can deal with them nicely.
Let's deprecate our specific properties.
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
Changes from v2:
- Use the deprecated keyword instead of duplicating them
Changes from v1:
- New patch
---
Documentation/devicetree/bindings/net/snps,dwmac.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index 956308806c33..0bf322408500 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -172,16 +172,19 @@ properties:
* snps,priority, TX queue priority (Range 0x0 to 0xF)
snps,reset-gpio:
+ deprecated: true
maxItems: 1
description:
PHY Reset GPIO
snps,reset-active-low:
+ deprecated: true
$ref: /schemas/types.yaml#definitions/flag
description:
Indicates that the PHY Reset is active low
snps,reset-delays-us:
+ deprecated: true
allOf:
- $ref: /schemas/types.yaml#definitions/uint32-array
- minItems: 3
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v3 01/16] dt-bindings: net: Add YAML schemas for the generic Ethernet options
From: Maxime Ripard @ 2019-06-19 9:47 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, David S . Miller,
Chen-Yu Tsai, Maxime Ripard
Cc: Maxime Coquelin, Alexandre Torgue, netdev, linux-arm-kernel,
devicetree, linux-stm32, Maxime Chevallier, Antoine Ténart,
Andrew Lunn, Florian Fainelli, Heiner Kallweit, Rob Herring
The Ethernet controllers have a good number of generic options that can be
needed in a device tree. Add a YAML schemas for those.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
Changes from v2:
- Add back the deprecated properties using the deprecated keyword
Changes from v1:
- Use an enum for phy-connection-types
- Validate the items for the fixed-link array
- Set the number of valid items for link-gpios to 1
- Removed deprecated properties (phy-mode, phy, phy-device)
---
Documentation/devicetree/bindings/net/ethernet-controller.yaml | 204 +++++++-
Documentation/devicetree/bindings/net/ethernet.txt | 69 +--
Documentation/devicetree/bindings/net/fixed-link.txt | 55 +--
3 files changed, 206 insertions(+), 122 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/ethernet-controller.yaml
diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
new file mode 100644
index 000000000000..501ea658b319
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -0,0 +1,204 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ethernet Controller Generic Binding
+
+maintainers:
+ - David S. Miller <davem@davemloft.net>
+
+properties:
+ $nodename:
+ pattern: "^ethernet(@.*)?$"
+
+ local-mac-address:
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/uint8-array
+ - minItems: 6
+ maxItems: 6
+ description:
+ Specifies the MAC address that was assigned to the network device.
+
+ mac-address:
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/uint8-array
+ - minItems: 6
+ maxItems: 6
+ description:
+ Specifies the MAC address that was last used by the boot
+ program; should be used in cases where the MAC address assigned
+ to the device by the boot program is different from the
+ local-mac-address property.
+
+ max-frame-size:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description:
+ Maximum transfer unit (IEEE defined MTU), rather than the
+ maximum frame size (there\'s contradiction in the Devicetree
+ Specification).
+
+ max-speed:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description:
+ Specifies maximum speed in Mbit/s supported by the device.
+
+ nvmem-cells:
+ maxItems: 1
+ description:
+ Reference to an nvmem node for the MAC address
+
+ nvmem-cells-names:
+ const: mac-address
+
+ phy-connection-type:
+ description:
+ Operation mode of the PHY interface
+ enum:
+ # There is not a standard bus between the MAC and the PHY,
+ # something proprietary is being used to embed the PHY in the
+ # MAC.
+ - internal
+ - mii
+ - gmii
+ - sgmii
+ - qsgmii
+ - tbi
+ - rev-mii
+ - rmii
+
+ # RX and TX delays are added by the MAC when required
+ - rgmii
+
+ # RGMII with internal RX and TX delays provided by the PHY,
+ # the MAC should not add the RX or TX delays in this case
+ - rgmii-id
+
+ # RGMII with internal RX delay provided by the PHY, the MAC
+ # should not add an RX delay in this case
+ - rgmii-rxid
+
+ # RGMII with internal TX delay provided by the PHY, the MAC
+ # should not add an TX delay in this case
+ - rgmii-txid
+ - rtbi
+ - smii
+ - xgmii
+ - trgmii
+ - 1000base-x
+ - 2500base-x
+ - rxaui
+ - xaui
+
+ # 10GBASE-KR, XFI, SFI
+ - 10gbase-kr
+ - usxgmii
+
+ phy-mode:
+ $ref: "#/properties/phy-connection-type"
+ deprecated: true
+
+ phy-handle:
+ $ref: /schemas/types.yaml#definitions/phandle
+ description:
+ Specifies a reference to a node representing a PHY device.
+
+ phy:
+ $ref: "#/properties/phy-handle"
+ deprecated: true
+
+ phy-device:
+ $ref: "#/properties/phy-handle"
+ deprecated: true
+
+ rx-fifo-depth:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description:
+ The size of the controller\'s receive fifo in bytes. This is used
+ for components that can have configurable receive fifo sizes,
+ and is useful for determining certain configuration settings
+ such as flow control thresholds.
+
+ tx-fifo-depth:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description:
+ The size of the controller\'s transmit fifo in bytes. This
+ is used for components that can have configurable fifo sizes.
+
+ managed:
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/string
+ - default: auto
+ enum:
+ - auto
+ - in-band-status
+ description:
+ Specifies the PHY management type. If auto is set and fixed-link
+ is not specified, it uses MDIO for management.
+
+ fixed-link:
+ allOf:
+ - if:
+ type: array
+ then:
+ minItems: 1
+ maxItems: 1
+ items:
+ items:
+ - minimum: 0
+ maximum: 31
+ description:
+ Emulated PHY ID, choose any but unique to the all
+ specified fixed-links
+
+ - enum: [0, 1]
+ description:
+ Duplex configuration. 0 for half duplex or 1 for
+ full duplex
+
+ - enum: [10, 100, 1000]
+ description:
+ Link speed in Mbits/sec.
+
+ - enum: [0, 1]
+ description:
+ Pause configuration. 0 for no pause, 1 for pause
+
+ - enum: [0, 1]
+ description:
+ Asymmetric pause configuration. 0 for no asymmetric
+ pause, 1 for asymmetric pause
+
+
+ - if:
+ type: object
+ then:
+ properties:
+ speed:
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/uint32
+ - enum: [10, 100, 1000]
+ description:
+ Link speed.
+
+ full-duplex:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ Indicates that full-duplex is used. When absent, half
+ duplex is assumed.
+
+ asym-pause:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ Indicates that asym_pause should be enabled.
+
+ link-gpios:
+ maxItems: 1
+ description:
+ GPIO to determine if the link is up
+
+ required:
+ - speed
+
+...
diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt
index 5475682bf06e..5df413d01be2 100644
--- a/Documentation/devicetree/bindings/net/ethernet.txt
+++ b/Documentation/devicetree/bindings/net/ethernet.txt
@@ -1,68 +1 @@
-The following properties are common to the Ethernet controllers:
-
-NOTE: All 'phy*' properties documented below are Ethernet specific. For the
-generic PHY 'phys' property, see
-Documentation/devicetree/bindings/phy/phy-bindings.txt.
-
-- mac-address: array of 6 bytes, specifies the MAC address that was last used by
- the boot program; should be used in cases where the MAC address assigned to
- the device by the boot program is different from the "local-mac-address"
- property;
-- local-mac-address: array of 6 bytes, specifies the MAC address that was
- assigned to the network device;
-- nvmem-cells: phandle, reference to an nvmem node for the MAC address
-- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used
-- max-speed: number, specifies maximum speed in Mbit/s supported by the device;
-- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
- the maximum frame size (there's contradiction in the Devicetree
- Specification).
-- phy-mode: string, operation mode of the PHY interface. This is now a de-facto
- standard property; supported values are:
- * "internal" (Internal means there is not a standard bus between the MAC and
- the PHY, something proprietary is being used to embed the PHY in the MAC.)
- * "mii"
- * "gmii"
- * "sgmii"
- * "qsgmii"
- * "tbi"
- * "rev-mii"
- * "rmii"
- * "rgmii" (RX and TX delays are added by the MAC when required)
- * "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the
- MAC should not add the RX or TX delays in this case)
- * "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC
- should not add an RX delay in this case)
- * "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC
- should not add an TX delay in this case)
- * "rtbi"
- * "smii"
- * "xgmii"
- * "trgmii"
- * "1000base-x",
- * "2500base-x",
- * "rxaui"
- * "xaui"
- * "10gbase-kr" (10GBASE-KR, XFI, SFI)
- * "usxgmii"
-- phy-connection-type: the same as "phy-mode" property but described in the
- Devicetree Specification;
-- phy-handle: phandle, specifies a reference to a node representing a PHY
- device; this property is described in the Devicetree Specification and so
- preferred;
-- phy: the same as "phy-handle" property, not recommended for new bindings.
-- phy-device: the same as "phy-handle" property, not recommended for new
- bindings.
-- rx-fifo-depth: the size of the controller's receive fifo in bytes. This
- is used for components that can have configurable receive fifo sizes,
- and is useful for determining certain configuration settings such as
- flow control thresholds.
-- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This
- is used for components that can have configurable fifo sizes.
-- managed: string, specifies the PHY management type. Supported values are:
- "auto", "in-band-status". "auto" is the default, it usess MDIO for
- management if fixed-link is not specified.
-
-Child nodes of the Ethernet controller are typically the individual PHY devices
-connected via the MDIO bus (sometimes the MDIO bus controller is separate).
-They are described in the phy.txt file in this same directory.
-For non-MDIO PHY management see fixed-link.txt.
+This file has moved to ethernet-controller.yaml.
diff --git a/Documentation/devicetree/bindings/net/fixed-link.txt b/Documentation/devicetree/bindings/net/fixed-link.txt
index ec5d889fe3d8..5df413d01be2 100644
--- a/Documentation/devicetree/bindings/net/fixed-link.txt
+++ b/Documentation/devicetree/bindings/net/fixed-link.txt
@@ -1,54 +1 @@
-Fixed link Device Tree binding
-------------------------------
-
-Some Ethernet MACs have a "fixed link", and are not connected to a
-normal MDIO-managed PHY device. For those situations, a Device Tree
-binding allows to describe a "fixed link".
-
-Such a fixed link situation is described by creating a 'fixed-link'
-sub-node of the Ethernet MAC device node, with the following
-properties:
-
-* 'speed' (integer, mandatory), to indicate the link speed. Accepted
- values are 10, 100 and 1000
-* 'full-duplex' (boolean, optional), to indicate that full duplex is
- used. When absent, half duplex is assumed.
-* 'pause' (boolean, optional), to indicate that pause should be
- enabled.
-* 'asym-pause' (boolean, optional), to indicate that asym_pause should
- be enabled.
-* 'link-gpios' ('gpio-list', optional), to indicate if a gpio can be read
- to determine if the link is up.
-
-Old, deprecated 'fixed-link' binding:
-
-* A 'fixed-link' property in the Ethernet MAC node, with 5 cells, of the
- form <a b c d e> with the following accepted values:
- - a: emulated PHY ID, choose any but but unique to the all specified
- fixed-links, from 0 to 31
- - b: duplex configuration: 0 for half duplex, 1 for full duplex
- - c: link speed in Mbits/sec, accepted values are: 10, 100 and 1000
- - d: pause configuration: 0 for no pause, 1 for pause
- - e: asymmetric pause configuration: 0 for no asymmetric pause, 1 for
- asymmetric pause
-
-Examples:
-
-ethernet@0 {
- ...
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- ...
-};
-
-ethernet@1 {
- ...
- fixed-link {
- speed = <1000>;
- pause;
- link-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
- };
- ...
-};
+This file has moved to ethernet-controller.yaml.
base-commit: f08776cae7f5ab26f0f239b9ec58aa60fdbb9a1a
--
git-series 0.9.1
^ permalink raw reply related
* Re: [net-next, PATCH 2/2] net: netsec: remove loops in napi Rx process
From: Ard Biesheuvel @ 2019-06-19 9:41 UTC (permalink / raw)
To: Ilias Apalodimas
Cc: Jaswinder Singh, <netdev@vger.kernel.org>, Masahisa Kojima,
David S. Miller
In-Reply-To: <1560931034-6810-2-git-send-email-ilias.apalodimas@linaro.org>
On Wed, 19 Jun 2019 at 09:57, Ilias Apalodimas
<ilias.apalodimas@linaro.org> wrote:
>
> netsec_process_rx was running in a loop trying to process as many packets
> as possible before re-enabling interrupts. With the recent DMA changes
> this is not needed anymore as we manage to consume all the budget without
> looping over the function.
> Since it has no performance penalty let's remove that and simplify the Rx
> path a bit
>
> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> drivers/net/ethernet/socionext/netsec.c | 11 ++---------
> 1 file changed, 2 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c
> index a10ef700f16d..48fd7448b513 100644
> --- a/drivers/net/ethernet/socionext/netsec.c
> +++ b/drivers/net/ethernet/socionext/netsec.c
> @@ -820,19 +820,12 @@ static int netsec_process_rx(struct netsec_priv *priv, int budget)
> static int netsec_napi_poll(struct napi_struct *napi, int budget)
> {
> struct netsec_priv *priv;
> - int rx, done, todo;
> + int done;
>
> priv = container_of(napi, struct netsec_priv, napi);
>
> netsec_process_tx(priv);
> -
> - todo = budget;
> - do {
> - rx = netsec_process_rx(priv, todo);
> - todo -= rx;
> - } while (rx);
> -
> - done = budget - todo;
> + done = netsec_process_rx(priv, budget);
>
> if (done < budget && napi_complete_done(napi, done)) {
> unsigned long flags;
> --
> 2.20.1
>
^ permalink raw reply
* Re: [net-next, PATCH 1/2] net: netsec: initialize tx ring on ndo_open
From: Ard Biesheuvel @ 2019-06-19 9:40 UTC (permalink / raw)
To: Ilias Apalodimas
Cc: Jaswinder Singh, <netdev@vger.kernel.org>, Masahisa Kojima,
David S. Miller
In-Reply-To: <1560931034-6810-1-git-send-email-ilias.apalodimas@linaro.org>
On Wed, 19 Jun 2019 at 09:57, Ilias Apalodimas
<ilias.apalodimas@linaro.org> wrote:
>
> Since we changed the Tx ring handling and now depend not bit31 to figure
s/not/on/
> out the owner of the descriptor, we should initialize this every time
> the device goes down-up instead of doing it once on driver init. If the
> value is not correctly initialized the device won't have any available
> descriptors
>
> Fixes: 35e07d23473972b8876f98bcfc631ebcf779e870 ("net: socionext: remove mmio reads on Tx")
>
> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> drivers/net/ethernet/socionext/netsec.c | 32 ++++++++++++++-----------
> 1 file changed, 18 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c
> index cba5881b2746..a10ef700f16d 100644
> --- a/drivers/net/ethernet/socionext/netsec.c
> +++ b/drivers/net/ethernet/socionext/netsec.c
> @@ -1029,7 +1029,6 @@ static void netsec_free_dring(struct netsec_priv *priv, int id)
> static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id)
> {
> struct netsec_desc_ring *dring = &priv->desc_ring[id];
> - int i;
>
> dring->vaddr = dma_alloc_coherent(priv->dev, DESC_SZ * DESC_NUM,
> &dring->desc_dma, GFP_KERNEL);
> @@ -1040,19 +1039,6 @@ static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id)
> if (!dring->desc)
> goto err;
>
> - if (id == NETSEC_RING_TX) {
> - for (i = 0; i < DESC_NUM; i++) {
> - struct netsec_de *de;
> -
> - de = dring->vaddr + (DESC_SZ * i);
> - /* de->attr is not going to be accessed by the NIC
> - * until netsec_set_tx_de() is called.
> - * No need for a dma_wmb() here
> - */
> - de->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD;
> - }
> - }
> -
> return 0;
> err:
> netsec_free_dring(priv, id);
> @@ -1060,6 +1046,23 @@ static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id)
> return -ENOMEM;
> }
>
> +static void netsec_setup_tx_dring(struct netsec_priv *priv)
> +{
> + struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
> + int i;
> +
> + for (i = 0; i < DESC_NUM; i++) {
> + struct netsec_de *de;
> +
> + de = dring->vaddr + (DESC_SZ * i);
> + /* de->attr is not going to be accessed by the NIC
> + * until netsec_set_tx_de() is called.
> + * No need for a dma_wmb() here
> + */
> + de->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD;
> + }
> +}
> +
> static int netsec_setup_rx_dring(struct netsec_priv *priv)
> {
> struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
> @@ -1361,6 +1364,7 @@ static int netsec_netdev_open(struct net_device *ndev)
>
> pm_runtime_get_sync(priv->dev);
>
> + netsec_setup_tx_dring(priv);
> ret = netsec_setup_rx_dring(priv);
> if (ret) {
> netif_err(priv, probe, priv->ndev,
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH] net/ipv4: fib_trie: Avoid cryptic ternary expressions
From: Joe Perches @ 2019-06-19 9:36 UTC (permalink / raw)
To: Nick Desaulniers, Matthias Kaehlcke
Cc: David S . Miller, Alexey Kuznetsov, Hideaki YOSHIFUJI,
Alexander Duyck, netdev, LKML, Douglas Anderson,
Nathan Huckleberry, clang-built-linux, Nathan Chancellor
In-Reply-To: <CAKwvOd=i2qsEO90cHn-Zvgd7vbhK5Z4RH89gJGy=Cjzbi9QRMA@mail.gmail.com>
On Tue, 2019-06-18 at 16:23 -0700, Nick Desaulniers wrote:
> As a side note, I'm going to try to see if MAINTAINERS and
> scripts/get_maintainers.pl supports regexes on the commit messages in
> order to cc our mailing list
Neither. Why should either?
^ permalink raw reply
* Re: [PATCH v2 2/5] net: macb: add support for sgmii MAC-PHY interface
From: Russell King - ARM Linux admin @ 2019-06-19 9:31 UTC (permalink / raw)
To: Parshuram Thombare
Cc: andrew, nicolas.ferre, davem, f.fainelli, netdev, hkallweit1,
linux-kernel, rafalc, aniljoy, piotrs
In-Reply-To: <1560933646-29852-1-git-send-email-pthombar@cadence.com>
On Wed, Jun 19, 2019 at 09:40:46AM +0100, Parshuram Thombare wrote:
> This patch add support for SGMII interface) and
> 2.5Gbps MAC in Cadence ethernet controller driver.
>
> Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
> ---
> drivers/net/ethernet/cadence/macb.h | 76 ++++++++++--
> drivers/net/ethernet/cadence/macb_main.c | 151 ++++++++++++++++++++---
> 2 files changed, 200 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 35ed13236c8b..d7ffbfb2ecc0 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -80,6 +80,7 @@
> #define MACB_RBQPH 0x04D4
>
> /* GEM register offsets. */
> +#define GEM_NCR 0x0000 /* Network Control */
> #define GEM_NCFGR 0x0004 /* Network Config */
> #define GEM_USRIO 0x000c /* User IO */
> #define GEM_DMACFG 0x0010 /* DMA Configuration */
> @@ -159,6 +160,9 @@
> #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
> #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
> #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
> +#define GEM_PCS_CTRL 0x0200 /* PCS Control */
> +#define GEM_PCS_STATUS 0x0204 /* PCS Status */
> +#define GEM_PCS_AN_LP_BASE 0x0214 /* PCS AN LP BASE*/
> #define GEM_DCFG1 0x0280 /* Design Config 1 */
> #define GEM_DCFG2 0x0284 /* Design Config 2 */
> #define GEM_DCFG3 0x0288 /* Design Config 3 */
> @@ -274,6 +278,10 @@
> #define MACB_IRXFCS_OFFSET 19
> #define MACB_IRXFCS_SIZE 1
>
> +/* GEM specific NCR bitfields. */
> +#define GEM_TWO_PT_FIVE_GIG_OFFSET 29
> +#define GEM_TWO_PT_FIVE_GIG_SIZE 1
> +
> /* GEM specific NCFGR bitfields. */
> #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
> #define GEM_GBE_SIZE 1
> @@ -326,6 +334,9 @@
> #define MACB_MDIO_SIZE 1
> #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
> #define MACB_IDLE_SIZE 1
> +#define MACB_DUPLEX_OFFSET 3
> +#define MACB_DUPLEX_SIZE 1
> +
>
> /* Bitfields in TSR */
> #define MACB_UBR_OFFSET 0 /* Used bit read */
> @@ -459,11 +470,37 @@
> #define MACB_REV_OFFSET 0
> #define MACB_REV_SIZE 16
>
> +/* Bitfields in PCS_CONTROL. */
> +#define GEM_PCS_CTRL_RST_OFFSET 15
> +#define GEM_PCS_CTRL_RST_SIZE 1
> +#define GEM_PCS_CTRL_EN_AN_OFFSET 12
> +#define GEM_PCS_CTRL_EN_AN_SIZE 1
> +#define GEM_PCS_CTRL_RESTART_AN_OFFSET 9
> +#define GEM_PCS_CTRL_RESTART_AN_SIZE 1
> +
> +/* Bitfields in PCS_STATUS. */
> +#define GEM_PCS_STATUS_AN_DONE_OFFSET 5
> +#define GEM_PCS_STATUS_AN_DONE_SIZE 1
> +#define GEM_PCS_STATUS_AN_SUPPORT_OFFSET 3
> +#define GEM_PCS_STATUS_AN_SUPPORT_SIZE 1
> +#define GEM_PCS_STATUS_LINK_OFFSET 2
> +#define GEM_PCS_STATUS_LINK_SIZE 1
> +
> +/* Bitfield in PCS_AN_LP_BASE */
> +#define GEM_PCS_AN_LP_BASE_LINK_OFFSET 15
> +#define GEM_PCS_AN_LP_BASE_LINK_SIZE 1
> +#define GEM_PCS_AN_LP_BASE_DUPLEX_OFFSET 12
> +#define GEM_PCS_AN_LP_BASE_DUPLEX_SIZE 1
> +#define GEM_PCS_AN_LP_BASE_SPEED_OFFSET 10
> +#define GEM_PCS_AN_LP_BASE_SPEED_SIZE 2
> +
> /* Bitfields in DCFG1. */
> #define GEM_IRQCOR_OFFSET 23
> #define GEM_IRQCOR_SIZE 1
> #define GEM_DBWDEF_OFFSET 25
> #define GEM_DBWDEF_SIZE 3
> +#define GEM_NO_PCS_OFFSET 0
> +#define GEM_NO_PCS_SIZE 1
>
> /* Bitfields in DCFG2. */
> #define GEM_RX_PKT_BUFF_OFFSET 20
> @@ -636,19 +673,32 @@
> #define MACB_MAN_CODE 2
>
> /* Capability mask bits */
> -#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
> -#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
> -#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
> -#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
> -#define MACB_CAPS_USRIO_DISABLED 0x00000010
> -#define MACB_CAPS_JUMBO 0x00000020
> -#define MACB_CAPS_GEM_HAS_PTP 0x00000040
> -#define MACB_CAPS_BD_RD_PREFETCH 0x00000080
> -#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
> -#define MACB_CAPS_FIFO_MODE 0x10000000
> -#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
> -#define MACB_CAPS_SG_DISABLED 0x40000000
> -#define MACB_CAPS_MACB_IS_GEM 0x80000000
> +#define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0)
> +#define MACB_CAPS_USRIO_HAS_CLKEN BIT(1)
> +#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII BIT(2)
> +#define MACB_CAPS_NO_GIGABIT_HALF BIT(3)
> +#define MACB_CAPS_USRIO_DISABLED BIT(4)
> +#define MACB_CAPS_JUMBO BIT(5)
> +#define MACB_CAPS_GEM_HAS_PTP BIT(6)
> +#define MACB_CAPS_BD_RD_PREFETCH BIT(7)
> +#define MACB_CAPS_NEEDS_RSTONUBR BIT(8)
> +#define MACB_CAPS_FIFO_MODE BIT(28)
> +#define MACB_CAPS_GIGABIT_MODE_AVAILABLE BIT(29)
> +#define MACB_CAPS_SG_DISABLED BIT(30)
> +#define MACB_CAPS_MACB_IS_GEM BIT(31)
> +#define MACB_CAPS_PCS BIT(24)
> +#define MACB_CAPS_MACB_IS_GEM_GXL BIT(25)
> +
> +#define MACB_GEM7010_IDNUM 0x009
> +#define MACB_GEM7014_IDNU 0x107
> +#define MACB_GEM7014A_IDNUM 0x207
> +#define MACB_GEM7016_IDNUM 0x10a
> +#define MACB_GEM7017_IDNUM 0x00a
> +#define MACB_GEM7017A_IDNUM 0x20a
> +#define MACB_GEM7020_IDNUM 0x003
> +#define MACB_GEM7021_IDNUM 0x00c
> +#define MACB_GEM7021A_IDNUM 0x20c
> +#define MACB_GEM7022_IDNUM 0x00b
>
> /* LSO settings */
> #define MACB_LSO_UFO_ENABLE 0x01
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index 830af86d3c65..884d2a4408ad 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -403,6 +403,7 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
> */
> static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
> {
> + struct macb *bp = netdev_priv(dev);
> long ferr, rate, rate_rounded;
>
> if (!clk)
> @@ -418,6 +419,12 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
> case SPEED_1000:
> rate = 125000000;
> break;
> + case SPEED_2500:
> + if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL)
> + rate = 312500000;
> + else
> + rate = 125000000;
> + break;
> default:
> return;
> }
> @@ -448,15 +455,16 @@ static void gem_phylink_validate(struct phylink_config *pl_config,
> __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
>
> switch (state->interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
> + phylink_set(mask, 2500baseT_Full);
This doesn't look correct to me. SGMII as defined by Cisco only
supports 1G, 100M and 10M speeds, not 2.5G.
Even so, SGMII is not limited to just base-T - PHYs are free to offer
base-X to SGMII conversion too.
> + /* fallthrough */
> case PHY_INTERFACE_MODE_GMII:
> case PHY_INTERFACE_MODE_RGMII:
> if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) {
> phylink_set(mask, 1000baseT_Full);
> - phylink_set(mask, 1000baseX_Full);
> - if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) {
> - phylink_set(mask, 1000baseT_Half);
> + if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
> phylink_set(mask, 1000baseT_Half);
> - }
> }
> /* fallthrough */
> case PHY_INTERFACE_MODE_MII:
> @@ -466,6 +474,16 @@ static void gem_phylink_validate(struct phylink_config *pl_config,
> phylink_set(mask, 100baseT_Half);
> phylink_set(mask, 100baseT_Full);
> break;
> +
> + case PHY_INTERFACE_MODE_2500BASEX:
> + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
> + phylink_set(mask, 2500baseX_Full);
> + /* fallthrough */
> + case PHY_INTERFACE_MODE_1000BASEX:
> + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
> + phylink_set(mask, 1000baseX_Full);
> + break;
Please see how other drivers which use phylink deal with the validate()
format, and please read the phylink documentation:
* Note that the PHY may be able to transform from one connection
* technology to another, so, eg, don't clear 1000BaseX just
* because the MAC is unable to BaseX mode. This is more about
* clearing unsupported speeds and duplex settings.
> +
> default:
> break;
> }
> @@ -480,13 +498,52 @@ static int gem_phylink_mac_link_state(struct phylink_config *pl_config,
> {
> struct net_device *netdev = to_net_dev(pl_config->dev);
> struct macb *bp = netdev_priv(netdev);
> + u32 status;
>
> - state->speed = bp->speed;
> - state->duplex = bp->duplex;
> - state->link = bp->link;
> + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
> + status = gem_readl(bp, PCS_STATUS);
> + state->an_complete = GEM_BFEXT(PCS_STATUS_AN_DONE, status);
> + status = gem_readl(bp, PCS_AN_LP_BASE);
> + switch (GEM_BFEXT(PCS_AN_LP_BASE_SPEED, status)) {
> + case 0:
> + state->speed = SPEED_10;
> + break;
> + case 1:
> + state->speed = SPEED_100;
> + break;
> + case 2:
> + state->speed = SPEED_1000;
> + break;
> + default:
> + break;
> + }
> + state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR));
> + state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR));
> + } else if (bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
> + state->speed = SPEED_2500;
> + state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR));
> + state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR));
> + } else if (bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
> + state->speed = SPEED_1000;
> + state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR));
> + state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR));
> + }
So if the phy_interface type is not one listed, we leave state alone?
That doesn't seem good. It looks like you should at least simply set
state->duplex and state->link according to the NSR register content,
and always derive the speed.
It would also be good to set state->lp_advertising if you have access
to that so ethtool can report the link partner's abilities. Current
Marvell drivers that use phylink don't do that because that information
is not available from the hardware.
> return 1;
> }
>
> +static void gem_mac_an_restart(struct phylink_config *pl_config)
> +{
> + struct net_device *netdev = to_net_dev(pl_config->dev);
> + struct macb *bp = netdev_priv(netdev);
> +
> + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
> + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
> + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
> + gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) |
> + GEM_BIT(PCS_CTRL_RESTART_AN));
> + }
This will only be called for 802.3z link modes, so you don't need these
checks.
> +}
> +
> static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
> const struct phylink_link_state *state)
> {
> @@ -506,18 +563,26 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
> reg &= ~GEM_BIT(GBE);
> if (state->duplex)
> reg |= MACB_BIT(FD);
> + macb_or_gem_writel(bp, NCFGR, reg);
>
> switch (state->speed) {
> + case SPEED_2500:
> + gem_writel(bp, NCFGR, GEM_BIT(GBE) |
> + gem_readl(bp, NCFGR));
> + gem_writel(bp, NCR, GEM_BIT(TWO_PT_FIVE_GIG) |
> + gem_readl(bp, NCR));
> + break;
> case SPEED_1000:
> - reg |= GEM_BIT(GBE);
> + gem_writel(bp, NCFGR, GEM_BIT(GBE) |
> + gem_readl(bp, NCFGR));
> break;
> case SPEED_100:
> - reg |= MACB_BIT(SPD);
> + macb_writel(bp, NCFGR, MACB_BIT(SPD) |
> + macb_readl(bp, NCFGR));
> break;
> default:
> break;
> }
> - macb_or_gem_writel(bp, NCFGR, reg);
>
> bp->speed = state->speed;
> bp->duplex = state->duplex;
This is not going to work for 802.3z nor SGMII properly when in-band
negotiation is used. We don't know ahead of time what the speed and
duplex will be. Please see existing drivers for examples showing
how mac_config() should be implemented (there's good reason why its
laid out as it is in those drivers.)
> @@ -555,6 +620,7 @@ static void gem_mac_link_down(struct phylink_config *pl_config,
> static const struct phylink_mac_ops gem_phylink_ops = {
> .validate = gem_phylink_validate,
> .mac_link_state = gem_phylink_mac_link_state,
> + .mac_an_restart = gem_mac_an_restart,
> .mac_config = gem_mac_config,
> .mac_link_up = gem_mac_link_up,
> .mac_link_down = gem_mac_link_down,
> @@ -2248,7 +2314,9 @@ static void macb_init_hw(struct macb *bp)
> macb_set_hwaddr(bp);
>
> config = macb_mdc_clk_div(bp);
> - if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
> + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
> + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
> + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
> config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
Configuration of the phy interface mode should be done in mac_config()
as previously mentioned, some PHYs can change their link mode at run
time. Hotplugging SFPs can change the link mode between SGMII and
base-X too.
> config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
> config |= MACB_BIT(PAE); /* PAuse Enable */
> @@ -2273,6 +2341,17 @@ static void macb_init_hw(struct macb *bp)
> if (bp->caps & MACB_CAPS_JUMBO)
> bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
>
> + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
> + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
> + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
> + //Enable PCS AN
> + gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) |
> + GEM_BIT(PCS_CTRL_EN_AN));
> + //Reset PCS block
> + gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) |
> + GEM_BIT(PCS_CTRL_RST));
> + }
> +
Should be in mac_config.
> macb_configure_dma(bp);
>
> /* Initialize TX and RX buffers */
> @@ -3364,6 +3443,22 @@ static void macb_configure_caps(struct macb *bp,
> dcfg = gem_readl(bp, DCFG1);
> if (GEM_BFEXT(IRQCOR, dcfg) == 0)
> bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
> + if (GEM_BFEXT(NO_PCS, dcfg) == 0)
> + bp->caps |= MACB_CAPS_PCS;
> + switch (MACB_BFEXT(IDNUM, macb_readl(bp, MID))) {
> + case MACB_GEM7016_IDNUM:
> + case MACB_GEM7017_IDNUM:
> + case MACB_GEM7017A_IDNUM:
> + case MACB_GEM7020_IDNUM:
> + case MACB_GEM7021_IDNUM:
> + case MACB_GEM7021A_IDNUM:
> + case MACB_GEM7022_IDNUM:
> + bp->caps |= MACB_CAPS_USRIO_DISABLED;
> + bp->caps |= MACB_CAPS_MACB_IS_GEM_GXL;
> + break;
> + default:
> + break;
> + }
> dcfg = gem_readl(bp, DCFG2);
> if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
> bp->caps |= MACB_CAPS_FIFO_MODE;
> @@ -3652,7 +3747,9 @@ static int macb_init(struct platform_device *pdev)
> /* Set MII management clock divider */
> val = macb_mdc_clk_div(bp);
> val |= macb_dbw(bp);
> - if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
> + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
> + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
> + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
> val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
Should be in mac_config.
> macb_writel(bp, NCFGR, val);
>
> @@ -4346,11 +4443,37 @@ static int macb_probe(struct platform_device *pdev)
> }
>
> phy_mode = of_get_phy_mode(np);
> - if (phy_mode < 0)
> + if (phy_mode < 0) {
> /* not found in DT, MII by default */
> bp->phy_interface = PHY_INTERFACE_MODE_MII;
> - else
> + } else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) {
> + u32 interface_supported = 1;
> +
> + if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
> + phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
> + phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
> + if (!(bp->caps & MACB_CAPS_PCS))
> + interface_supported = 0;
> + } else if (phy_mode == PHY_INTERFACE_MODE_GMII ||
> + phy_mode == PHY_INTERFACE_MODE_RGMII) {
> + if (!macb_is_gem(bp))
> + interface_supported = 0;
> + } else if (phy_mode != PHY_INTERFACE_MODE_RMII &&
> + phy_mode != PHY_INTERFACE_MODE_MII) {
> + /* Add new mode before this */
> + interface_supported = 0;
> + }
> +
> + if (!interface_supported) {
> + netdev_err(dev, "Phy mode %s not supported",
> + phy_modes(phy_mode));
> + goto err_out_free_netdev;
> + }
> +
> bp->phy_interface = phy_mode;
> + } else {
> + bp->phy_interface = phy_mode;
> + }
>
> /* IP specific init */
> err = init(pdev);
> --
> 2.17.1
>
>
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
^ permalink raw reply
* Re: [RFC PATCH 0/2] enable broadcom tagging for bcm531x5 switches
From: Benedikt Spranger @ 2019-06-19 9:18 UTC (permalink / raw)
To: Florian Fainelli; +Cc: netdev, Sebastian Andrzej Siewior, Kurt Kanzenbach
In-Reply-To: <bc932af1-d957-bd40-fa65-ee05b9478ec7@gmail.com>
On Tue, 18 Jun 2019 11:16:23 -0700
Florian Fainelli <f.fainelli@gmail.com> wrote:
> How is that a problem for other machines? Does that lead to some kind
> of broadcast storm because there are machines that keep trying to
> respond to ARP solicitations?
Mirroring broadcast packages on the interface they are coming in, is
IMHO a poor idea. As a result any switch connected to wan update the
MAC table and send packages on a port where they do not belong to.
Just imagine to send a DHCP request. The BPi R1 acts as nearly perfect
black hole in such a situation.
> The few aspects that bother me, not in any particular order, are that:
>
> - you might be able to not change anything and just get away with the
> one line patch below that sets skb->offload_fwd_mark to 1 to indicate
> to the bridge, not to bother with sending a copy of the packet, since
> the HW took care of that already
I can test it, but i like to note that the changed function is not
executed in case of bcm53125.
See commit 54e98b5d663f ("net: dsa: b53: Turn off Broadcom tags for
more switches")
From drivers/net/dsa/b53/b53_common.c:
---8<---
/* Older models (5325, 5365) support a different tag format that we do
* not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
* mode to be turned on which means we need to specifically manage ARL
* misses on multicast addresses (TBD).
*/
if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
!b53_can_enable_brcm_tags(ds, port))
return DSA_TAG_PROTO_NONE;
---8<---
> - the patch from me that you included was part of a larger series that
> also addressed multicast while in management mode, such we would not
> have to chose like you did, have you tested it, did it somehow not
> work?
Since the patch series was not available any more, I had to gather the
snippets. Trying these patches was the last effort to get the switch
running without causing network problems.
(As far as I see are other parts of the original patch series in
mainline)
> - you have not copied the DSA maintainers on all of the patches, so
> you get a C grade for your patch submission
OK. As a RFC patch I am more interrested in the attention of the
original author of the patch, which I received :)
Regards
Bene Spranger
^ permalink raw reply
* Re: [PATCH v2 1/5] net: macb: add phylink support
From: Russell King - ARM Linux admin @ 2019-06-19 9:22 UTC (permalink / raw)
To: Parshuram Thombare
Cc: andrew, nicolas.ferre, davem, f.fainelli, netdev, hkallweit1,
linux-kernel, rafalc, aniljoy, piotrs
In-Reply-To: <1560933636-29684-1-git-send-email-pthombar@cadence.com>
On Wed, Jun 19, 2019 at 09:40:36AM +0100, Parshuram Thombare wrote:
> This patch replace phylib API's by phylink API's.
>
> Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
> ---
> drivers/net/ethernet/cadence/Kconfig | 2 +-
> drivers/net/ethernet/cadence/macb.h | 3 +
> drivers/net/ethernet/cadence/macb_main.c | 312 +++++++++++++----------
> 3 files changed, 182 insertions(+), 135 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/Kconfig b/drivers/net/ethernet/cadence/Kconfig
> index 1766697c9c5a..d71411a71587 100644
> --- a/drivers/net/ethernet/cadence/Kconfig
> +++ b/drivers/net/ethernet/cadence/Kconfig
> @@ -22,7 +22,7 @@ if NET_VENDOR_CADENCE
> config MACB
> tristate "Cadence MACB/GEM support"
> depends on HAS_DMA
> - select PHYLIB
> + select PHYLINK
> ---help---
> The Cadence MACB ethernet interface is found on many Atmel AT32 and
> AT91 parts. This driver also supports the Cadence GEM (Gigabit
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 00ee5e8e0ff0..35ed13236c8b 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -14,6 +14,7 @@
> #include <linux/ptp_clock_kernel.h>
> #include <linux/net_tstamp.h>
> #include <linux/interrupt.h>
> +#include <linux/phylink.h>
>
> #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
> #define MACB_EXT_DESC
> @@ -1227,6 +1228,8 @@ struct macb {
> u32 rx_intr_mask;
>
> struct macb_pm_data pm_data;
> + struct phylink *pl;
> + struct phylink_config pl_config;
> };
>
> #ifdef CONFIG_MACB_USE_HWSTAMP
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index c545c5b435d8..830af86d3c65 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -39,6 +39,7 @@
> #include <linux/tcp.h>
> #include <linux/iopoll.h>
> #include <linux/pm_runtime.h>
> +#include <linux/phylink.h>
> #include "macb.h"
>
> /* This structure is only used for MACB on SiFive FU540 devices */
> @@ -438,115 +439,150 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
> netdev_err(dev, "adjusting tx_clk failed.\n");
> }
>
> -static void macb_handle_link_change(struct net_device *dev)
> +static void gem_phylink_validate(struct phylink_config *pl_config,
> + unsigned long *supported,
> + struct phylink_link_state *state)
> {
> - struct macb *bp = netdev_priv(dev);
> - struct phy_device *phydev = dev->phydev;
> - unsigned long flags;
> - int status_change = 0;
> + struct net_device *netdev = to_net_dev(pl_config->dev);
> + struct macb *bp = netdev_priv(netdev);
> + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
> +
> + switch (state->interface) {
> + case PHY_INTERFACE_MODE_GMII:
> + case PHY_INTERFACE_MODE_RGMII:
> + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) {
> + phylink_set(mask, 1000baseT_Full);
> + phylink_set(mask, 1000baseX_Full);
> + if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) {
> + phylink_set(mask, 1000baseT_Half);
> + phylink_set(mask, 1000baseT_Half);
> + }
> + }
> + /* fallthrough */
> + case PHY_INTERFACE_MODE_MII:
> + case PHY_INTERFACE_MODE_RMII:
> + phylink_set(mask, 10baseT_Half);
> + phylink_set(mask, 10baseT_Full);
> + phylink_set(mask, 100baseT_Half);
> + phylink_set(mask, 100baseT_Full);
> + break;
> + default:
> + break;
> + }
>
> - spin_lock_irqsave(&bp->lock, flags);
> + bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
> + bitmap_and(state->advertising, state->advertising, mask,
> + __ETHTOOL_LINK_MODE_MASK_NBITS);
Consider using linkmode_and() here.
> +}
>
> - if (phydev->link) {
> - if ((bp->speed != phydev->speed) ||
> - (bp->duplex != phydev->duplex)) {
> - u32 reg;
> +static int gem_phylink_mac_link_state(struct phylink_config *pl_config,
> + struct phylink_link_state *state)
> +{
> + struct net_device *netdev = to_net_dev(pl_config->dev);
> + struct macb *bp = netdev_priv(netdev);
>
> - reg = macb_readl(bp, NCFGR);
> - reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
> - if (macb_is_gem(bp))
> - reg &= ~GEM_BIT(GBE);
> + state->speed = bp->speed;
> + state->duplex = bp->duplex;
> + state->link = bp->link;
You can't read from the hardware what the actual MAC is doing?
> + return 1;
> +}
>
> - if (phydev->duplex)
> - reg |= MACB_BIT(FD);
> - if (phydev->speed == SPEED_100)
> - reg |= MACB_BIT(SPD);
> - if (phydev->speed == SPEED_1000 &&
> - bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
> - reg |= GEM_BIT(GBE);
> +static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
> + const struct phylink_link_state *state)
> +{
> + struct net_device *netdev = to_net_dev(pl_config->dev);
> + struct macb *bp = netdev_priv(netdev);
> + unsigned long flags;
>
> - macb_or_gem_writel(bp, NCFGR, reg);
> + spin_lock_irqsave(&bp->lock, flags);
>
> - bp->speed = phydev->speed;
> - bp->duplex = phydev->duplex;
> - status_change = 1;
> - }
> - }
> + if (bp->speed != state->speed ||
> + bp->duplex != state->duplex) {
Please read the updated phylink documentation - state->{speed,duplex}
are not always valid depending on the negotiation mode.
> + u32 reg;
>
> - if (phydev->link != bp->link) {
> - if (!phydev->link) {
> - bp->speed = 0;
> - bp->duplex = -1;
> + reg = macb_readl(bp, NCFGR);
> + reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
> + if (macb_is_gem(bp))
> + reg &= ~GEM_BIT(GBE);
> + if (state->duplex)
> + reg |= MACB_BIT(FD);
> +
> + switch (state->speed) {
> + case SPEED_1000:
> + reg |= GEM_BIT(GBE);
> + break;
> + case SPEED_100:
> + reg |= MACB_BIT(SPD);
> + break;
> + default:
> + break;
> }
> - bp->link = phydev->link;
> + macb_or_gem_writel(bp, NCFGR, reg);
> +
> + bp->speed = state->speed;
> + bp->duplex = state->duplex;
>
> - status_change = 1;
> + if (state->link)
> + macb_set_tx_clk(bp->tx_clk, state->speed, netdev);
> }
>
> spin_unlock_irqrestore(&bp->lock, flags);
> +}
>
> - if (status_change) {
> - if (phydev->link) {
> - /* Update the TX clock rate if and only if the link is
> - * up and there has been a link change.
> - */
> - macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
> +static void gem_mac_link_up(struct phylink_config *pl_config, unsigned int mode,
> + phy_interface_t interface, struct phy_device *phy)
> +{
> + struct net_device *netdev = to_net_dev(pl_config->dev);
> + struct macb *bp = netdev_priv(netdev);
>
> - netif_carrier_on(dev);
> - netdev_info(dev, "link up (%d/%s)\n",
> - phydev->speed,
> - phydev->duplex == DUPLEX_FULL ?
> - "Full" : "Half");
> - } else {
> - netif_carrier_off(dev);
> - netdev_info(dev, "link down\n");
> - }
> - }
> + bp->link = 1;
> + /* Enable TX and RX */
> + macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
> +}
> +
> +static void gem_mac_link_down(struct phylink_config *pl_config,
> + unsigned int mode, phy_interface_t interface)
> +{
> + struct net_device *netdev = to_net_dev(pl_config->dev);
> + struct macb *bp = netdev_priv(netdev);
> +
> + bp->link = 0;
> + /* Disable TX and RX */
> + macb_writel(bp, NCR,
> + macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE)));
> }
>
> +static const struct phylink_mac_ops gem_phylink_ops = {
> + .validate = gem_phylink_validate,
> + .mac_link_state = gem_phylink_mac_link_state,
> + .mac_config = gem_mac_config,
> + .mac_link_up = gem_mac_link_up,
> + .mac_link_down = gem_mac_link_down,
> +};
> +
> /* based on au1000_eth. c*/
> static int macb_mii_probe(struct net_device *dev)
> {
> struct macb *bp = netdev_priv(dev);
> struct phy_device *phydev;
> struct device_node *np;
> - int ret, i;
> + int ret;
>
> np = bp->pdev->dev.of_node;
> ret = 0;
>
> - if (np) {
> - if (of_phy_is_fixed_link(np)) {
> - bp->phy_node = of_node_get(np);
> - } else {
> - bp->phy_node = of_parse_phandle(np, "phy-handle", 0);
> - /* fallback to standard phy registration if no
> - * phy-handle was found nor any phy found during
> - * dt phy registration
> - */
> - if (!bp->phy_node && !phy_find_first(bp->mii_bus)) {
> - for (i = 0; i < PHY_MAX_ADDR; i++) {
> - phydev = mdiobus_scan(bp->mii_bus, i);
> - if (IS_ERR(phydev) &&
> - PTR_ERR(phydev) != -ENODEV) {
> - ret = PTR_ERR(phydev);
> - break;
> - }
> - }
> -
> - if (ret)
> - return -ENODEV;
> - }
> - }
> + bp->pl_config.dev = &dev->dev;
> + bp->pl_config.type = PHYLINK_NETDEV;
> + bp->pl = phylink_create(&bp->pl_config, of_fwnode_handle(np),
> + bp->phy_interface, &gem_phylink_ops);
> + if (IS_ERR(bp->pl)) {
> + netdev_err(dev,
> + "error creating PHYLINK: %ld\n", PTR_ERR(bp->pl));
> + return PTR_ERR(bp->pl);
> }
At this point bp->pl can never be NULL.
>
> - if (bp->phy_node) {
> - phydev = of_phy_connect(dev, bp->phy_node,
> - &macb_handle_link_change, 0,
> - bp->phy_interface);
> - if (!phydev)
> - return -ENODEV;
> - } else {
> + ret = phylink_of_phy_connect(bp->pl, np, 0);
> + if (ret == -ENODEV && bp->mii_bus) {
> phydev = phy_find_first(bp->mii_bus);
> if (!phydev) {
> netdev_err(dev, "no PHY found\n");
> @@ -554,29 +590,18 @@ static int macb_mii_probe(struct net_device *dev)
> }
>
> /* attach the mac to the phy */
> - ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
> - bp->phy_interface);
> + ret = phylink_connect_phy(bp->pl, phydev);
> if (ret) {
> netdev_err(dev, "Could not attach to PHY\n");
> return ret;
> }
> }
>
> - /* mask with MAC supported features */
> - if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
> - phy_set_max_speed(phydev, SPEED_1000);
> - else
> - phy_set_max_speed(phydev, SPEED_100);
> -
> - if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
> - phy_remove_link_mode(phydev,
> - ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
> -
> bp->link = 0;
> bp->speed = 0;
> bp->duplex = -1;
>
> - return 0;
> + return ret;
> }
>
> static int macb_mii_init(struct macb *bp)
> @@ -604,17 +629,7 @@ static int macb_mii_init(struct macb *bp)
> dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
>
> np = bp->pdev->dev.of_node;
> - if (np && of_phy_is_fixed_link(np)) {
> - if (of_phy_register_fixed_link(np) < 0) {
> - dev_err(&bp->pdev->dev,
> - "broken fixed-link specification %pOF\n", np);
> - goto err_out_free_mdiobus;
> - }
> -
> - err = mdiobus_register(bp->mii_bus);
> - } else {
> - err = of_mdiobus_register(bp->mii_bus, np);
> - }
> + err = of_mdiobus_register(bp->mii_bus, np);
>
> if (err)
> goto err_out_free_fixed_link;
> @@ -630,7 +645,6 @@ static int macb_mii_init(struct macb *bp)
> err_out_free_fixed_link:
> if (np && of_phy_is_fixed_link(np))
> of_phy_deregister_fixed_link(np);
> -err_out_free_mdiobus:
> of_node_put(bp->phy_node);
> mdiobus_free(bp->mii_bus);
> err_out:
> @@ -2422,7 +2436,7 @@ static int macb_open(struct net_device *dev)
> netif_carrier_off(dev);
>
> /* if the phy is not yet register, retry later*/
> - if (!dev->phydev) {
> + if (!bp->pl) {
So this check is unnecessary.
> err = -EAGAIN;
> goto pm_exit;
> }
> @@ -2444,7 +2458,7 @@ static int macb_open(struct net_device *dev)
> macb_init_hw(bp);
>
> /* schedule a link state check */
> - phy_start(dev->phydev);
> + phylink_start(bp->pl);
>
> netif_tx_start_all_queues(dev);
>
> @@ -2471,8 +2485,8 @@ static int macb_close(struct net_device *dev)
> for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
> napi_disable(&queue->napi);
>
> - if (dev->phydev)
> - phy_stop(dev->phydev);
> + if (bp->pl)
> + phylink_stop(bp->pl);
Ditto.
>
> spin_lock_irqsave(&bp->lock, flags);
> macb_reset_hw(bp);
> @@ -3161,6 +3175,29 @@ static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
> return ret;
> }
>
> +static int gem_ethtool_get_link_ksettings(struct net_device *netdev,
> + struct ethtool_link_ksettings *cmd)
> +{
> + struct macb *bp = netdev_priv(netdev);
> +
> + if (!bp->pl)
> + return -ENOTSUPP;
Ditto.
> +
> + return phylink_ethtool_ksettings_get(bp->pl, cmd);
> +}
> +
> +static int
> +gem_ethtool_set_link_ksettings(struct net_device *netdev,
> + const struct ethtool_link_ksettings *cmd)
> +{
> + struct macb *bp = netdev_priv(netdev);
> +
> + if (!bp->pl)
> + return -ENOTSUPP;
Ditto.
> +
> + return phylink_ethtool_ksettings_set(bp->pl, cmd);
> +}
> +
> static const struct ethtool_ops macb_ethtool_ops = {
> .get_regs_len = macb_get_regs_len,
> .get_regs = macb_get_regs,
> @@ -3168,8 +3205,8 @@ static const struct ethtool_ops macb_ethtool_ops = {
> .get_ts_info = ethtool_op_get_ts_info,
> .get_wol = macb_get_wol,
> .set_wol = macb_set_wol,
> - .get_link_ksettings = phy_ethtool_get_link_ksettings,
> - .set_link_ksettings = phy_ethtool_set_link_ksettings,
> + .get_link_ksettings = gem_ethtool_get_link_ksettings,
> + .set_link_ksettings = gem_ethtool_set_link_ksettings,
> .get_ringparam = macb_get_ringparam,
> .set_ringparam = macb_set_ringparam,
> };
> @@ -3182,8 +3219,8 @@ static const struct ethtool_ops gem_ethtool_ops = {
> .get_ethtool_stats = gem_get_ethtool_stats,
> .get_strings = gem_get_ethtool_strings,
> .get_sset_count = gem_get_sset_count,
> - .get_link_ksettings = phy_ethtool_get_link_ksettings,
> - .set_link_ksettings = phy_ethtool_set_link_ksettings,
> + .get_link_ksettings = gem_ethtool_get_link_ksettings,
> + .set_link_ksettings = gem_ethtool_set_link_ksettings,
> .get_ringparam = macb_get_ringparam,
> .set_ringparam = macb_set_ringparam,
> .get_rxnfc = gem_get_rxnfc,
> @@ -3192,17 +3229,16 @@ static const struct ethtool_ops gem_ethtool_ops = {
>
> static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
> {
> - struct phy_device *phydev = dev->phydev;
> struct macb *bp = netdev_priv(dev);
>
> if (!netif_running(dev))
> return -EINVAL;
>
> - if (!phydev)
> + if (!bp->pl)
> return -ENODEV;
Ditto.
>
> if (!bp->ptp_info)
> - return phy_mii_ioctl(phydev, rq, cmd);
> + return phylink_mii_ioctl(bp->pl, rq, cmd);
>
> switch (cmd) {
> case SIOCSHWTSTAMP:
> @@ -3210,7 +3246,7 @@ static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
> case SIOCGHWTSTAMP:
> return bp->ptp_info->get_hwtst(dev, rq);
> default:
> - return phy_mii_ioctl(phydev, rq, cmd);
> + return phylink_mii_ioctl(bp->pl, rq, cmd);
> }
> }
>
> @@ -3710,7 +3746,7 @@ static int at91ether_open(struct net_device *dev)
> MACB_BIT(HRESP));
>
> /* schedule a link state check */
> - phy_start(dev->phydev);
> + phylink_start(lp->pl);
>
> netif_start_queue(dev);
>
> @@ -4183,13 +4219,12 @@ static int macb_probe(struct platform_device *pdev)
> struct clk *tsu_clk = NULL;
> unsigned int queue_mask, num_queues;
> bool native_io;
> - struct phy_device *phydev;
> struct net_device *dev;
> struct resource *regs;
> void __iomem *mem;
> const char *mac;
> struct macb *bp;
> - int err, val;
> + int err, val, phy_mode;
>
> regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> mem = devm_ioremap_resource(&pdev->dev, regs);
> @@ -4310,12 +4345,12 @@ static int macb_probe(struct platform_device *pdev)
> macb_get_hwaddr(bp);
> }
>
> - err = of_get_phy_mode(np);
> - if (err < 0)
> + phy_mode = of_get_phy_mode(np);
> + if (phy_mode < 0)
> /* not found in DT, MII by default */
> bp->phy_interface = PHY_INTERFACE_MODE_MII;
> else
> - bp->phy_interface = err;
> + bp->phy_interface = phy_mode;
The phy interface mode is managed by phylink - and there are phys out
there that dynamically change their link mode. You may wish to update
the link mode in your mac_config() implementation too.
>
> /* IP specific init */
> err = init(pdev);
> @@ -4326,8 +4361,6 @@ static int macb_probe(struct platform_device *pdev)
> if (err)
> goto err_out_free_netdev;
>
> - phydev = dev->phydev;
> -
> netif_carrier_off(dev);
>
> err = register_netdev(dev);
> @@ -4339,7 +4372,8 @@ static int macb_probe(struct platform_device *pdev)
> tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
> (unsigned long)bp);
>
> - phy_attached_info(phydev);
> + if (dev->phydev)
> + phy_attached_info(dev->phydev);
phylink already prints information about the attached phy, why do we
need another print here?
>
> netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
> macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
> @@ -4351,7 +4385,9 @@ static int macb_probe(struct platform_device *pdev)
> return 0;
>
> err_out_unregister_mdio:
> - phy_disconnect(dev->phydev);
> + rtnl_lock();
> + phylink_disconnect_phy(bp->pl);
> + rtnl_unlock();
> mdiobus_unregister(bp->mii_bus);
> of_node_put(bp->phy_node);
> if (np && of_phy_is_fixed_link(np))
> @@ -4385,13 +4421,18 @@ static int macb_remove(struct platform_device *pdev)
>
> if (dev) {
> bp = netdev_priv(dev);
> - if (dev->phydev)
> - phy_disconnect(dev->phydev);
> + if (bp->pl) {
> + rtnl_lock();
> + phylink_disconnect_phy(bp->pl);
> + rtnl_unlock();
> + }
> mdiobus_unregister(bp->mii_bus);
> if (np && of_phy_is_fixed_link(np))
> of_phy_deregister_fixed_link(np);
> dev->phydev = NULL;
> mdiobus_free(bp->mii_bus);
> + if (bp->pl)
> + phylink_destroy(bp->pl);
>
> unregister_netdev(dev);
> pm_runtime_disable(&pdev->dev);
> @@ -4434,8 +4475,9 @@ static int __maybe_unused macb_suspend(struct device *dev)
> for (q = 0, queue = bp->queues; q < bp->num_queues;
> ++q, ++queue)
> napi_disable(&queue->napi);
> - phy_stop(netdev->phydev);
> - phy_suspend(netdev->phydev);
> + phylink_stop(bp->pl);
> + if (netdev->phydev)
> + phy_suspend(netdev->phydev);
When the attached phy is stopped, the state machine suspends the phy.
Why do we need an explicit call to phy_suspend() here, bypassing
phylink?
> spin_lock_irqsave(&bp->lock, flags);
> macb_reset_hw(bp);
> spin_unlock_irqrestore(&bp->lock, flags);
> @@ -4483,9 +4525,11 @@ static int __maybe_unused macb_resume(struct device *dev)
> for (q = 0, queue = bp->queues; q < bp->num_queues;
> ++q, ++queue)
> napi_enable(&queue->napi);
> - phy_resume(netdev->phydev);
> - phy_init_hw(netdev->phydev);
> - phy_start(netdev->phydev);
> + if (netdev->phydev) {
> + phy_resume(netdev->phydev);
> + phy_init_hw(netdev->phydev);
> + }
> + phylink_start(bp->pl);
When the phy is started, the phy state machine will resume the phy.
Same question as above.
> }
>
> bp->macbgem_ops.mog_init_rings(bp);
> --
> 2.17.1
>
>
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
^ permalink raw reply
* Re: [RFC bpf-next 0/7] Programming socket lookup with BPF
From: Jakub Sitnicki @ 2019-06-19 9:13 UTC (permalink / raw)
To: Florian Westphal; +Cc: netdev, bpf, kernel-team
In-Reply-To: <20190618135258.spo6c457h6dfknt2@breakpoint.cc>
Hey Florian,
Thanks for taking a look at it.
On Tue, Jun 18, 2019 at 03:52 PM CEST, Florian Westphal wrote:
> Jakub Sitnicki <jakub@cloudflare.com> wrote:
>> - XDP programs using bpf_sk_lookup helpers, like load balancers, can't
>> find the listening socket to check for SYN cookies with TPROXY redirect.
>
> Sorry for the question, but where is the problem?
> (i.e., is it with TPROXY or bpf side)?
The way I see it is that the problem is that we have mappings for
steering traffic into sockets split between two places: (1) the socket
lookup tables, and (2) the TPROXY rules.
BPF programs that need to check if there is a socket the packet is
destined for have access to the socket lookup tables, via the mentioned
bpf_sk_lookup helper, but are unaware of TPROXY redirects.
For TCP we're able to look up from BPF if there are any established,
request, and "normal" listening sockets. The listening sockets that
receive connections via TPROXY are invisible to BPF progs.
Why are we interested in finding all listening sockets? To check if any
of them had SYN queue overflow recently and if we should honor SYN
cookies.
>> - TPROXY takes a reference to the listening socket on dispatch, which
>> raises lock contention concerns.
>
> FWIW this could be avoided in similar way as to how we handle noref dsts.
>
> The only reason we need to take the reference at the moment is because
> once skb leaves the TPROXY target hook, the skb could leave rcu
> protection as well at some point (nfqueue for example).
>
> Maybe its even enough to move reference taking to nfqueue and add
> 'noref' destructor, that would allow skb_steal_sock to propagate
> refcounted value in __inet_lookup_skb.
>
> So, at least for this part I don't see a technical reason why this
> has to grab a reference for listener socket.
That's helpful, thanks! We rely on TPROXY, so I would like to help with
that. Let me see if I can get time to work on it.
>
>> - Traffic steering configuration is split over several iptables rules, at
>> least one per service, which makes configuration changes error prone.
>
> Could you perhaps sketch an example ruleset (doesn't have to be complete
> nor parse-able by itpables-restore), I would just like to understand if
> there is any room for improvement on netfilter/iptables/nft side.
Happy to. Scenarios that are of interest to us:
1) Port sharing, while accepting on a set of subnets
(same are the demo BPF prog from cover letter)
ip route add local 192.0.2.0/24 dev lo
ip route add local 198.51.100.0/24 dev lo
ip route add local 203.0.113.0/24 dev lo
ipset create net1 hash:net
ipset create net2 hash:net
ipset create net3 hash:net
ipset add net1 192.0.2.0/24
ipset add net2 198.51.100.0/24
ipset add net3 203.0.113.0/24
iptables -t mangle -A PREROUTING -p tcp --dport 80 \
-m set --match-set net1 dst \
-j TPROXY --on-ip=127.0.0.1 --on-port=81
iptables -t mangle -A PREROUTING -p tcp --dport 80 \
-m set --match-set net2 dst \
-j TPROXY --on-ip=127.0.0.1 --on-port=82
2) Receving on all ports, except some
iptables -t mangle -A PREROUTING -p tcp --dport 80 \
-m set --match-set net3 dst \
-j TPROXY --on-ip=127.0.0.1 --on-port=81
iptables -t mangle -A PREROUTING -p tcp \
-m set --match-set net3 dst \
-j TPROXY --on-ip=127.0.0.1 --on-port=1
3) Steering part of the traffic to a different socket (A/B testing)
iptables -t mangle -A PREROUTING -p tcp \
-m set --match-set net3 dst \
-m statistic --mode random --probability 0.01 \
-j TPROXY --on-ip=127.0.0.1 --on-port=2
iptables -t mangle -A PREROUTING -p tcp \
-m set --match-set net3 dst \
-j TPROXY --on-ip=127.0.0.1 --on-port=1
One thing I haven't touched on in the cover letter is that to use TPROXY
you need to set IP_TRANSPARENT on the listening socket. This requires
that your process runs with CAP_NET_RAW or CAP_NET_ADMIN, or that you
get the socket from systemd.
I haven't been able to explain why the process needs to be privileged to
receive traffic steered with TPROXY, but it turns out to be a pain point
too. We end up having to lock down the service to ensure it doesn't use
the elevated privileges for anything else than setting IP_TRANSPARENT.
Thanks,
Jakub
^ permalink raw reply
* Re: linux-next: build failure after merge of the net-next tree
From: Kevin 'ldir' Darbyshire-Bryant @ 2019-06-19 8:50 UTC (permalink / raw)
To: Masahiro Yamada
Cc: Stephen Rothwell, David Miller, Networking,
Linux Next Mailing List, Linux Kernel Mailing List
In-Reply-To: <CAK7LNARVfXySZK_Wzmww=UeFwpWu+vjbctK33zX9KW8w_adexw@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2992 bytes --]
Greetings!
As the guilty party in authoring this, and also pretty new around here
I’m wondering what I need to do to help clean it up?
> On 19 Jun 2019, at 05:14, Masahiro Yamada <yamada.masahiro@socionext.com> wrote:
>
> On Wed, Jun 19, 2019 at 1:02 PM Masahiro Yamada
> <yamada.masahiro@socionext.com> wrote:
>>
>> Hi.
>>
>>
>> On Wed, Jun 19, 2019 at 12:23 PM Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>>>
>>> Hi all,
>>>
>>> After merging the net-next tree, today's linux-next build (x86_64
>>> allmodconfig) failed like this:
>>>
>>> In file included from usr/include/linux/tc_act/tc_ctinfo.hdrtest.c:1:
>>> ./usr/include/linux/tc_act/tc_ctinfo.h:30:21: error: implicit declaration of function 'BIT' [-Werror=implicit-function-declaration]
>>> CTINFO_MODE_DSCP = BIT(0),
>>> ^~~
>>> ./usr/include/linux/tc_act/tc_ctinfo.h:30:2: error: enumerator value for 'CTINFO_MODE_DSCP' is not an integer constant
>>> CTINFO_MODE_DSCP = BIT(0),
>>> ^~~~~~~~~~~~~~~~
>>> ./usr/include/linux/tc_act/tc_ctinfo.h:32:1: error: enumerator value for 'CTINFO_MODE_CPMARK' is not an integer constant
>>> };
>>> ^
>>>
>>> Caused by commit
>>>
>>> 24ec483cec98 ("net: sched: Introduce act_ctinfo action")
>>>
>>> Presumably exposed by commit
>>>
>>> b91976b7c0e3 ("kbuild: compile-test UAPI headers to ensure they are self-contained")
>>>
>>> from the kbuild tree.
Stephen, thanks for the fixup - is that now in the tree or do I need to submit
a fix via the normal net-next channel so it gets picked up by the iproute2 people
who maintain a local copy of the uapi includes?
>>
>>
>> My commit correctly blocked the broken UAPI header, Hooray!
>>
>> People export more and more headers that
>> are never able to compile in user-space.
>>
>> We must block new breakages from coming in.
>>
>>
>> BIT() is not exported to user-space
>> since it is not prefixed with underscore.
>>
>>
>> You can use _BITUL() in user-space,
>> which is available in include/uapi/linux/const.h
Thanks for the pointers.
I am confused as to why I didn’t hit this issue when I built & run tested locally off
the net-next tree.
>>
>>
>
>
> I just took a look at
> include/uapi/linux/tc_act/tc_ctinfo.h
>
>
> I just wondered why the following can be compiled:
>
> struct tc_ctinfo {
> tc_gen;
> };
>
>
> Then, I found 'tc_gen' is a macro.
>
> #define tc_gen \
> __u32 index; \
> __u32 capab; \
> int action; \
> int refcnt; \
> int bindcnt
>
>
>
> What a hell.
This is what other actions do e.g. tc_skbedit. Can you advise what I should do instead?
> --
> Best Regards
> Masahiro Yamada
Many thanks to all for your valuable time & advice.
Cheers,
Kevin D-B
gpg: 012C ACB2 28C6 C53E 9775 9123 B3A2 389B 9DE2 334A
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^ permalink raw reply
* RE: [RFC net-next 1/5] net: stmmac: introduce IEEE 802.1Qbv configuration functionalities
From: Voon, Weifeng @ 2019-06-19 8:48 UTC (permalink / raw)
To: Andrew Lunn
Cc: David S. Miller, Maxime Coquelin, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, Jose Abreu, Giuseppe Cavallaro,
Florian Fainelli, Alexandre Torgue, Gomes, Vinicius,
Ong, Boon Leong
In-Reply-To: <20190619030729.GA26784@lunn.ch>
> > +static int est_poll_srwo(void *ioaddr) {
> > + /* Poll until the EST GCL Control[SRWO] bit clears.
> > + * Total wait = 12 x 50ms ~= 0.6s.
> > + */
> > + unsigned int retries = 12;
> > + unsigned int value;
> > +
> > + do {
> > + value = TSN_RD32(ioaddr + MTL_EST_GCL_CTRL);
> > + if (!(value & MTL_EST_GCL_CTRL_SRWO))
> > + return 0;
> > + msleep(50);
> > + } while (--retries);
> > +
> > + return -ETIMEDOUT;
>
> Maybe use one of the readx_poll_timeout() macros?
>
> > +static int est_read_gce(void *ioaddr, unsigned int row,
> > + unsigned int *gates, unsigned int *ti_nsec,
> > + unsigned int dbgb, unsigned int dbgm) {
> > + struct tsn_hw_cap *cap = &dw_tsn_hwcap;
> > + unsigned int ti_wid = cap->ti_wid;
> > + unsigned int gates_mask;
> > + unsigned int ti_mask;
> > + unsigned int value;
> > + int ret;
> > +
> > + gates_mask = (1 << cap->txqcnt) - 1;
> > + ti_mask = (1 << ti_wid) - 1;
> > +
> > + ret = est_read_gcl_config(ioaddr, &value, row, 0, dbgb, dbgm);
> > + if (ret) {
> > + TSN_ERR("Read GCE failed! row=%u\n", row);
>
> It is generally not a good idea to put wrappers around the kernel print
> functions. It would be better if all these functions took struct
> stmmac_priv *priv rather than ioaddr, so you could then do
>
> netdev_err(priv->dev, "Read GCE failed! row=%u\n", row);
>
> > + /* Ensure that HW is not in the midst of GCL transition */
> > + value = TSN_RD32(ioaddr + MTL_EST_CTRL);
>
> Also, don't put wrapper around readl()/writel().
>
> > + value &= ~MTL_EST_CTRL_SSWL;
> > +
> > + /* MTL_EST_CTRL value has been read earlier, if TILS value
> > + * differs, we update here.
> > + */
> > + if (tils != dw_tsn_hwtunable[TSN_HWTUNA_TX_EST_TILS]) {
> > + value &= ~MTL_EST_CTRL_TILS;
> > + value |= (tils << MTL_EST_CTRL_TILS_SHIFT);
> > +
> > + TSN_WR32(value, ioaddr + MTL_EST_CTRL);
> > + dw_tsn_hwtunable[TSN_HWTUNA_TX_EST_TILS] = tils;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int est_set_ov(void *ioaddr,
> > + const unsigned int *ptov,
> > + const unsigned int *ctov)
> > +{
> > + unsigned int value;
> > +
> > + if (!dw_tsn_feat_en[TSN_FEAT_ID_EST])
> > + return -ENOTSUPP;
> > +
> > + value = TSN_RD32(ioaddr + MTL_EST_CTRL);
> > + value &= ~MTL_EST_CTRL_SSWL;
> > +
> > + if (ptov) {
> > + if (*ptov > EST_PTOV_MAX) {
> > + TSN_WARN("EST: invalid PTOV(%u), max=%u\n",
> > + *ptov, EST_PTOV_MAX);
>
> It looks like most o the TSN_WARN should actually be netdev_dbg().
>
> Andrew
Hi Andrew,
This file is targeted for dual licensing which is GPL-2.0 OR BSD-3-Clause.
This is the reason why we are using wrappers around the functions so that
all the function call is generic.
Regards,
Weifeng
^ permalink raw reply
* [PATCH v2 5/5] net: macb: parameter added to cadence ethernet controller DT binding
From: Parshuram Thombare @ 2019-06-19 8:41 UTC (permalink / raw)
To: andrew, nicolas.ferre, davem, f.fainelli
Cc: linux, netdev, hkallweit1, linux-kernel, rafalc, aniljoy, piotrs,
pthombar
In-Reply-To: <1560933600-27626-1-git-send-email-pthombar@cadence.com>
New parameters added to Cadence ethernet controller DT binding
for USXGMII interface.
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
---
Documentation/devicetree/bindings/net/macb.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
index 63c73fafe26d..dabdf9d3b574 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -28,6 +28,9 @@ Required properties:
Optional elements: 'rx_clk' applies to cdns,zynqmp-gem
Optional elements: 'tsu_clk'
- clocks: Phandles to input clocks.
+- serdes-rate-gbps External serdes rate.Mandatory for USXGMII mode.
+ 5 - 5G
+ 10 - 10G
The MAC address will be determined using the optional properties
defined in ethernet.txt.
--
2.17.1
^ permalink raw reply related
* [PATCH v2 4/5] net: macb: add support for high speed interface
From: Parshuram Thombare @ 2019-06-19 8:41 UTC (permalink / raw)
To: andrew, nicolas.ferre, davem, f.fainelli
Cc: linux, netdev, hkallweit1, linux-kernel, rafalc, aniljoy, piotrs,
pthombar
In-Reply-To: <1560933600-27626-1-git-send-email-pthombar@cadence.com>
This patch add support for high speed USXGMII PCS and 10G
speed in Cadence ethernet controller driver.
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
---
drivers/net/ethernet/cadence/macb.h | 41 +++++
drivers/net/ethernet/cadence/macb_main.c | 216 +++++++++++++++++++----
2 files changed, 218 insertions(+), 39 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 34768d35aea1..0910d0bfdceb 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -85,6 +85,7 @@
#define GEM_USRIO 0x000c /* User IO */
#define GEM_DMACFG 0x0010 /* DMA Configuration */
#define GEM_JML 0x0048 /* Jumbo Max Length */
+#define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */
#define GEM_HRB 0x0080 /* Hash Bottom */
#define GEM_HRT 0x0084 /* Hash Top */
#define GEM_SA1B 0x0088 /* Specific1 Bottom */
@@ -172,6 +173,9 @@
#define GEM_DCFG7 0x0298 /* Design Config 7 */
#define GEM_DCFG8 0x029C /* Design Config 8 */
#define GEM_DCFG10 0x02A4 /* Design Config 10 */
+#define GEM_DCFG12 0x02AC /* Design Config 12 */
+#define GEM_USX_CONTROL 0x0A80 /* USXGMII control register */
+#define GEM_USX_STATUS 0x0A88 /* USXGMII status register */
#define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
#define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
@@ -279,6 +283,8 @@
#define MACB_IRXFCS_SIZE 1
/* GEM specific NCR bitfields. */
+#define GEM_ENABLE_HS_MAC_OFFSET 31
+#define GEM_ENABLE_HS_MAC_SIZE 1
#define GEM_TWO_PT_FIVE_GIG_OFFSET 29
#define GEM_TWO_PT_FIVE_GIG_SIZE 1
@@ -470,6 +476,10 @@
#define MACB_REV_OFFSET 0
#define MACB_REV_SIZE 16
+/* Bitfield in HS_MAC_CONFIG */
+#define GEM_HS_MAC_SPEED_OFFSET 0
+#define GEM_HS_MAC_SPEED_SIZE 3
+
/* Bitfields in PCS_CONTROL. */
#define GEM_PCS_CTRL_RST_OFFSET 15
#define GEM_PCS_CTRL_RST_SIZE 1
@@ -535,6 +545,34 @@
#define GEM_RXBD_RDBUFF_OFFSET 8
#define GEM_RXBD_RDBUFF_SIZE 4
+/* Bitfields in DCFG12. */
+#define GEM_HIGH_SPEED_OFFSET 26
+#define GEM_HIGH_SPEED_SIZE 1
+
+/* Bitfields in USX_CONTROL. */
+#define GEM_USX_CTRL_SPEED_OFFSET 14
+#define GEM_USX_CTRL_SPEED_SIZE 3
+#define GEM_SERDES_RATE_OFFSET 12
+#define GEM_SERDES_RATE_SIZE 2
+#define GEM_RX_SCR_BYPASS_OFFSET 9
+#define GEM_RX_SCR_BYPASS_SIZE 1
+#define GEM_TX_SCR_BYPASS_OFFSET 8
+#define GEM_TX_SCR_BYPASS_SIZE 1
+#define GEM_RX_SYNC_RESET_OFFSET 2
+#define GEM_RX_SYNC_RESET_SIZE 1
+#define GEM_TX_EN_OFFSET 1
+#define GEM_TX_EN_SIZE 1
+#define GEM_SIGNAL_OK_OFFSET 0
+#define GEM_SIGNAL_OK_SIZE 1
+
+/* Bitfields in USX_STATUS. */
+#define GEM_USX_TX_FAULT_OFFSET 28
+#define GEM_USX_TX_FAULT_SIZE 1
+#define GEM_USX_RX_FAULT_OFFSET 27
+#define GEM_USX_RX_FAULT_SIZE 1
+#define GEM_USX_BLOCK_LOCK_OFFSET 0
+#define GEM_USX_BLOCK_LOCK_SIZE 1
+
/* Bitfields in TISUBN */
#define GEM_SUBNSINCR_OFFSET 0
#define GEM_SUBNSINCR_SIZE 16
@@ -695,6 +733,7 @@
#define MACB_CAPS_MACB_IS_GEM BIT(31)
#define MACB_CAPS_PCS BIT(24)
#define MACB_CAPS_MACB_IS_GEM_GXL BIT(25)
+#define MACB_CAPS_HIGH_SPEED BIT(26)
#define MACB_GEM7010_IDNUM 0x009
#define MACB_GEM7014_IDNU 0x107
@@ -774,6 +813,7 @@
})
#define MACB_READ_NSR(bp) macb_readl(bp, NSR)
+#define GEM_READ_USX_STATUS(bp) gem_readl(bp, USX_STATUS)
/* struct macb_dma_desc - Hardware DMA descriptor
* @addr: DMA address of data buffer
@@ -1287,6 +1327,7 @@ struct macb {
struct macb_pm_data pm_data;
struct phylink *pl;
struct phylink_config pl_config;
+ u32 serdes_rate;
};
#ifdef CONFIG_MACB_USE_HWSTAMP
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index cf63381d54ee..7b59e64dfe20 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -87,6 +87,20 @@ static struct sifive_fu540_macb_mgmt *mgmt;
#define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
#define MACB_WOL_ENABLED (0x1 << 1)
+enum {
+ HS_MAC_SPEED_100M,
+ HS_MAC_SPEED_1000M,
+ HS_MAC_SPEED_2500M,
+ HS_MAC_SPEED_5000M,
+ HS_MAC_SPEED_10000M,
+ HS_MAC_SPEED_25000M,
+};
+
+enum {
+ MACB_SERDES_RATE_5_PT_15625Gbps = 5,
+ MACB_SERDES_RATE_10_PT_3125Gbps = 10,
+};
+
/* Graceful stop timeouts in us. We should allow up to
* 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
*/
@@ -96,6 +110,8 @@ static struct sifive_fu540_macb_mgmt *mgmt;
#define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
+#define MACB_USX_BLOCK_LOCK_TIMEOUT 1000000 /* in usecs */
+
/* DMA buffer descriptor might be different size
* depends on hardware configuration:
*
@@ -448,24 +464,37 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
if (!clk)
return;
- switch (speed) {
- case SPEED_10:
- rate = 2500000;
- break;
- case SPEED_100:
- rate = 25000000;
- break;
- case SPEED_1000:
- rate = 125000000;
- break;
- case SPEED_2500:
- if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL)
- rate = 312500000;
- else
+ if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
+ switch (bp->serdes_rate) {
+ case MACB_SERDES_RATE_5_PT_15625Gbps:
+ rate = 78125000;
+ break;
+ case MACB_SERDES_RATE_10_PT_3125Gbps:
+ rate = 156250000;
+ break;
+ default:
+ return;
+ }
+ } else {
+ switch (speed) {
+ case SPEED_10:
+ rate = 2500000;
+ break;
+ case SPEED_100:
+ rate = 25000000;
+ break;
+ case SPEED_1000:
rate = 125000000;
- break;
- default:
- return;
+ break;
+ case SPEED_2500:
+ if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL)
+ rate = 312500000;
+ else
+ return;
+ break;
+ default:
+ return;
+ }
}
rate_rounded = clk_round_rate(clk, rate);
@@ -494,6 +523,21 @@ static void gem_phylink_validate(struct phylink_config *pl_config,
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
switch (state->interface) {
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GKR:
+ if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) {
+ phylink_set(mask, 10000baseCR_Full);
+ phylink_set(mask, 10000baseER_Full);
+ phylink_set(mask, 10000baseKR_Full);
+ phylink_set(mask, 10000baseLR_Full);
+ phylink_set(mask, 10000baseLRM_Full);
+ phylink_set(mask, 10000baseSR_Full);
+ phylink_set(mask, 10000baseT_Full);
+ phylink_set(mask, 5000baseT_Full);
+ phylink_set(mask, 2500baseX_Full);
+ phylink_set(mask, 1000baseX_Full);
+ }
+ /* Fall-through */
case PHY_INTERFACE_MODE_SGMII:
if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
phylink_set(mask, 2500baseT_Full);
@@ -583,6 +627,63 @@ static void gem_mac_an_restart(struct phylink_config *pl_config)
}
}
+static inline void gem_set_usx_mac_speed(struct macb *bp, int spd)
+{
+ u32 speed;
+
+ switch (spd) {
+ case SPEED_10000:
+ if (bp->serdes_rate >= MACB_SERDES_RATE_10_PT_3125Gbps) {
+ speed = HS_MAC_SPEED_10000M;
+ } else {
+ netdev_warn(bp->dev, "10G speed isn't supported by HW");
+ netdev_warn(bp->dev, "Setting speed to 1G");
+ speed = HS_MAC_SPEED_1000M;
+ }
+ break;
+ case SPEED_5000:
+ speed = HS_MAC_SPEED_5000M;
+ break;
+ case SPEED_2500:
+ speed = HS_MAC_SPEED_2500M;
+ break;
+ case SPEED_1000:
+ speed = HS_MAC_SPEED_1000M;
+ break;
+ default:
+ case SPEED_100:
+ speed = HS_MAC_SPEED_100M;
+ break;
+ }
+
+ gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, speed,
+ gem_readl(bp, HS_MAC_CONFIG)));
+ gem_writel(bp, USX_CONTROL, GEM_BFINS(USX_CTRL_SPEED, speed,
+ gem_readl(bp, USX_CONTROL)));
+}
+
+static inline void gem_set_mac_speed(struct macb *bp, int speed)
+{
+ switch (speed) {
+ case SPEED_2500:
+ gem_writel(bp, NCFGR, GEM_BIT(GBE) |
+ gem_readl(bp, NCFGR));
+ gem_writel(bp, NCR, GEM_BIT(TWO_PT_FIVE_GIG) |
+ gem_readl(bp, NCR));
+ break;
+ case SPEED_1000:
+ gem_writel(bp, NCFGR, GEM_BIT(GBE) |
+ gem_readl(bp, NCFGR));
+ break;
+ case SPEED_100:
+ macb_writel(bp, NCFGR, MACB_BIT(SPD) |
+ macb_readl(bp, NCFGR));
+ break;
+ default:
+ break;
+ }
+}
+
static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
const struct phylink_link_state *state)
{
@@ -604,24 +705,10 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
reg |= MACB_BIT(FD);
macb_or_gem_writel(bp, NCFGR, reg);
- switch (state->speed) {
- case SPEED_2500:
- gem_writel(bp, NCFGR, GEM_BIT(GBE) |
- gem_readl(bp, NCFGR));
- gem_writel(bp, NCR, GEM_BIT(TWO_PT_FIVE_GIG) |
- gem_readl(bp, NCR));
- break;
- case SPEED_1000:
- gem_writel(bp, NCFGR, GEM_BIT(GBE) |
- gem_readl(bp, NCFGR));
- break;
- case SPEED_100:
- macb_writel(bp, NCFGR, MACB_BIT(SPD) |
- macb_readl(bp, NCFGR));
- break;
- default:
- break;
- }
+ if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII)
+ gem_set_usx_mac_speed(bp, state->speed);
+ else
+ gem_set_mac_speed(bp, state->speed);
bp->speed = state->speed;
bp->duplex = state->duplex;
@@ -2342,7 +2429,16 @@ static void macb_configure_dma(struct macb *bp)
}
}
-static void macb_init_hw(struct macb *bp)
+static int macb_wait_for_usx_block_lock(struct macb *bp)
+{
+ u32 val;
+
+ return readx_poll_timeout(GEM_READ_USX_STATUS, bp, val,
+ val & GEM_BIT(USX_BLOCK_LOCK),
+ 1, MACB_USX_BLOCK_LOCK_TIMEOUT);
+}
+
+static int macb_init_hw(struct macb *bp)
{
struct macb_queue *queue;
unsigned int q;
@@ -2380,6 +2476,23 @@ static void macb_init_hw(struct macb *bp)
if (bp->caps & MACB_CAPS_JUMBO)
bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
+ if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
+ gem_writel(bp, NCR, gem_readl(bp, NCR) |
+ GEM_BIT(ENABLE_HS_MAC));
+ gem_writel(bp, NCFGR, gem_readl(bp, NCFGR) |
+ MACB_BIT(FD) | GEM_BIT(PCSSEL));
+ config = gem_readl(bp, USX_CONTROL);
+ config = GEM_BFINS(SERDES_RATE, bp->serdes_rate, config);
+ config &= ~GEM_BIT(TX_SCR_BYPASS);
+ config &= ~GEM_BIT(RX_SCR_BYPASS);
+ gem_writel(bp, USX_CONTROL, config |
+ GEM_BIT(TX_EN));
+ config = gem_readl(bp, USX_CONTROL);
+ gem_writel(bp, USX_CONTROL, config | GEM_BIT(SIGNAL_OK));
+ if (macb_wait_for_usx_block_lock(bp) < 0)
+ return -ETIMEDOUT;
+ }
+
if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
@@ -2415,6 +2528,7 @@ static void macb_init_hw(struct macb *bp)
/* Enable TX and RX */
macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
+ return 0;
}
/* The hash address register is 64 bits long and takes up two
@@ -2573,7 +2687,9 @@ static int macb_open(struct net_device *dev)
napi_enable(&queue->napi);
bp->macbgem_ops.mog_init_rings(bp);
- macb_init_hw(bp);
+ err = macb_init_hw(bp);
+ if (err)
+ goto init_hw_exit;
/* schedule a link state check */
phylink_start(bp->pl);
@@ -2583,6 +2699,9 @@ static int macb_open(struct net_device *dev)
if (bp->ptp_info)
bp->ptp_info->ptp_init(dev);
+init_hw_exit:
+ if (err)
+ macb_free_consistent(bp);
pm_exit:
if (err) {
pm_runtime_put_sync(&bp->pdev->dev);
@@ -3498,6 +3617,9 @@ static void macb_configure_caps(struct macb *bp,
default:
break;
}
+ dcfg = gem_readl(bp, DCFG12);
+ if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
+ bp->caps |= MACB_CAPS_HIGH_SPEED;
dcfg = gem_readl(bp, DCFG2);
if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
bp->caps |= MACB_CAPS_FIFO_MODE;
@@ -3789,7 +3911,12 @@ static int macb_init(struct platform_device *pdev)
if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
- val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
+ val |= GEM_BIT(SGMIIEN);
+ if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
+ val |= GEM_BIT(PCSSEL);
macb_writel(bp, NCFGR, val);
return 0;
@@ -4488,7 +4615,18 @@ static int macb_probe(struct platform_device *pdev)
} else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) {
u32 interface_supported = 1;
- if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
+ if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
+ if (!(bp->caps & MACB_CAPS_HIGH_SPEED &&
+ bp->caps & MACB_CAPS_PCS))
+ interface_supported = 0;
+
+ if (of_property_read_u32(np, "serdes-rate-gbps",
+ &bp->serdes_rate)) {
+ netdev_err(dev,
+ "GEM serdes_rate not specified");
+ interface_supported = 0;
+ }
+ } else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
if (!(bp->caps & MACB_CAPS_PCS))
--
2.17.1
^ permalink raw reply related
* [PATCH v2 3/5] net: macb: add support for c45 PHY
From: Parshuram Thombare @ 2019-06-19 8:40 UTC (permalink / raw)
To: andrew, nicolas.ferre, davem, f.fainelli
Cc: linux, netdev, hkallweit1, linux-kernel, rafalc, aniljoy, piotrs,
pthombar
In-Reply-To: <1560933600-27626-1-git-send-email-pthombar@cadence.com>
This patch modify MDIO read/write functions to support
communication with C45 PHY.
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
---
drivers/net/ethernet/cadence/macb.h | 15 ++++--
drivers/net/ethernet/cadence/macb_main.c | 61 +++++++++++++++++++-----
2 files changed, 61 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index d7ffbfb2ecc0..34768d35aea1 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -667,10 +667,17 @@
#define GEM_CLK_DIV96 5
/* Constants for MAN register */
-#define MACB_MAN_SOF 1
-#define MACB_MAN_WRITE 1
-#define MACB_MAN_READ 2
-#define MACB_MAN_CODE 2
+#define MACB_MAN_C22_SOF 1
+#define MACB_MAN_C22_WRITE 1
+#define MACB_MAN_C22_READ 2
+#define MACB_MAN_C22_CODE 2
+
+#define MACB_MAN_C45_SOF 0
+#define MACB_MAN_C45_ADDR 0
+#define MACB_MAN_C45_WRITE 1
+#define MACB_MAN_C45_POST_READ_INCR 2
+#define MACB_MAN_C45_READ 3
+#define MACB_MAN_C45_CODE 2
/* Capability mask bits */
#define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0)
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 884d2a4408ad..cf63381d54ee 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -344,11 +344,30 @@ static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
if (status < 0)
goto mdio_read_exit;
- macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
- | MACB_BF(RW, MACB_MAN_READ)
- | MACB_BF(PHYA, mii_id)
- | MACB_BF(REGA, regnum)
- | MACB_BF(CODE, MACB_MAN_CODE)));
+ if (regnum & MII_ADDR_C45) {
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
+ | MACB_BF(RW, MACB_MAN_C45_ADDR)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, (regnum >> 16) & 0x1F)
+ | MACB_BF(DATA, regnum & 0xFFFF)
+ | MACB_BF(CODE, MACB_MAN_C45_CODE)));
+
+ status = macb_mdio_wait_for_idle(bp);
+ if (status < 0)
+ goto mdio_read_exit;
+
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
+ | MACB_BF(RW, MACB_MAN_C45_READ)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, (regnum >> 16) & 0x1F)
+ | MACB_BF(CODE, MACB_MAN_C45_CODE)));
+ } else {
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
+ | MACB_BF(RW, MACB_MAN_C22_READ)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, regnum)
+ | MACB_BF(CODE, MACB_MAN_C22_CODE)));
+ }
status = macb_mdio_wait_for_idle(bp);
if (status < 0)
@@ -377,12 +396,32 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
if (status < 0)
goto mdio_write_exit;
- macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
- | MACB_BF(RW, MACB_MAN_WRITE)
- | MACB_BF(PHYA, mii_id)
- | MACB_BF(REGA, regnum)
- | MACB_BF(CODE, MACB_MAN_CODE)
- | MACB_BF(DATA, value)));
+ if (regnum & MII_ADDR_C45) {
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
+ | MACB_BF(RW, MACB_MAN_C45_ADDR)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, (regnum >> 16) & 0x1F)
+ | MACB_BF(DATA, regnum & 0xFFFF)
+ | MACB_BF(CODE, MACB_MAN_C45_CODE)));
+
+ status = macb_mdio_wait_for_idle(bp);
+ if (status < 0)
+ goto mdio_write_exit;
+
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
+ | MACB_BF(RW, MACB_MAN_C45_WRITE)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, (regnum >> 16) & 0x1F)
+ | MACB_BF(CODE, MACB_MAN_C45_CODE)
+ | MACB_BF(DATA, value)));
+ } else {
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
+ | MACB_BF(RW, MACB_MAN_C22_WRITE)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, regnum)
+ | MACB_BF(CODE, MACB_MAN_C22_CODE)
+ | MACB_BF(DATA, value)));
+ }
status = macb_mdio_wait_for_idle(bp);
if (status < 0)
--
2.17.1
^ permalink raw reply related
* [PATCH v2 2/5] net: macb: add support for sgmii MAC-PHY interface
From: Parshuram Thombare @ 2019-06-19 8:40 UTC (permalink / raw)
To: andrew, nicolas.ferre, davem, f.fainelli
Cc: linux, netdev, hkallweit1, linux-kernel, rafalc, aniljoy, piotrs,
pthombar
In-Reply-To: <1560933600-27626-1-git-send-email-pthombar@cadence.com>
This patch add support for SGMII interface) and
2.5Gbps MAC in Cadence ethernet controller driver.
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
---
drivers/net/ethernet/cadence/macb.h | 76 ++++++++++--
drivers/net/ethernet/cadence/macb_main.c | 151 ++++++++++++++++++++---
2 files changed, 200 insertions(+), 27 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 35ed13236c8b..d7ffbfb2ecc0 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -80,6 +80,7 @@
#define MACB_RBQPH 0x04D4
/* GEM register offsets. */
+#define GEM_NCR 0x0000 /* Network Control */
#define GEM_NCFGR 0x0004 /* Network Config */
#define GEM_USRIO 0x000c /* User IO */
#define GEM_DMACFG 0x0010 /* DMA Configuration */
@@ -159,6 +160,9 @@
#define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
#define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
#define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
+#define GEM_PCS_CTRL 0x0200 /* PCS Control */
+#define GEM_PCS_STATUS 0x0204 /* PCS Status */
+#define GEM_PCS_AN_LP_BASE 0x0214 /* PCS AN LP BASE*/
#define GEM_DCFG1 0x0280 /* Design Config 1 */
#define GEM_DCFG2 0x0284 /* Design Config 2 */
#define GEM_DCFG3 0x0288 /* Design Config 3 */
@@ -274,6 +278,10 @@
#define MACB_IRXFCS_OFFSET 19
#define MACB_IRXFCS_SIZE 1
+/* GEM specific NCR bitfields. */
+#define GEM_TWO_PT_FIVE_GIG_OFFSET 29
+#define GEM_TWO_PT_FIVE_GIG_SIZE 1
+
/* GEM specific NCFGR bitfields. */
#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
#define GEM_GBE_SIZE 1
@@ -326,6 +334,9 @@
#define MACB_MDIO_SIZE 1
#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
#define MACB_IDLE_SIZE 1
+#define MACB_DUPLEX_OFFSET 3
+#define MACB_DUPLEX_SIZE 1
+
/* Bitfields in TSR */
#define MACB_UBR_OFFSET 0 /* Used bit read */
@@ -459,11 +470,37 @@
#define MACB_REV_OFFSET 0
#define MACB_REV_SIZE 16
+/* Bitfields in PCS_CONTROL. */
+#define GEM_PCS_CTRL_RST_OFFSET 15
+#define GEM_PCS_CTRL_RST_SIZE 1
+#define GEM_PCS_CTRL_EN_AN_OFFSET 12
+#define GEM_PCS_CTRL_EN_AN_SIZE 1
+#define GEM_PCS_CTRL_RESTART_AN_OFFSET 9
+#define GEM_PCS_CTRL_RESTART_AN_SIZE 1
+
+/* Bitfields in PCS_STATUS. */
+#define GEM_PCS_STATUS_AN_DONE_OFFSET 5
+#define GEM_PCS_STATUS_AN_DONE_SIZE 1
+#define GEM_PCS_STATUS_AN_SUPPORT_OFFSET 3
+#define GEM_PCS_STATUS_AN_SUPPORT_SIZE 1
+#define GEM_PCS_STATUS_LINK_OFFSET 2
+#define GEM_PCS_STATUS_LINK_SIZE 1
+
+/* Bitfield in PCS_AN_LP_BASE */
+#define GEM_PCS_AN_LP_BASE_LINK_OFFSET 15
+#define GEM_PCS_AN_LP_BASE_LINK_SIZE 1
+#define GEM_PCS_AN_LP_BASE_DUPLEX_OFFSET 12
+#define GEM_PCS_AN_LP_BASE_DUPLEX_SIZE 1
+#define GEM_PCS_AN_LP_BASE_SPEED_OFFSET 10
+#define GEM_PCS_AN_LP_BASE_SPEED_SIZE 2
+
/* Bitfields in DCFG1. */
#define GEM_IRQCOR_OFFSET 23
#define GEM_IRQCOR_SIZE 1
#define GEM_DBWDEF_OFFSET 25
#define GEM_DBWDEF_SIZE 3
+#define GEM_NO_PCS_OFFSET 0
+#define GEM_NO_PCS_SIZE 1
/* Bitfields in DCFG2. */
#define GEM_RX_PKT_BUFF_OFFSET 20
@@ -636,19 +673,32 @@
#define MACB_MAN_CODE 2
/* Capability mask bits */
-#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
-#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
-#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
-#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
-#define MACB_CAPS_USRIO_DISABLED 0x00000010
-#define MACB_CAPS_JUMBO 0x00000020
-#define MACB_CAPS_GEM_HAS_PTP 0x00000040
-#define MACB_CAPS_BD_RD_PREFETCH 0x00000080
-#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
-#define MACB_CAPS_FIFO_MODE 0x10000000
-#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
-#define MACB_CAPS_SG_DISABLED 0x40000000
-#define MACB_CAPS_MACB_IS_GEM 0x80000000
+#define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0)
+#define MACB_CAPS_USRIO_HAS_CLKEN BIT(1)
+#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII BIT(2)
+#define MACB_CAPS_NO_GIGABIT_HALF BIT(3)
+#define MACB_CAPS_USRIO_DISABLED BIT(4)
+#define MACB_CAPS_JUMBO BIT(5)
+#define MACB_CAPS_GEM_HAS_PTP BIT(6)
+#define MACB_CAPS_BD_RD_PREFETCH BIT(7)
+#define MACB_CAPS_NEEDS_RSTONUBR BIT(8)
+#define MACB_CAPS_FIFO_MODE BIT(28)
+#define MACB_CAPS_GIGABIT_MODE_AVAILABLE BIT(29)
+#define MACB_CAPS_SG_DISABLED BIT(30)
+#define MACB_CAPS_MACB_IS_GEM BIT(31)
+#define MACB_CAPS_PCS BIT(24)
+#define MACB_CAPS_MACB_IS_GEM_GXL BIT(25)
+
+#define MACB_GEM7010_IDNUM 0x009
+#define MACB_GEM7014_IDNU 0x107
+#define MACB_GEM7014A_IDNUM 0x207
+#define MACB_GEM7016_IDNUM 0x10a
+#define MACB_GEM7017_IDNUM 0x00a
+#define MACB_GEM7017A_IDNUM 0x20a
+#define MACB_GEM7020_IDNUM 0x003
+#define MACB_GEM7021_IDNUM 0x00c
+#define MACB_GEM7021A_IDNUM 0x20c
+#define MACB_GEM7022_IDNUM 0x00b
/* LSO settings */
#define MACB_LSO_UFO_ENABLE 0x01
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 830af86d3c65..884d2a4408ad 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -403,6 +403,7 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
*/
static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
{
+ struct macb *bp = netdev_priv(dev);
long ferr, rate, rate_rounded;
if (!clk)
@@ -418,6 +419,12 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
case SPEED_1000:
rate = 125000000;
break;
+ case SPEED_2500:
+ if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL)
+ rate = 312500000;
+ else
+ rate = 125000000;
+ break;
default:
return;
}
@@ -448,15 +455,16 @@ static void gem_phylink_validate(struct phylink_config *pl_config,
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
switch (state->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
+ phylink_set(mask, 2500baseT_Full);
+ /* fallthrough */
case PHY_INTERFACE_MODE_GMII:
case PHY_INTERFACE_MODE_RGMII:
if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) {
phylink_set(mask, 1000baseT_Full);
- phylink_set(mask, 1000baseX_Full);
- if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) {
- phylink_set(mask, 1000baseT_Half);
+ if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
phylink_set(mask, 1000baseT_Half);
- }
}
/* fallthrough */
case PHY_INTERFACE_MODE_MII:
@@ -466,6 +474,16 @@ static void gem_phylink_validate(struct phylink_config *pl_config,
phylink_set(mask, 100baseT_Half);
phylink_set(mask, 100baseT_Full);
break;
+
+ case PHY_INTERFACE_MODE_2500BASEX:
+ if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
+ phylink_set(mask, 2500baseX_Full);
+ /* fallthrough */
+ case PHY_INTERFACE_MODE_1000BASEX:
+ if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
+ phylink_set(mask, 1000baseX_Full);
+ break;
+
default:
break;
}
@@ -480,13 +498,52 @@ static int gem_phylink_mac_link_state(struct phylink_config *pl_config,
{
struct net_device *netdev = to_net_dev(pl_config->dev);
struct macb *bp = netdev_priv(netdev);
+ u32 status;
- state->speed = bp->speed;
- state->duplex = bp->duplex;
- state->link = bp->link;
+ if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ status = gem_readl(bp, PCS_STATUS);
+ state->an_complete = GEM_BFEXT(PCS_STATUS_AN_DONE, status);
+ status = gem_readl(bp, PCS_AN_LP_BASE);
+ switch (GEM_BFEXT(PCS_AN_LP_BASE_SPEED, status)) {
+ case 0:
+ state->speed = SPEED_10;
+ break;
+ case 1:
+ state->speed = SPEED_100;
+ break;
+ case 2:
+ state->speed = SPEED_1000;
+ break;
+ default:
+ break;
+ }
+ state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR));
+ state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR));
+ } else if (bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
+ state->speed = SPEED_2500;
+ state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR));
+ state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR));
+ } else if (bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ state->speed = SPEED_1000;
+ state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR));
+ state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR));
+ }
return 1;
}
+static void gem_mac_an_restart(struct phylink_config *pl_config)
+{
+ struct net_device *netdev = to_net_dev(pl_config->dev);
+ struct macb *bp = netdev_priv(netdev);
+
+ if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
+ gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) |
+ GEM_BIT(PCS_CTRL_RESTART_AN));
+ }
+}
+
static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
const struct phylink_link_state *state)
{
@@ -506,18 +563,26 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
reg &= ~GEM_BIT(GBE);
if (state->duplex)
reg |= MACB_BIT(FD);
+ macb_or_gem_writel(bp, NCFGR, reg);
switch (state->speed) {
+ case SPEED_2500:
+ gem_writel(bp, NCFGR, GEM_BIT(GBE) |
+ gem_readl(bp, NCFGR));
+ gem_writel(bp, NCR, GEM_BIT(TWO_PT_FIVE_GIG) |
+ gem_readl(bp, NCR));
+ break;
case SPEED_1000:
- reg |= GEM_BIT(GBE);
+ gem_writel(bp, NCFGR, GEM_BIT(GBE) |
+ gem_readl(bp, NCFGR));
break;
case SPEED_100:
- reg |= MACB_BIT(SPD);
+ macb_writel(bp, NCFGR, MACB_BIT(SPD) |
+ macb_readl(bp, NCFGR));
break;
default:
break;
}
- macb_or_gem_writel(bp, NCFGR, reg);
bp->speed = state->speed;
bp->duplex = state->duplex;
@@ -555,6 +620,7 @@ static void gem_mac_link_down(struct phylink_config *pl_config,
static const struct phylink_mac_ops gem_phylink_ops = {
.validate = gem_phylink_validate,
.mac_link_state = gem_phylink_mac_link_state,
+ .mac_an_restart = gem_mac_an_restart,
.mac_config = gem_mac_config,
.mac_link_up = gem_mac_link_up,
.mac_link_down = gem_mac_link_down,
@@ -2248,7 +2314,9 @@ static void macb_init_hw(struct macb *bp)
macb_set_hwaddr(bp);
config = macb_mdc_clk_div(bp);
- if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
+ if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
config |= MACB_BIT(PAE); /* PAuse Enable */
@@ -2273,6 +2341,17 @@ static void macb_init_hw(struct macb *bp)
if (bp->caps & MACB_CAPS_JUMBO)
bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
+ if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
+ //Enable PCS AN
+ gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) |
+ GEM_BIT(PCS_CTRL_EN_AN));
+ //Reset PCS block
+ gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) |
+ GEM_BIT(PCS_CTRL_RST));
+ }
+
macb_configure_dma(bp);
/* Initialize TX and RX buffers */
@@ -3364,6 +3443,22 @@ static void macb_configure_caps(struct macb *bp,
dcfg = gem_readl(bp, DCFG1);
if (GEM_BFEXT(IRQCOR, dcfg) == 0)
bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
+ if (GEM_BFEXT(NO_PCS, dcfg) == 0)
+ bp->caps |= MACB_CAPS_PCS;
+ switch (MACB_BFEXT(IDNUM, macb_readl(bp, MID))) {
+ case MACB_GEM7016_IDNUM:
+ case MACB_GEM7017_IDNUM:
+ case MACB_GEM7017A_IDNUM:
+ case MACB_GEM7020_IDNUM:
+ case MACB_GEM7021_IDNUM:
+ case MACB_GEM7021A_IDNUM:
+ case MACB_GEM7022_IDNUM:
+ bp->caps |= MACB_CAPS_USRIO_DISABLED;
+ bp->caps |= MACB_CAPS_MACB_IS_GEM_GXL;
+ break;
+ default:
+ break;
+ }
dcfg = gem_readl(bp, DCFG2);
if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
bp->caps |= MACB_CAPS_FIFO_MODE;
@@ -3652,7 +3747,9 @@ static int macb_init(struct platform_device *pdev)
/* Set MII management clock divider */
val = macb_mdc_clk_div(bp);
val |= macb_dbw(bp);
- if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
+ if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
macb_writel(bp, NCFGR, val);
@@ -4346,11 +4443,37 @@ static int macb_probe(struct platform_device *pdev)
}
phy_mode = of_get_phy_mode(np);
- if (phy_mode < 0)
+ if (phy_mode < 0) {
/* not found in DT, MII by default */
bp->phy_interface = PHY_INTERFACE_MODE_MII;
- else
+ } else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) {
+ u32 interface_supported = 1;
+
+ if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
+ phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
+ phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
+ if (!(bp->caps & MACB_CAPS_PCS))
+ interface_supported = 0;
+ } else if (phy_mode == PHY_INTERFACE_MODE_GMII ||
+ phy_mode == PHY_INTERFACE_MODE_RGMII) {
+ if (!macb_is_gem(bp))
+ interface_supported = 0;
+ } else if (phy_mode != PHY_INTERFACE_MODE_RMII &&
+ phy_mode != PHY_INTERFACE_MODE_MII) {
+ /* Add new mode before this */
+ interface_supported = 0;
+ }
+
+ if (!interface_supported) {
+ netdev_err(dev, "Phy mode %s not supported",
+ phy_modes(phy_mode));
+ goto err_out_free_netdev;
+ }
+
bp->phy_interface = phy_mode;
+ } else {
+ bp->phy_interface = phy_mode;
+ }
/* IP specific init */
err = init(pdev);
--
2.17.1
^ permalink raw reply related
* [PATCH v2 1/5] net: macb: add phylink support
From: Parshuram Thombare @ 2019-06-19 8:40 UTC (permalink / raw)
To: andrew, nicolas.ferre, davem, f.fainelli
Cc: linux, netdev, hkallweit1, linux-kernel, rafalc, aniljoy, piotrs,
pthombar
In-Reply-To: <1560933600-27626-1-git-send-email-pthombar@cadence.com>
This patch replace phylib API's by phylink API's.
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
---
drivers/net/ethernet/cadence/Kconfig | 2 +-
drivers/net/ethernet/cadence/macb.h | 3 +
drivers/net/ethernet/cadence/macb_main.c | 312 +++++++++++++----------
3 files changed, 182 insertions(+), 135 deletions(-)
diff --git a/drivers/net/ethernet/cadence/Kconfig b/drivers/net/ethernet/cadence/Kconfig
index 1766697c9c5a..d71411a71587 100644
--- a/drivers/net/ethernet/cadence/Kconfig
+++ b/drivers/net/ethernet/cadence/Kconfig
@@ -22,7 +22,7 @@ if NET_VENDOR_CADENCE
config MACB
tristate "Cadence MACB/GEM support"
depends on HAS_DMA
- select PHYLIB
+ select PHYLINK
---help---
The Cadence MACB ethernet interface is found on many Atmel AT32 and
AT91 parts. This driver also supports the Cadence GEM (Gigabit
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 00ee5e8e0ff0..35ed13236c8b 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -14,6 +14,7 @@
#include <linux/ptp_clock_kernel.h>
#include <linux/net_tstamp.h>
#include <linux/interrupt.h>
+#include <linux/phylink.h>
#if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
#define MACB_EXT_DESC
@@ -1227,6 +1228,8 @@ struct macb {
u32 rx_intr_mask;
struct macb_pm_data pm_data;
+ struct phylink *pl;
+ struct phylink_config pl_config;
};
#ifdef CONFIG_MACB_USE_HWSTAMP
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index c545c5b435d8..830af86d3c65 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -39,6 +39,7 @@
#include <linux/tcp.h>
#include <linux/iopoll.h>
#include <linux/pm_runtime.h>
+#include <linux/phylink.h>
#include "macb.h"
/* This structure is only used for MACB on SiFive FU540 devices */
@@ -438,115 +439,150 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
netdev_err(dev, "adjusting tx_clk failed.\n");
}
-static void macb_handle_link_change(struct net_device *dev)
+static void gem_phylink_validate(struct phylink_config *pl_config,
+ unsigned long *supported,
+ struct phylink_link_state *state)
{
- struct macb *bp = netdev_priv(dev);
- struct phy_device *phydev = dev->phydev;
- unsigned long flags;
- int status_change = 0;
+ struct net_device *netdev = to_net_dev(pl_config->dev);
+ struct macb *bp = netdev_priv(netdev);
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_GMII:
+ case PHY_INTERFACE_MODE_RGMII:
+ if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) {
+ phylink_set(mask, 1000baseT_Full);
+ phylink_set(mask, 1000baseX_Full);
+ if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) {
+ phylink_set(mask, 1000baseT_Half);
+ phylink_set(mask, 1000baseT_Half);
+ }
+ }
+ /* fallthrough */
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_RMII:
+ phylink_set(mask, 10baseT_Half);
+ phylink_set(mask, 10baseT_Full);
+ phylink_set(mask, 100baseT_Half);
+ phylink_set(mask, 100baseT_Full);
+ break;
+ default:
+ break;
+ }
- spin_lock_irqsave(&bp->lock, flags);
+ bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
+ bitmap_and(state->advertising, state->advertising, mask,
+ __ETHTOOL_LINK_MODE_MASK_NBITS);
+}
- if (phydev->link) {
- if ((bp->speed != phydev->speed) ||
- (bp->duplex != phydev->duplex)) {
- u32 reg;
+static int gem_phylink_mac_link_state(struct phylink_config *pl_config,
+ struct phylink_link_state *state)
+{
+ struct net_device *netdev = to_net_dev(pl_config->dev);
+ struct macb *bp = netdev_priv(netdev);
- reg = macb_readl(bp, NCFGR);
- reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
- if (macb_is_gem(bp))
- reg &= ~GEM_BIT(GBE);
+ state->speed = bp->speed;
+ state->duplex = bp->duplex;
+ state->link = bp->link;
+ return 1;
+}
- if (phydev->duplex)
- reg |= MACB_BIT(FD);
- if (phydev->speed == SPEED_100)
- reg |= MACB_BIT(SPD);
- if (phydev->speed == SPEED_1000 &&
- bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
- reg |= GEM_BIT(GBE);
+static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ struct net_device *netdev = to_net_dev(pl_config->dev);
+ struct macb *bp = netdev_priv(netdev);
+ unsigned long flags;
- macb_or_gem_writel(bp, NCFGR, reg);
+ spin_lock_irqsave(&bp->lock, flags);
- bp->speed = phydev->speed;
- bp->duplex = phydev->duplex;
- status_change = 1;
- }
- }
+ if (bp->speed != state->speed ||
+ bp->duplex != state->duplex) {
+ u32 reg;
- if (phydev->link != bp->link) {
- if (!phydev->link) {
- bp->speed = 0;
- bp->duplex = -1;
+ reg = macb_readl(bp, NCFGR);
+ reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
+ if (macb_is_gem(bp))
+ reg &= ~GEM_BIT(GBE);
+ if (state->duplex)
+ reg |= MACB_BIT(FD);
+
+ switch (state->speed) {
+ case SPEED_1000:
+ reg |= GEM_BIT(GBE);
+ break;
+ case SPEED_100:
+ reg |= MACB_BIT(SPD);
+ break;
+ default:
+ break;
}
- bp->link = phydev->link;
+ macb_or_gem_writel(bp, NCFGR, reg);
+
+ bp->speed = state->speed;
+ bp->duplex = state->duplex;
- status_change = 1;
+ if (state->link)
+ macb_set_tx_clk(bp->tx_clk, state->speed, netdev);
}
spin_unlock_irqrestore(&bp->lock, flags);
+}
- if (status_change) {
- if (phydev->link) {
- /* Update the TX clock rate if and only if the link is
- * up and there has been a link change.
- */
- macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
+static void gem_mac_link_up(struct phylink_config *pl_config, unsigned int mode,
+ phy_interface_t interface, struct phy_device *phy)
+{
+ struct net_device *netdev = to_net_dev(pl_config->dev);
+ struct macb *bp = netdev_priv(netdev);
- netif_carrier_on(dev);
- netdev_info(dev, "link up (%d/%s)\n",
- phydev->speed,
- phydev->duplex == DUPLEX_FULL ?
- "Full" : "Half");
- } else {
- netif_carrier_off(dev);
- netdev_info(dev, "link down\n");
- }
- }
+ bp->link = 1;
+ /* Enable TX and RX */
+ macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
+}
+
+static void gem_mac_link_down(struct phylink_config *pl_config,
+ unsigned int mode, phy_interface_t interface)
+{
+ struct net_device *netdev = to_net_dev(pl_config->dev);
+ struct macb *bp = netdev_priv(netdev);
+
+ bp->link = 0;
+ /* Disable TX and RX */
+ macb_writel(bp, NCR,
+ macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE)));
}
+static const struct phylink_mac_ops gem_phylink_ops = {
+ .validate = gem_phylink_validate,
+ .mac_link_state = gem_phylink_mac_link_state,
+ .mac_config = gem_mac_config,
+ .mac_link_up = gem_mac_link_up,
+ .mac_link_down = gem_mac_link_down,
+};
+
/* based on au1000_eth. c*/
static int macb_mii_probe(struct net_device *dev)
{
struct macb *bp = netdev_priv(dev);
struct phy_device *phydev;
struct device_node *np;
- int ret, i;
+ int ret;
np = bp->pdev->dev.of_node;
ret = 0;
- if (np) {
- if (of_phy_is_fixed_link(np)) {
- bp->phy_node = of_node_get(np);
- } else {
- bp->phy_node = of_parse_phandle(np, "phy-handle", 0);
- /* fallback to standard phy registration if no
- * phy-handle was found nor any phy found during
- * dt phy registration
- */
- if (!bp->phy_node && !phy_find_first(bp->mii_bus)) {
- for (i = 0; i < PHY_MAX_ADDR; i++) {
- phydev = mdiobus_scan(bp->mii_bus, i);
- if (IS_ERR(phydev) &&
- PTR_ERR(phydev) != -ENODEV) {
- ret = PTR_ERR(phydev);
- break;
- }
- }
-
- if (ret)
- return -ENODEV;
- }
- }
+ bp->pl_config.dev = &dev->dev;
+ bp->pl_config.type = PHYLINK_NETDEV;
+ bp->pl = phylink_create(&bp->pl_config, of_fwnode_handle(np),
+ bp->phy_interface, &gem_phylink_ops);
+ if (IS_ERR(bp->pl)) {
+ netdev_err(dev,
+ "error creating PHYLINK: %ld\n", PTR_ERR(bp->pl));
+ return PTR_ERR(bp->pl);
}
- if (bp->phy_node) {
- phydev = of_phy_connect(dev, bp->phy_node,
- &macb_handle_link_change, 0,
- bp->phy_interface);
- if (!phydev)
- return -ENODEV;
- } else {
+ ret = phylink_of_phy_connect(bp->pl, np, 0);
+ if (ret == -ENODEV && bp->mii_bus) {
phydev = phy_find_first(bp->mii_bus);
if (!phydev) {
netdev_err(dev, "no PHY found\n");
@@ -554,29 +590,18 @@ static int macb_mii_probe(struct net_device *dev)
}
/* attach the mac to the phy */
- ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
- bp->phy_interface);
+ ret = phylink_connect_phy(bp->pl, phydev);
if (ret) {
netdev_err(dev, "Could not attach to PHY\n");
return ret;
}
}
- /* mask with MAC supported features */
- if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
- phy_set_max_speed(phydev, SPEED_1000);
- else
- phy_set_max_speed(phydev, SPEED_100);
-
- if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
- phy_remove_link_mode(phydev,
- ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
-
bp->link = 0;
bp->speed = 0;
bp->duplex = -1;
- return 0;
+ return ret;
}
static int macb_mii_init(struct macb *bp)
@@ -604,17 +629,7 @@ static int macb_mii_init(struct macb *bp)
dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
np = bp->pdev->dev.of_node;
- if (np && of_phy_is_fixed_link(np)) {
- if (of_phy_register_fixed_link(np) < 0) {
- dev_err(&bp->pdev->dev,
- "broken fixed-link specification %pOF\n", np);
- goto err_out_free_mdiobus;
- }
-
- err = mdiobus_register(bp->mii_bus);
- } else {
- err = of_mdiobus_register(bp->mii_bus, np);
- }
+ err = of_mdiobus_register(bp->mii_bus, np);
if (err)
goto err_out_free_fixed_link;
@@ -630,7 +645,6 @@ static int macb_mii_init(struct macb *bp)
err_out_free_fixed_link:
if (np && of_phy_is_fixed_link(np))
of_phy_deregister_fixed_link(np);
-err_out_free_mdiobus:
of_node_put(bp->phy_node);
mdiobus_free(bp->mii_bus);
err_out:
@@ -2422,7 +2436,7 @@ static int macb_open(struct net_device *dev)
netif_carrier_off(dev);
/* if the phy is not yet register, retry later*/
- if (!dev->phydev) {
+ if (!bp->pl) {
err = -EAGAIN;
goto pm_exit;
}
@@ -2444,7 +2458,7 @@ static int macb_open(struct net_device *dev)
macb_init_hw(bp);
/* schedule a link state check */
- phy_start(dev->phydev);
+ phylink_start(bp->pl);
netif_tx_start_all_queues(dev);
@@ -2471,8 +2485,8 @@ static int macb_close(struct net_device *dev)
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
napi_disable(&queue->napi);
- if (dev->phydev)
- phy_stop(dev->phydev);
+ if (bp->pl)
+ phylink_stop(bp->pl);
spin_lock_irqsave(&bp->lock, flags);
macb_reset_hw(bp);
@@ -3161,6 +3175,29 @@ static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
return ret;
}
+static int gem_ethtool_get_link_ksettings(struct net_device *netdev,
+ struct ethtool_link_ksettings *cmd)
+{
+ struct macb *bp = netdev_priv(netdev);
+
+ if (!bp->pl)
+ return -ENOTSUPP;
+
+ return phylink_ethtool_ksettings_get(bp->pl, cmd);
+}
+
+static int
+gem_ethtool_set_link_ksettings(struct net_device *netdev,
+ const struct ethtool_link_ksettings *cmd)
+{
+ struct macb *bp = netdev_priv(netdev);
+
+ if (!bp->pl)
+ return -ENOTSUPP;
+
+ return phylink_ethtool_ksettings_set(bp->pl, cmd);
+}
+
static const struct ethtool_ops macb_ethtool_ops = {
.get_regs_len = macb_get_regs_len,
.get_regs = macb_get_regs,
@@ -3168,8 +3205,8 @@ static const struct ethtool_ops macb_ethtool_ops = {
.get_ts_info = ethtool_op_get_ts_info,
.get_wol = macb_get_wol,
.set_wol = macb_set_wol,
- .get_link_ksettings = phy_ethtool_get_link_ksettings,
- .set_link_ksettings = phy_ethtool_set_link_ksettings,
+ .get_link_ksettings = gem_ethtool_get_link_ksettings,
+ .set_link_ksettings = gem_ethtool_set_link_ksettings,
.get_ringparam = macb_get_ringparam,
.set_ringparam = macb_set_ringparam,
};
@@ -3182,8 +3219,8 @@ static const struct ethtool_ops gem_ethtool_ops = {
.get_ethtool_stats = gem_get_ethtool_stats,
.get_strings = gem_get_ethtool_strings,
.get_sset_count = gem_get_sset_count,
- .get_link_ksettings = phy_ethtool_get_link_ksettings,
- .set_link_ksettings = phy_ethtool_set_link_ksettings,
+ .get_link_ksettings = gem_ethtool_get_link_ksettings,
+ .set_link_ksettings = gem_ethtool_set_link_ksettings,
.get_ringparam = macb_get_ringparam,
.set_ringparam = macb_set_ringparam,
.get_rxnfc = gem_get_rxnfc,
@@ -3192,17 +3229,16 @@ static const struct ethtool_ops gem_ethtool_ops = {
static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
- struct phy_device *phydev = dev->phydev;
struct macb *bp = netdev_priv(dev);
if (!netif_running(dev))
return -EINVAL;
- if (!phydev)
+ if (!bp->pl)
return -ENODEV;
if (!bp->ptp_info)
- return phy_mii_ioctl(phydev, rq, cmd);
+ return phylink_mii_ioctl(bp->pl, rq, cmd);
switch (cmd) {
case SIOCSHWTSTAMP:
@@ -3210,7 +3246,7 @@ static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
case SIOCGHWTSTAMP:
return bp->ptp_info->get_hwtst(dev, rq);
default:
- return phy_mii_ioctl(phydev, rq, cmd);
+ return phylink_mii_ioctl(bp->pl, rq, cmd);
}
}
@@ -3710,7 +3746,7 @@ static int at91ether_open(struct net_device *dev)
MACB_BIT(HRESP));
/* schedule a link state check */
- phy_start(dev->phydev);
+ phylink_start(lp->pl);
netif_start_queue(dev);
@@ -4183,13 +4219,12 @@ static int macb_probe(struct platform_device *pdev)
struct clk *tsu_clk = NULL;
unsigned int queue_mask, num_queues;
bool native_io;
- struct phy_device *phydev;
struct net_device *dev;
struct resource *regs;
void __iomem *mem;
const char *mac;
struct macb *bp;
- int err, val;
+ int err, val, phy_mode;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mem = devm_ioremap_resource(&pdev->dev, regs);
@@ -4310,12 +4345,12 @@ static int macb_probe(struct platform_device *pdev)
macb_get_hwaddr(bp);
}
- err = of_get_phy_mode(np);
- if (err < 0)
+ phy_mode = of_get_phy_mode(np);
+ if (phy_mode < 0)
/* not found in DT, MII by default */
bp->phy_interface = PHY_INTERFACE_MODE_MII;
else
- bp->phy_interface = err;
+ bp->phy_interface = phy_mode;
/* IP specific init */
err = init(pdev);
@@ -4326,8 +4361,6 @@ static int macb_probe(struct platform_device *pdev)
if (err)
goto err_out_free_netdev;
- phydev = dev->phydev;
-
netif_carrier_off(dev);
err = register_netdev(dev);
@@ -4339,7 +4372,8 @@ static int macb_probe(struct platform_device *pdev)
tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
(unsigned long)bp);
- phy_attached_info(phydev);
+ if (dev->phydev)
+ phy_attached_info(dev->phydev);
netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
@@ -4351,7 +4385,9 @@ static int macb_probe(struct platform_device *pdev)
return 0;
err_out_unregister_mdio:
- phy_disconnect(dev->phydev);
+ rtnl_lock();
+ phylink_disconnect_phy(bp->pl);
+ rtnl_unlock();
mdiobus_unregister(bp->mii_bus);
of_node_put(bp->phy_node);
if (np && of_phy_is_fixed_link(np))
@@ -4385,13 +4421,18 @@ static int macb_remove(struct platform_device *pdev)
if (dev) {
bp = netdev_priv(dev);
- if (dev->phydev)
- phy_disconnect(dev->phydev);
+ if (bp->pl) {
+ rtnl_lock();
+ phylink_disconnect_phy(bp->pl);
+ rtnl_unlock();
+ }
mdiobus_unregister(bp->mii_bus);
if (np && of_phy_is_fixed_link(np))
of_phy_deregister_fixed_link(np);
dev->phydev = NULL;
mdiobus_free(bp->mii_bus);
+ if (bp->pl)
+ phylink_destroy(bp->pl);
unregister_netdev(dev);
pm_runtime_disable(&pdev->dev);
@@ -4434,8 +4475,9 @@ static int __maybe_unused macb_suspend(struct device *dev)
for (q = 0, queue = bp->queues; q < bp->num_queues;
++q, ++queue)
napi_disable(&queue->napi);
- phy_stop(netdev->phydev);
- phy_suspend(netdev->phydev);
+ phylink_stop(bp->pl);
+ if (netdev->phydev)
+ phy_suspend(netdev->phydev);
spin_lock_irqsave(&bp->lock, flags);
macb_reset_hw(bp);
spin_unlock_irqrestore(&bp->lock, flags);
@@ -4483,9 +4525,11 @@ static int __maybe_unused macb_resume(struct device *dev)
for (q = 0, queue = bp->queues; q < bp->num_queues;
++q, ++queue)
napi_enable(&queue->napi);
- phy_resume(netdev->phydev);
- phy_init_hw(netdev->phydev);
- phy_start(netdev->phydev);
+ if (netdev->phydev) {
+ phy_resume(netdev->phydev);
+ phy_init_hw(netdev->phydev);
+ }
+ phylink_start(bp->pl);
}
bp->macbgem_ops.mog_init_rings(bp);
--
2.17.1
^ permalink raw reply related
* [PATCH v2 0/5] net: macb: cover letter
From: Parshuram Thombare @ 2019-06-19 8:40 UTC (permalink / raw)
To: andrew, nicolas.ferre, davem, f.fainelli
Cc: linux, netdev, hkallweit1, linux-kernel, rafalc, aniljoy, piotrs,
pthombar
Hello !,
This is second version of patch set containing following patches
for Cadence ethernet controller driver.
1. 0001-net-macb-add-phylink-support.patch
Replace phylib API's with phylink API's.
2. 0002-net-macb-add-support-for-sgmii-MAC-PHY-interface.patch
This patch add support for SGMII mode.
3. 0004-net-macb-add-support-for-c45-PHY.patch
This patch is to support C45 PHY.
4. 0005-net-macb-add-support-for-high-speed-interface
This patch add support for 10G USXGMII PCS in fixed mode.
5. 0006-net-macb-parameter-added-to-cadence-ethernet-controller-DT-binding
New parameter added to Cadence ethernet controller DT binding
for USXGMII interface.
Changes:
1. Dropped patch configuring TI PHY DP83867 from
Cadence PCI wrapper driver.
2. Removed code registering emulated PHY for fixed mode.
3. Code reformatting as per Andrew's and Floren's suggestions.
Regards,
Parshuram Thombare
Parshuram Thombare (5):
net: macb: add phylink support
net: macb: add support for sgmii MAC-PHY interface
net: macb: add support for c45 PHY
net: macb: add support for high speed interface
net: macb: parameter added to cadence ethernet controller DT binding
.../devicetree/bindings/net/macb.txt | 3 +
drivers/net/ethernet/cadence/Kconfig | 2 +-
drivers/net/ethernet/cadence/macb.h | 135 +++-
drivers/net/ethernet/cadence/macb_main.c | 668 +++++++++++++-----
4 files changed, 628 insertions(+), 180 deletions(-)
--
2.17.1
^ permalink raw reply
* RE: [PATCH v2 1/6] net: macb: add phylink support
From: Parshuram Raju Thombare @ 2019-06-19 8:28 UTC (permalink / raw)
To: Andrew Lunn
Cc: nicolas.ferre@microchip.com, davem@davemloft.net,
f.fainelli@gmail.com, netdev@vger.kernel.org,
hkallweit1@gmail.com, linux-kernel@vger.kernel.org,
Rafal Ciepiela, Anil Joy Varughese, Piotr Sroka, Russell King
In-Reply-To: <20190618213259.GB18352@lunn.ch>
Hi Andrew,
Sure, I will Cc Russel King in next version of patch series.
Regards,
Parshuram Thombare
>-----Original Message-----
>From: Andrew Lunn <andrew@lunn.ch>
>Sent: Wednesday, June 19, 2019 3:03 AM
>To: Parshuram Raju Thombare <pthombar@cadence.com>
>Cc: nicolas.ferre@microchip.com; davem@davemloft.net;
>f.fainelli@gmail.com; netdev@vger.kernel.org; hkallweit1@gmail.com; linux-
>kernel@vger.kernel.org; Rafal Ciepiela <rafalc@cadence.com>; Anil Joy
>Varughese <aniljoy@cadence.com>; Piotr Sroka <piotrs@cadence.com>;
>Russell King <rmk+kernel@arm.linux.org.uk>
>Subject: Re: [PATCH v2 1/6] net: macb: add phylink support
>
>EXTERNAL MAIL
>
>
>On Tue, Jun 18, 2019 at 07:41:05PM +0100, Parshuram Thombare wrote:
>> This patch replace phylib API's by phylink API's.
>
>Hi Parshuram
>
>When you repost as a proper threaded patchset, please Cc: Russell King, the
>phylink maintainer.
>
> Thanks
> Andrew
^ permalink raw reply
* Re: [PATCH] mm: mempolicy: handle vma with unmovable pages mapped correctly in mbind
From: Vlastimil Babka @ 2019-06-19 8:22 UTC (permalink / raw)
To: Michal Hocko, Yang Shi
Cc: akpm, mgorman, linux-mm, linux-kernel, Eric Dumazet,
David S. Miller, netdev
In-Reply-To: <20190619052133.GB2968@dhcp22.suse.cz>
On 6/19/19 7:21 AM, Michal Hocko wrote:
> On Tue 18-06-19 14:13:16, Yang Shi wrote:
> [...]
>>
>> I used to have !__PageMovable(page), but it was removed since the
>> aforementioned reason. I could add it back.
>>
>> For the temporary off LRU page, I did a quick search, it looks the most
>> paths have to acquire mmap_sem, so it can't race with us here. Page
>> reclaim/compaction looks like the only race. But, since the mapping should
>> be preserved even though the page is off LRU temporarily unless the page is
>> reclaimed, so we should be able to exclude temporary off LRU pages by
>> calling page_mapping() and page_anon_vma().
>>
>> So, the fix may look like:
>>
>> if (!PageLRU(head) && !__PageMovable(page)) {
>> if (!(page_mapping(page) || page_anon_vma(page)))
>> return -EIO;
>
> This is getting even more muddy TBH. Is there any reason that we have to
> handle this problem during the isolation phase rather the migration?
I think it was already said that if pages can't be isolated, then
migration phase won't process them, so they're just ignored.
However I think the patch is wrong to abort immediately when
encountering such page that cannot be isolated (AFAICS). IMHO it should
still try to migrate everything it can, and only then return -EIO.
^ permalink raw reply
* Re: [PATCH] mm: mempolicy: handle vma with unmovable pages mapped correctly in mbind
From: Vlastimil Babka @ 2019-06-19 8:18 UTC (permalink / raw)
To: Yang Shi, Michal Hocko
Cc: akpm, mgorman, linux-mm, linux-kernel, Eric Dumazet,
David S. Miller, netdev
In-Reply-To: <cf33b724-fdd5-58e3-c06a-1bc563525311@linux.alibaba.com>
On 6/18/19 7:06 PM, Yang Shi wrote:
> The BUG_ON was removed by commit
> d44d363f65780f2ac2ec672164555af54896d40d ("mm: don't assume anonymous
> pages have SwapBacked flag") since 4.12.
Perhaps that commit should be sent to stable@ ? Although with
VM_BUG_ON() this is less critical than plain BUG_ON().
^ permalink raw reply
* Re: [PATCH mlx5-next 11/15] RDMA/mlx5: Add vport metadata matching for IB representors
From: Leon Romanovsky @ 2019-06-19 8:12 UTC (permalink / raw)
To: Mark Bloch
Cc: Jianbo Liu, Saeed Mahameed, netdev@vger.kernel.org,
linux-rdma@vger.kernel.org, Roi Dayan
In-Reply-To: <ac23c3ea-3ea7-2a5b-5fc6-aece0aed0b54@mellanox.com>
On Wed, Jun 19, 2019 at 07:58:51AM +0000, Mark Bloch wrote:
>
>
> On 6/19/2019 00:43, Leon Romanovsky wrote:
> > On Wed, Jun 19, 2019 at 07:26:54AM +0000, Mark Bloch wrote:
> >>
> >>
> >> On 6/18/2019 23:51, Leon Romanovsky wrote:
> >>> On Wed, Jun 19, 2019 at 06:40:16AM +0000, Jianbo Liu wrote:
> >>>> The 06/19/2019 13:04, Leon Romanovsky wrote:
> >>>>> On Wed, Jun 19, 2019 at 04:44:26AM +0000, Jianbo Liu wrote:
> >>>>>> The 06/18/2019 18:19, Leon Romanovsky wrote:
> >>>>>>> On Mon, Jun 17, 2019 at 07:23:30PM +0000, Saeed Mahameed wrote:
> >>>>>>>> From: Jianbo Liu <jianbol@mellanox.com>
> >>>>>>>>
> >>>>>>>> If vport metadata matching is enabled in eswitch, the rule created
> >>>>>>>> must be changed to match on the metadata, instead of source port.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Jianbo Liu <jianbol@mellanox.com>
> >>>>>>>> Reviewed-by: Roi Dayan <roid@mellanox.com>
> >>>>>>>> Reviewed-by: Mark Bloch <markb@mellanox.com>
> >>>>>>>> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
> >>>>>>>> ---
> >>>>>>>> drivers/infiniband/hw/mlx5/ib_rep.c | 11 +++++++
> >>>>>>>> drivers/infiniband/hw/mlx5/ib_rep.h | 16 ++++++++++
> >>>>>>>> drivers/infiniband/hw/mlx5/main.c | 45 +++++++++++++++++++++++------
> >>>>>>>> 3 files changed, 63 insertions(+), 9 deletions(-)
> >>>>>>>>
> >>>>>>>> diff --git a/drivers/infiniband/hw/mlx5/ib_rep.c b/drivers/infiniband/hw/mlx5/ib_rep.c
> >>>>>>>> index 22e651cb5534..d4ed611de35d 100644
> >>>>>>>> --- a/drivers/infiniband/hw/mlx5/ib_rep.c
> >>>>>>>> +++ b/drivers/infiniband/hw/mlx5/ib_rep.c
> >>>>>>>> @@ -131,6 +131,17 @@ struct mlx5_eswitch_rep *mlx5_ib_vport_rep(struct mlx5_eswitch *esw, int vport)
> >>>>>>>> return mlx5_eswitch_vport_rep(esw, vport);
> >>>>>>>> }
> >>>>>>>>
> >>>>>>>> +u32 mlx5_ib_eswitch_vport_match_metadata_enabled(struct mlx5_eswitch *esw)
> >>>>>>>> +{
> >>>>>>>> + return mlx5_eswitch_vport_match_metadata_enabled(esw);
> >>>>>>>> +}
> >>>>>>>> +
> >>>>>>>> +u32 mlx5_ib_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
> >>>>>>>> + u16 vport)
> >>>>>>>> +{
> >>>>>>>> + return mlx5_eswitch_get_vport_metadata_for_match(esw, vport);
> >>>>>>>> +}
> >>>>>>>
> >>>>>>> 1. There is no need to introduce one line functions, call to that code directly.
> >>>>>>
> >>>>>> No. They are in IB, and we don't want them be mixed up by the original
> >>>>>> functions in eswitch. Please ask Mark more about it.
> >>>>>
> >>>>> Please enlighten me.
> >>>>
> >>>> It was suggested by Mark in prevouis review.
> >>>> I think it's because there are in different modules, and better to with
> >>>> different names, so introduce there extra one line functions.
> >>>> Please correct me if I'm wrong, Mark...
> >>>
> >>> mlx5_ib is full of direct function calls to mlx5_core and it is done on
> >>> purpose for at least two reasons. First is to control in one place
> >>> all compilation options and expose proper API interface with and without
> >>> specific kernel config is on. Second is to emphasize that this is core
> >>> function and save us time in refactoring and reviewing.
> >>
> >> This was done in order to avoid #ifdef CONFIG_MLX5_ESWITCH,
> >> I want to hide (as much as possible) the interactions with the eswitch level in ib_rep.c/ib_rep.h
> >> so ib_rep.h will provide the stubs needed in case CONFIG_MLX5_ESWITCH isn't defined.
> >> (Today include/linux/mlx5/eswitch.h) doesn't provide any stubs, mlx5_eswitch_get_encap_mode()
> >> should have probably done the same.
> >
> > This is exactly the problem, eswitch.h should provide stubs for all
> > exported functions, so other clients of eswitch won't need to deal with
> > various unrelated config options.
>
> The way it works today, code in drivers/infiniband/hw/mlx5/main.c doesn't call eswitch layer directly
> but the functions in ib_rep.{c,h} as most often there is additional logic we must do before calling
> the eswitch layer.
>
> If you look at drivers/infiniband/hw/mlx5/Makefile you will see ib_rep is complied only when
> CONFIG_MLX5_ESWITCH id defined.
This simple patch + cleanup of ib_rep.h will do the trick.
diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c
index 67b9e7ac569a..b917ba28659e 100644
--- a/drivers/infiniband/hw/mlx5/main.c
+++ b/drivers/infiniband/hw/mlx5/main.c
@@ -59,7 +59,9 @@
#include <linux/in.h>
#include <linux/etherdevice.h>
#include "mlx5_ib.h"
+#if defined(CONFIG_MLX5_ESWITCH)
#include "ib_rep.h"
+#endif
#include "cmd.h"
#include "srq.h"
#include <linux/mlx5/fs_helpers.h>
@@ -6765,6 +6767,7 @@ static const struct mlx5_ib_profile pf_profile = {
mlx5_ib_stage_delay_drop_cleanup),
};
+#if defined(CONFIG_MLX5_ESWITCH)
const struct mlx5_ib_profile uplink_rep_profile = {
STAGE_CREATE(MLX5_IB_STAGE_INIT,
mlx5_ib_stage_init_init,
@@ -6812,6 +6815,7 @@
const struct mlx5_ib_profile uplink_rep_profile = {
mlx5_ib_stage_post_ib_reg_umr_init,
NULL),
};
>
> so instead of having to deal with two places that contain stubs, we need to deal with only one (ib_rep.h).
> For me it makes it easier to follow, but I can adept if you don't like it.
>
> Mark
>
> >
> >>
> >> As my long term goal is to break drivers/infiniband/hw/mlx5/main.c (that file is already 7000 LOC)
> >> I want to group together stuff in separate files.
> >
> > Yes, it is right thing to do.
> >
> >>
> >> If you prefer direct calls that's okay as well.
> >
> > Yes, please.
> >
> >>
> >> Mark
> >>
> >>>
> >>>>
> >>>>>
> >>>>>>
> >>>>>>> 2. It should be bool and not u32.
> >>>>>>>
> >>>>>>> Thanks
> >>>>>>
> >>>>>> --
> >>>>
> >>>> --
^ permalink raw reply related
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