* Re: [PATCH] sis900: increment revision number
From: David Miller @ 2019-06-23 15:37 UTC (permalink / raw)
To: venza; +Cc: joe, sergej.benilov, netdev
In-Reply-To: <7038d64e-0d3c-6b13-04fd-b614efbf5162@brownhat.org>
From: Daniele Venzano <venza@brownhat.org>
Date: Sun, 23 Jun 2019 11:13:28 +0200
> Hello,
>
> I think it is good to know just by looking at the sources that the
> driver is still kept up-to-date, so I am in favor of this patch.
I absolutely, strongly, disagree.
These are pointless.
^ permalink raw reply
* Re: [PATCH] sis900: increment revision number
From: David Miller @ 2019-06-23 15:36 UTC (permalink / raw)
To: sergej.benilov; +Cc: venza, netdev
In-Reply-To: <20190623074707.6348-1-sergej.benilov@googlemail.com>
From: Sergej Benilov <sergej.benilov@googlemail.com>
Date: Sun, 23 Jun 2019 09:47:07 +0200
> Increment revision number to 1.08.11 (TX completion fix).
>
> Signed-off-by: Sergej Benilov <sergej.benilov@googlemail.com>
These are useless, really...
People are going to backport the TX completion fix all by itself
and not this change if I were to merge it.
I really want to heavily discourage these kinds of things, sorry.
Code is code, the fix is there or it isn't.
^ permalink raw reply
* Re: [PATCH 10/15] ARM: orion5x: cleanup cppcheck shifting errors
From: Andrew Lunn @ 2019-06-23 15:23 UTC (permalink / raw)
To: Phong Tran
Cc: mark.rutland, kstewart, songliubraving, peterz, nsekhar, ast,
jolsa, netdev, gerg, lorenzo.pieralisi, will, linux-samsung-soc,
daniel, festevam, gregory.clement, allison, linux, krzk,
haojian.zhuang, bgolaszewski, tony, mingo, linux-imx, yhs,
sebastian.hesselbarth, illusionist.neo, jason, liviu.dudau,
s.hauer, acme, lkundrak, robert.jarzmik, dmg, swinslow, namhyung,
tglx, linux-omap, alexander.sverdlin, linux-arm-kernel, info,
gregkh, linux-kernel, alexander.shishkin, hsweeten, kgene, kernel,
sudeep.holla, bpf, shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-11-tranmanphong@gmail.com>
On Sun, Jun 23, 2019 at 10:13:08PM +0700, Phong Tran wrote:
> [arch/arm/mach-orion5x/pci.c:281]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-orion5x/pci.c:305]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
>
> Signed-off-by: Phong Tran <tranmanphong@gmail.com>
Maybe using the BIT() macro would be better, but this is O.K.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* Re: [PATCH 03/15] ARM: ep93xx: cleanup cppcheck shifting errors
From: Alexander Sverdlin @ 2019-06-23 15:23 UTC (permalink / raw)
To: Phong Tran
Cc: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, festevam, gregory.clement, allison,
linux, krzk, haojian.zhuang, bgolaszewski, tony, mingo, linux-imx,
yhs, sebastian.hesselbarth, illusionist.neo, jason, liviu.dudau,
s.hauer, acme, lkundrak, robert.jarzmik, dmg, swinslow, namhyung,
tglx, linux-omap, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-4-tranmanphong@gmail.com>
Hi!
On Sun, 23 Jun 2019 22:13:01 +0700
Phong Tran <tranmanphong@gmail.com> wrote:
> [arch/arm/mach-ep93xx/clock.c:102]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/clock.c:132]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/clock.c:140]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/core.c:1001]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/core.c:1002]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
>
> Signed-off-by: Phong Tran <tranmanphong@gmail.com>
> ---
> arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++++++-----------------------
> 1 file changed, 66 insertions(+), 66 deletions(-)
>
> diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
> index f2dace1c9154..831ea5266281 100644
> --- a/arch/arm/mach-ep93xx/soc.h
> +++ b/arch/arm/mach-ep93xx/soc.h
> @@ -109,89 +109,89 @@
> #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
> #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
> #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
> -#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
> -#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
> -#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
> +#define EP93XX_SYSCON_PWRCNT_FIR_EN (1U<<31)
Could you please use BIT() for this?
> +#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1U<<29)
> +#define EP93XX_SYSCON_PWRCNT_USH_EN (1U<<28)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1U<<27)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1U<<26)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1U<<25)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1U<<24)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1U<<23)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1U<<22)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1U<<21)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1U<<20)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1U<<19)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1U<<18)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1U<<17)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1U<<16)
> #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
> #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
> #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
> -#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
> +#define EP93XX_SYSCON_CLKSET1_NBYP1 (1U<<23)
> #define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
> -#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
> -#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
> +#define EP93XX_SYSCON_CLKSET2_NBYP2 (1U<<19)
> +#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1U<<18)
> #define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
> -#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
> -#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
> -#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
> -#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
> -#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
> -#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
> -#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
> -#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
> -#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
> -#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
> -#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
> -#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
> -#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
> -#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
> -#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
> -#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
> -#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
> -#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
> -#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
> -#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
> -#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
> -#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
> -#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
> -#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
> -#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
> -#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
> -#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
> -#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
> -#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
> -#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
> +#define EP93XX_SYSCON_DEVCFG_SWRST (1U<<31)
> +#define EP93XX_SYSCON_DEVCFG_D1ONG (1U<<30)
> +#define EP93XX_SYSCON_DEVCFG_D0ONG (1U<<29)
> +#define EP93XX_SYSCON_DEVCFG_IONU2 (1U<<28)
> +#define EP93XX_SYSCON_DEVCFG_GONK (1U<<27)
> +#define EP93XX_SYSCON_DEVCFG_TONG (1U<<26)
> +#define EP93XX_SYSCON_DEVCFG_MONG (1U<<25)
> +#define EP93XX_SYSCON_DEVCFG_U3EN (1U<<24)
> +#define EP93XX_SYSCON_DEVCFG_CPENA (1U<<23)
> +#define EP93XX_SYSCON_DEVCFG_A2ONG (1U<<22)
> +#define EP93XX_SYSCON_DEVCFG_A1ONG (1U<<21)
> +#define EP93XX_SYSCON_DEVCFG_U2EN (1U<<20)
> +#define EP93XX_SYSCON_DEVCFG_EXVC (1U<<19)
> +#define EP93XX_SYSCON_DEVCFG_U1EN (1U<<18)
> +#define EP93XX_SYSCON_DEVCFG_TIN (1U<<17)
> +#define EP93XX_SYSCON_DEVCFG_HC3IN (1U<<15)
> +#define EP93XX_SYSCON_DEVCFG_HC3EN (1U<<14)
> +#define EP93XX_SYSCON_DEVCFG_HC1IN (1U<<13)
> +#define EP93XX_SYSCON_DEVCFG_HC1EN (1U<<12)
> +#define EP93XX_SYSCON_DEVCFG_HONIDE (1U<<11)
> +#define EP93XX_SYSCON_DEVCFG_GONIDE (1U<<10)
> +#define EP93XX_SYSCON_DEVCFG_PONG (1U<<9)
> +#define EP93XX_SYSCON_DEVCFG_EONIDE (1U<<8)
> +#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1U<<7)
> +#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1U<<6)
> +#define EP93XX_SYSCON_DEVCFG_RASONP3 (1U<<4)
> +#define EP93XX_SYSCON_DEVCFG_RAS (1U<<3)
> +#define EP93XX_SYSCON_DEVCFG_ADCPD (1U<<2)
> +#define EP93XX_SYSCON_DEVCFG_KEYS (1U<<1)
> +#define EP93XX_SYSCON_DEVCFG_SHENA (1U<<0)
> #define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
> -#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
> -#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
> -#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
> +#define EP93XX_SYSCON_CLKDIV_ENABLE (1U<<15)
> +#define EP93XX_SYSCON_CLKDIV_ESEL (1U<<14)
> +#define EP93XX_SYSCON_CLKDIV_PSEL (1U<<13)
> #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
> #define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
> -#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31)
> -#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
> -#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
> +#define EP93XX_SYSCON_I2SCLKDIV_SENA (1U<<31)
> +#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1U<<29)
> +#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1U<<19)
> #define EP93XX_I2SCLKDIV_SDIV (1 << 16)
> #define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
> #define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
> #define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
> #define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
> #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1U<<31)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1U<<16)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1U<<15)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1U<<0)
> #define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
> #define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
> #define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
> -#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
> -#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
> -#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
> -#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
> -#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
> -#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
> -#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
> -#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
> +#define EP93XX_SYSCON_SYSCFG_SBOOT (1U<<8)
> +#define EP93XX_SYSCON_SYSCFG_LCSN7 (1U<<7)
> +#define EP93XX_SYSCON_SYSCFG_LCSN6 (1U<<6)
> +#define EP93XX_SYSCON_SYSCFG_LASDO (1U<<5)
> +#define EP93XX_SYSCON_SYSCFG_LEEDA (1U<<4)
> +#define EP93XX_SYSCON_SYSCFG_LEECLK (1U<<3)
> +#define EP93XX_SYSCON_SYSCFG_LCSN2 (1U<<1)
> +#define EP93XX_SYSCON_SYSCFG_LCSN1 (1U<<0)
> #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
>
> /* EP93xx System Controller software locked register write */
--
Alexander Sverdlin.
^ permalink raw reply
* [PATCH 15/15] ARM: vfp: cleanup cppcheck shifting errors
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/vfp/vfpdouble.c:397]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpdouble.c:407]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpmodule.c:263]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpmodule.c:264]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpsingle.c:441]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpsingle.c:451]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/vfp/vfpinstr.h | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h
index 38dc154e39ff..377ab0ced8d8 100644
--- a/arch/arm/vfp/vfpinstr.h
+++ b/arch/arm/vfp/vfpinstr.h
@@ -8,8 +8,8 @@
* VFP instruction masks.
*/
#define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000)
-#define INST_CPRT(inst) ((inst) & (1 << 4))
-#define INST_CPRT_L(inst) ((inst) & (1 << 20))
+#define INST_CPRT(inst) ((inst) & (1U << 4))
+#define INST_CPRT_L(inst) ((inst) & (1U << 20))
#define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12)
#define INST_CPRT_OP(inst) (((inst) >> 21) & 7)
#define INST_CPNUM(inst) ((inst) & 0xf00)
@@ -27,7 +27,7 @@
#define FOP_FDIV (0x00800000)
#define FOP_EXT (0x00b00040)
-#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
+#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1U << 6)) >> 4)
#define FEXT_MASK (0x000f0080)
#define FEXT_FCPY (0x00000000)
@@ -46,21 +46,21 @@
#define FEXT_FTOSI (0x000d0000)
#define FEXT_FTOSIZ (0x000d0080)
-#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
+#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1U << 7)) >> 7)
-#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
-#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
-#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
-#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
-#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
-#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
+#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1U << 22)) >> 22)
+#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1U << 22)) >> 18)
+#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1U << 5)) >> 5)
+#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1U << 5)) >> 1)
+#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1U << 7)) >> 7)
+#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1U << 7)) >> 3)
#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
-#define FPSCR_N (1 << 31)
-#define FPSCR_Z (1 << 30)
-#define FPSCR_C (1 << 29)
-#define FPSCR_V (1 << 28)
+#define FPSCR_N (1U << 31)
+#define FPSCR_Z (1U << 30)
+#define FPSCR_C (1U << 29)
+#define FPSCR_V (1U << 28)
/*
* Since we aren't building with -mfpu=vfp, we need to code
--
2.11.0
^ permalink raw reply related
* [PATCH 14/15] ARM: bpf: cleanup cppcheck shifting error
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/net/bpf_jit_32.c:618]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/net/bpf_jit_32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index adff54c312bf..9c3f8fb871e5 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -612,7 +612,7 @@ static inline void emit_a32_mov_se_i64(const bool is64, const s8 dst[],
const u32 val, struct jit_ctx *ctx) {
u64 val64 = val;
- if (is64 && (val & (1<<31)))
+ if (is64 && (val & (1U<<31)))
val64 |= 0xffffffff00000000ULL;
emit_a32_mov_i64(dst, val64, ctx);
}
--
2.11.0
^ permalink raw reply related
* [PATCH 13/15] ARM: mm: cleanup cppcheck shifting errors
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mm/alignment.c:875]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/mm/fault.c:556]: (error) Shifting signed 32-bit value by 31
bits is undefined behaviour
[arch/arm/mm/fault.c:585]: (error) Shifting signed 32-bit value by 31
bits is undefined behaviour
[arch/arm/mm/fault.c:219]: (error) Shifting signed 32-bit value by 31
bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mm/fault.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h
index c063708fa503..159c4e7bff09 100644
--- a/arch/arm/mm/fault.h
+++ b/arch/arm/mm/fault.h
@@ -5,9 +5,9 @@
/*
* Fault status register encodings. We steal bit 31 for our own purposes.
*/
-#define FSR_LNX_PF (1 << 31)
-#define FSR_WRITE (1 << 11)
-#define FSR_FS4 (1 << 10)
+#define FSR_LNX_PF (1U << 31)
+#define FSR_WRITE (1U << 11)
+#define FSR_FS4 (1U << 10)
#define FSR_FS3_0 (15)
#define FSR_FS5_0 (0x3f)
--
2.11.0
^ permalink raw reply related
* [PATCH 12/15] ARM: vexpress: cleanup cppcheck shifting error
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mach-vexpress/spc.c:366]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-vexpress/spc.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
index 0f5381d13494..f8911dae776c 100644
--- a/arch/arm/mach-vexpress/spc.c
+++ b/arch/arm/mach-vexpress/spc.c
@@ -57,8 +57,8 @@
/* SPC CPU/cluster reset statue */
#define STANDBYWFI_STAT 0x3c
-#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu))
-#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu)))
+#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1U << (cpu))
+#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1U << (3 + (cpu)))
/* SPC system config interface registers */
#define SYSCFG_WDATA 0x70
@@ -69,7 +69,7 @@
#define A7_PERFVAL_BASE 0xC30
/* Config interface control bits */
-#define SYSCFG_START (1 << 31)
+#define SYSCFG_START (1U << 31)
#define SYSCFG_SCC (6 << 20)
#define SYSCFG_STAT (14 << 20)
@@ -90,8 +90,8 @@
#define CA15_DVFS 0
#define CA7_DVFS 1
#define SPC_SYS_CFG 2
-#define STAT_COMPLETE(type) ((1 << 0) << (type << 2))
-#define STAT_ERR(type) ((1 << 1) << (type << 2))
+#define STAT_COMPLETE(type) ((1U << 0) << (type << 2))
+#define STAT_ERR(type) ((1U << 1) << (type << 2))
#define RESPONSE_MASK(type) (STAT_COMPLETE(type) | STAT_ERR(type))
struct ve_spc_opp {
@@ -162,7 +162,7 @@ void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
if (cluster >= MAX_CLUSTERS)
return;
- mask = 1 << cpu;
+ mask = 1U << cpu;
if (!cluster_is_a15(cluster))
mask <<= 4;
--
2.11.0
^ permalink raw reply related
* [PATCH 11/15] ARM: pxa: cleanup cppcheck shifting errors
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mach-pxa/irq.c:117]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/mach-pxa/irq.c:131]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-pxa/irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 74efc3ab595f..2e2afe16069c 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -35,9 +35,9 @@
#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
(0x144 + (((i) - 64) << 2)))
-#define ICHP_VAL_IRQ (1 << 31)
+#define ICHP_VAL_IRQ (1U << 31)
#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
-#define IPR_VALID (1 << 31)
+#define IPR_VALID (1U << 31)
#define MAX_INTERNAL_IRQS 128
--
2.11.0
^ permalink raw reply related
* [PATCH 10/15] ARM: orion5x: cleanup cppcheck shifting errors
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mach-orion5x/pci.c:281]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-orion5x/pci.c:305]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-orion5x/pci.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 76951bfbacf5..1b2c077ee7b8 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -200,13 +200,13 @@ static int __init pcie_setup(struct pci_sys_data *sys)
/*
* PCI_MODE bits
*/
-#define PCI_MODE_64BIT (1 << 2)
-#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
+#define PCI_MODE_64BIT (1U << 2)
+#define PCI_MODE_PCIX ((1U << 4) | (1U << 5))
/*
* PCI_CMD bits
*/
-#define PCI_CMD_HOST_REORDER (1 << 29)
+#define PCI_CMD_HOST_REORDER (1U << 29)
/*
* PCI_P2P_CONF bits
@@ -223,7 +223,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
-#define PCI_CONF_ADDR_EN (1 << 31)
+#define PCI_CONF_ADDR_EN (1U << 31)
/*
* Internal configuration space
--
2.11.0
^ permalink raw reply related
* [PATCH 09/15] ARM: omap2: cleanup cppcheck shifting error
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mach-omap2/powerdomain.c:190]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-omap2/powerdomain.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 1cbac76136d4..4e2eb39bc698 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -35,7 +35,7 @@
#include "soc.h"
#include "pm.h"
-#define PWRDM_TRACE_STATES_FLAG (1<<31)
+#define PWRDM_TRACE_STATES_FLAG (1U<<31)
void pwrdms_save_context(void);
void pwrdms_restore_context(void);
--
2.11.0
^ permalink raw reply related
* [PATCH 08/15] ARM: mmp: cleanup cppcheck shifting errors
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mach-mmp/pm-mmp2.c:121]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-mmp2.c:136]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-mmp2.c:244]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-pxa910.c:141]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-pxa910.c:159]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-mmp/pm-mmp2.h | 40 +++++++++++------------
arch/arm/mach-mmp/pm-pxa910.h | 76 +++++++++++++++++++++----------------------
2 files changed, 58 insertions(+), 58 deletions(-)
diff --git a/arch/arm/mach-mmp/pm-mmp2.h b/arch/arm/mach-mmp/pm-mmp2.h
index 70299a9450d3..87fd1c81547d 100644
--- a/arch/arm/mach-mmp/pm-mmp2.h
+++ b/arch/arm/mach-mmp/pm-mmp2.h
@@ -12,37 +12,37 @@
#include "addr-map.h"
#define APMU_PJ_IDLE_CFG APMU_REG(0x018)
-#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1)
-#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5)
+#define APMU_PJ_IDLE_CFG_PJ_IDLE (1U << 1)
+#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1U << 5)
#define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16)
-#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19)
+#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1U << 19)
#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28)
#define APMU_SRAM_PWR_DWN APMU_REG(0x08c)
#define MPMU_SCCR MPMU_REG(0x038)
#define MPMU_PCR_PJ MPMU_REG(0x1000)
-#define MPMU_PCR_PJ_AXISD (1 << 31)
-#define MPMU_PCR_PJ_SLPEN (1 << 29)
-#define MPMU_PCR_PJ_SPSD (1 << 28)
-#define MPMU_PCR_PJ_DDRCORSD (1 << 27)
-#define MPMU_PCR_PJ_APBSD (1 << 26)
-#define MPMU_PCR_PJ_INTCLR (1 << 24)
-#define MPMU_PCR_PJ_SLPWP0 (1 << 23)
-#define MPMU_PCR_PJ_SLPWP1 (1 << 22)
-#define MPMU_PCR_PJ_SLPWP2 (1 << 21)
-#define MPMU_PCR_PJ_SLPWP3 (1 << 20)
-#define MPMU_PCR_PJ_VCTCXOSD (1 << 19)
-#define MPMU_PCR_PJ_SLPWP4 (1 << 18)
-#define MPMU_PCR_PJ_SLPWP5 (1 << 17)
-#define MPMU_PCR_PJ_SLPWP6 (1 << 16)
-#define MPMU_PCR_PJ_SLPWP7 (1 << 15)
+#define MPMU_PCR_PJ_AXISD (1U << 31)
+#define MPMU_PCR_PJ_SLPEN (1U << 29)
+#define MPMU_PCR_PJ_SPSD (1U << 28)
+#define MPMU_PCR_PJ_DDRCORSD (1U << 27)
+#define MPMU_PCR_PJ_APBSD (1U << 26)
+#define MPMU_PCR_PJ_INTCLR (1U << 24)
+#define MPMU_PCR_PJ_SLPWP0 (1U << 23)
+#define MPMU_PCR_PJ_SLPWP1 (1U << 22)
+#define MPMU_PCR_PJ_SLPWP2 (1U << 21)
+#define MPMU_PCR_PJ_SLPWP3 (1U << 20)
+#define MPMU_PCR_PJ_VCTCXOSD (1U << 19)
+#define MPMU_PCR_PJ_SLPWP4 (1U << 18)
+#define MPMU_PCR_PJ_SLPWP5 (1U << 17)
+#define MPMU_PCR_PJ_SLPWP6 (1U << 16)
+#define MPMU_PCR_PJ_SLPWP7 (1U << 15)
#define MPMU_PLL2_CTRL1 MPMU_REG(0x0414)
#define MPMU_CGR_PJ MPMU_REG(0x1024)
#define MPMU_WUCRM_PJ MPMU_REG(0x104c)
-#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x))
-#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17)
+#define MPMU_WUCRM_PJ_WAKEUP(x) (1U << (x))
+#define MPMU_WUCRM_PJ_RTC_ALARM (1U << 17)
enum {
POWER_MODE_ACTIVE = 0,
diff --git a/arch/arm/mach-mmp/pm-pxa910.h b/arch/arm/mach-mmp/pm-pxa910.h
index 8e6344adaf51..0958cde1ca6e 100644
--- a/arch/arm/mach-mmp/pm-pxa910.h
+++ b/arch/arm/mach-mmp/pm-pxa910.h
@@ -10,54 +10,54 @@
#define __PXA910_PM_H__
#define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
-#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
-#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
-#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
+#define APMU_MOH_IDLE_CFG_MOH_IDLE (1U << 1)
+#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1U << 5)
+#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1U << 6)
#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
-#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
-#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
+#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1U << 21)
+#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1U << 20)
#define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
#define MPMU_FCCR MPMU_REG(0x0008)
#define MPMU_APCR MPMU_REG(0x1000)
-#define MPMU_APCR_AXISD (1 << 31)
-#define MPMU_APCR_DSPSD (1 << 30)
-#define MPMU_APCR_SLPEN (1 << 29)
-#define MPMU_APCR_DTCMSD (1 << 28)
-#define MPMU_APCR_DDRCORSD (1 << 27)
-#define MPMU_APCR_APBSD (1 << 26)
-#define MPMU_APCR_BBSD (1 << 25)
-#define MPMU_APCR_SLPWP0 (1 << 23)
-#define MPMU_APCR_SLPWP1 (1 << 22)
-#define MPMU_APCR_SLPWP2 (1 << 21)
-#define MPMU_APCR_SLPWP3 (1 << 20)
-#define MPMU_APCR_VCTCXOSD (1 << 19)
-#define MPMU_APCR_SLPWP4 (1 << 18)
-#define MPMU_APCR_SLPWP5 (1 << 17)
-#define MPMU_APCR_SLPWP6 (1 << 16)
-#define MPMU_APCR_SLPWP7 (1 << 15)
-#define MPMU_APCR_MSASLPEN (1 << 14)
-#define MPMU_APCR_STBYEN (1 << 13)
+#define MPMU_APCR_AXISD (1U << 31)
+#define MPMU_APCR_DSPSD (1U << 30)
+#define MPMU_APCR_SLPEN (1U << 29)
+#define MPMU_APCR_DTCMSD (1U << 28)
+#define MPMU_APCR_DDRCORSD (1U << 27)
+#define MPMU_APCR_APBSD (1U << 26)
+#define MPMU_APCR_BBSD (1U << 25)
+#define MPMU_APCR_SLPWP0 (1U << 23)
+#define MPMU_APCR_SLPWP1 (1U << 22)
+#define MPMU_APCR_SLPWP2 (1U << 21)
+#define MPMU_APCR_SLPWP3 (1U << 20)
+#define MPMU_APCR_VCTCXOSD (1U << 19)
+#define MPMU_APCR_SLPWP4 (1U << 18)
+#define MPMU_APCR_SLPWP5 (1U << 17)
+#define MPMU_APCR_SLPWP6 (1U << 16)
+#define MPMU_APCR_SLPWP7 (1U << 15)
+#define MPMU_APCR_MSASLPEN (1U << 14)
+#define MPMU_APCR_STBYEN (1U << 13)
#define MPMU_AWUCRM MPMU_REG(0x104c)
-#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
-#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
-#define MPMU_AWUCRM_SDH1 (1 << 23)
-#define MPMU_AWUCRM_SDH2 (1 << 22)
-#define MPMU_AWUCRM_KEYPRESS (1 << 21)
-#define MPMU_AWUCRM_TRACKBALL (1 << 20)
-#define MPMU_AWUCRM_NEWROTARY (1 << 19)
-#define MPMU_AWUCRM_RTC_ALARM (1 << 17)
-#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
-#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
-#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
-#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
-#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
-#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
-#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
+#define MPMU_AWUCRM_AP_ASYNC_INT (1U << 25)
+#define MPMU_AWUCRM_AP_FULL_IDLE (1U << 24)
+#define MPMU_AWUCRM_SDH1 (1U << 23)
+#define MPMU_AWUCRM_SDH2 (1U << 22)
+#define MPMU_AWUCRM_KEYPRESS (1U << 21)
+#define MPMU_AWUCRM_TRACKBALL (1U << 20)
+#define MPMU_AWUCRM_NEWROTARY (1U << 19)
+#define MPMU_AWUCRM_RTC_ALARM (1U << 17)
+#define MPMU_AWUCRM_AP2_TIMER_3 (1U << 13)
+#define MPMU_AWUCRM_AP2_TIMER_2 (1U << 12)
+#define MPMU_AWUCRM_AP2_TIMER_1 (1U << 11)
+#define MPMU_AWUCRM_AP1_TIMER_3 (1U << 10)
+#define MPMU_AWUCRM_AP1_TIMER_2 (1U << 9)
+#define MPMU_AWUCRM_AP1_TIMER_1 (1U << 8)
+#define MPMU_AWUCRM_WAKEUP(x) (1U << ((x) & 0x7))
enum {
POWER_MODE_ACTIVE = 0,
--
2.11.0
^ permalink raw reply related
* [PATCH 07/15] ARM: ks8695: cleanup cppcheck shifting error
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mach-ks8695/pci.c:33]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-ks8695/regs-pci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-ks8695/regs-pci.h b/arch/arm/mach-ks8695/regs-pci.h
index 75a9db6edbd9..9ddab054c6fc 100644
--- a/arch/arm/mach-ks8695/regs-pci.h
+++ b/arch/arm/mach-ks8695/regs-pci.h
@@ -45,9 +45,9 @@
-#define CFRV_GUEST (1 << 23)
+#define CFRV_GUEST (1U << 23)
#define PBCA_TYPE1 (1)
-#define PBCA_ENABLE (1 << 31)
+#define PBCA_ENABLE (1U << 31)
--
2.11.0
^ permalink raw reply related
* [PATCH 06/15] ARM: imx: cleanup cppcheck shifting errors
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mach-imx/iomux-mx3.h:93]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-imx/iomux-mx3.h | 64 +++++++++++++++++++++----------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index 99270a183d47..c30951dd110d 100644
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
@@ -59,38 +59,38 @@ enum iomux_pad_config {
* various IOMUX general purpose functions
*/
enum iomux_gp_func {
- MUX_PGP_FIRI = 1 << 0,
- MUX_DDR_MODE = 1 << 1,
- MUX_PGP_CSPI_BB = 1 << 2,
- MUX_PGP_ATA_1 = 1 << 3,
- MUX_PGP_ATA_2 = 1 << 4,
- MUX_PGP_ATA_3 = 1 << 5,
- MUX_PGP_ATA_4 = 1 << 6,
- MUX_PGP_ATA_5 = 1 << 7,
- MUX_PGP_ATA_6 = 1 << 8,
- MUX_PGP_ATA_7 = 1 << 9,
- MUX_PGP_ATA_8 = 1 << 10,
- MUX_PGP_UH2 = 1 << 11,
- MUX_SDCTL_CSD0_SEL = 1 << 12,
- MUX_SDCTL_CSD1_SEL = 1 << 13,
- MUX_CSPI1_UART3 = 1 << 14,
- MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
- MUX_TAMPER_DETECT_EN = 1 << 16,
- MUX_PGP_USB_4WIRE = 1 << 17,
- MUX_PGP_USB_COMMON = 1 << 18,
- MUX_SDHC_MEMSTICK1 = 1 << 19,
- MUX_SDHC_MEMSTICK2 = 1 << 20,
- MUX_PGP_SPLL_BYP = 1 << 21,
- MUX_PGP_UPLL_BYP = 1 << 22,
- MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
- MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
- MUX_CSPI3_UART5_SEL = 1 << 25,
- MUX_PGP_ATA_9 = 1 << 26,
- MUX_PGP_USB_SUSPEND = 1 << 27,
- MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
- MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
- MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
- MUX_CLKO_DDR_MODE = 1 << 31,
+ MUX_PGP_FIRI = 1U << 0,
+ MUX_DDR_MODE = 1U << 1,
+ MUX_PGP_CSPI_BB = 1U << 2,
+ MUX_PGP_ATA_1 = 1U << 3,
+ MUX_PGP_ATA_2 = 1U << 4,
+ MUX_PGP_ATA_3 = 1U << 5,
+ MUX_PGP_ATA_4 = 1U << 6,
+ MUX_PGP_ATA_5 = 1U << 7,
+ MUX_PGP_ATA_6 = 1U << 8,
+ MUX_PGP_ATA_7 = 1U << 9,
+ MUX_PGP_ATA_8 = 1U << 10,
+ MUX_PGP_UH2 = 1U << 11,
+ MUX_SDCTL_CSD0_SEL = 1U << 12,
+ MUX_SDCTL_CSD1_SEL = 1U << 13,
+ MUX_CSPI1_UART3 = 1U << 14,
+ MUX_EXTDMAREQ2_MBX_SEL = 1U << 15,
+ MUX_TAMPER_DETECT_EN = 1U << 16,
+ MUX_PGP_USB_4WIRE = 1U << 17,
+ MUX_PGP_USB_COMMON = 1U << 18,
+ MUX_SDHC_MEMSTICK1 = 1U << 19,
+ MUX_SDHC_MEMSTICK2 = 1U << 20,
+ MUX_PGP_SPLL_BYP = 1U << 21,
+ MUX_PGP_UPLL_BYP = 1U << 22,
+ MUX_PGP_MSHC1_CLK_SEL = 1U << 23,
+ MUX_PGP_MSHC2_CLK_SEL = 1U << 24,
+ MUX_CSPI3_UART5_SEL = 1U << 25,
+ MUX_PGP_ATA_9 = 1U << 26,
+ MUX_PGP_USB_SUSPEND = 1U << 27,
+ MUX_PGP_USB_OTG_LOOPBACK = 1U << 28,
+ MUX_PGP_USB_HS1_LOOPBACK = 1U << 29,
+ MUX_PGP_USB_HS2_LOOPBACK = 1U << 30,
+ MUX_CLKO_DDR_MODE = 1U << 31,
};
/*
--
2.11.0
^ permalink raw reply related
* [PATCH 05/15] ARM: footbridge: cleanup cppcheck shifting error
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mach-footbridge/dc21285.c:236]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 8b81a17f675d..a6c86175e76c 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -230,7 +230,7 @@ static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
printk("\n");
cmd = *CSR_PCICMD & 0xffff;
- *CSR_PCICMD = cmd | 1 << 31;
+ *CSR_PCICMD = cmd | 1U << 31;
/*
* back off this interrupt
--
2.11.0
^ permalink raw reply related
* [PATCH V2] net: dsa: microchip: Use gpiod_set_value_cansleep()
From: Marek Vasut @ 2019-06-23 15:12 UTC (permalink / raw)
To: netdev
Cc: Marek Vasut, Andrew Lunn, Florian Fainelli, Linus Walleij,
Tristram Ha, Woojung Huh
Replace gpiod_set_value() with gpiod_set_value_cansleep(), as the switch
reset GPIO can be connected to e.g. I2C GPIO expander and it is perfectly
fine for the kernel to sleep for a bit in ksz_switch_register().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Tristram Ha <Tristram.Ha@microchip.com>
Cc: Woojung Huh <Woojung.Huh@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
V2: use _cansleep in .remove as well
---
drivers/net/dsa/microchip/ksz_common.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 4f6648d5ac8b..978c59aa8efb 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -436,9 +436,9 @@ int ksz_switch_register(struct ksz_device *dev,
return PTR_ERR(dev->reset_gpio);
if (dev->reset_gpio) {
- gpiod_set_value(dev->reset_gpio, 1);
+ gpiod_set_value_cansleep(dev->reset_gpio, 1);
mdelay(10);
- gpiod_set_value(dev->reset_gpio, 0);
+ gpiod_set_value_cansleep(dev->reset_gpio, 0);
}
mutex_init(&dev->dev_mutex);
@@ -489,7 +489,7 @@ void ksz_switch_remove(struct ksz_device *dev)
dsa_unregister_switch(dev->ds);
if (dev->reset_gpio)
- gpiod_set_value(dev->reset_gpio, 1);
+ gpiod_set_value_cansleep(dev->reset_gpio, 1);
}
EXPORT_SYMBOL(ksz_switch_remove);
--
2.20.1
^ permalink raw reply related
* [PATCH 04/15] ARM: exynos: cleanup cppcheck shifting error
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mach-exynos/suspend.c:288]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-exynos/suspend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index be122af0de8f..8b93d130f79c 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -285,7 +285,7 @@ static void exynos_pm_set_wakeup_mask(void)
* Set wake-up mask registers
* EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
*/
- pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+ pmu_raw_writel(exynos_irqwake_intmask & ~(1U << 31), S5P_WAKEUP_MASK);
}
static void exynos_pm_enter_sleep_mode(void)
--
2.11.0
^ permalink raw reply related
* [PATCH 03/15] ARM: ep93xx: cleanup cppcheck shifting errors
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mach-ep93xx/clock.c:102]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/clock.c:132]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/clock.c:140]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/core.c:1001]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/core.c:1002]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++++++-----------------------
1 file changed, 66 insertions(+), 66 deletions(-)
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
index f2dace1c9154..831ea5266281 100644
--- a/arch/arm/mach-ep93xx/soc.h
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -109,89 +109,89 @@
#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
-#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
-#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
-#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
+#define EP93XX_SYSCON_PWRCNT_FIR_EN (1U<<31)
+#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1U<<29)
+#define EP93XX_SYSCON_PWRCNT_USH_EN (1U<<28)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1U<<27)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1U<<26)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1U<<25)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1U<<24)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1U<<23)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1U<<22)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1U<<21)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1U<<20)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1U<<19)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1U<<18)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1U<<17)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1U<<16)
#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
+#define EP93XX_SYSCON_CLKSET1_NBYP1 (1U<<23)
#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
-#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
-#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
+#define EP93XX_SYSCON_CLKSET2_NBYP2 (1U<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1U<<18)
#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
-#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
-#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
-#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
-#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
-#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
-#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
-#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
-#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
-#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
-#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
-#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
-#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
-#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
-#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
-#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
-#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
-#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
-#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
-#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
-#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
-#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
-#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
-#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
-#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
-#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
-#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
-#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
-#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
-#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
+#define EP93XX_SYSCON_DEVCFG_SWRST (1U<<31)
+#define EP93XX_SYSCON_DEVCFG_D1ONG (1U<<30)
+#define EP93XX_SYSCON_DEVCFG_D0ONG (1U<<29)
+#define EP93XX_SYSCON_DEVCFG_IONU2 (1U<<28)
+#define EP93XX_SYSCON_DEVCFG_GONK (1U<<27)
+#define EP93XX_SYSCON_DEVCFG_TONG (1U<<26)
+#define EP93XX_SYSCON_DEVCFG_MONG (1U<<25)
+#define EP93XX_SYSCON_DEVCFG_U3EN (1U<<24)
+#define EP93XX_SYSCON_DEVCFG_CPENA (1U<<23)
+#define EP93XX_SYSCON_DEVCFG_A2ONG (1U<<22)
+#define EP93XX_SYSCON_DEVCFG_A1ONG (1U<<21)
+#define EP93XX_SYSCON_DEVCFG_U2EN (1U<<20)
+#define EP93XX_SYSCON_DEVCFG_EXVC (1U<<19)
+#define EP93XX_SYSCON_DEVCFG_U1EN (1U<<18)
+#define EP93XX_SYSCON_DEVCFG_TIN (1U<<17)
+#define EP93XX_SYSCON_DEVCFG_HC3IN (1U<<15)
+#define EP93XX_SYSCON_DEVCFG_HC3EN (1U<<14)
+#define EP93XX_SYSCON_DEVCFG_HC1IN (1U<<13)
+#define EP93XX_SYSCON_DEVCFG_HC1EN (1U<<12)
+#define EP93XX_SYSCON_DEVCFG_HONIDE (1U<<11)
+#define EP93XX_SYSCON_DEVCFG_GONIDE (1U<<10)
+#define EP93XX_SYSCON_DEVCFG_PONG (1U<<9)
+#define EP93XX_SYSCON_DEVCFG_EONIDE (1U<<8)
+#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1U<<7)
+#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1U<<6)
+#define EP93XX_SYSCON_DEVCFG_RASONP3 (1U<<4)
+#define EP93XX_SYSCON_DEVCFG_RAS (1U<<3)
+#define EP93XX_SYSCON_DEVCFG_ADCPD (1U<<2)
+#define EP93XX_SYSCON_DEVCFG_KEYS (1U<<1)
+#define EP93XX_SYSCON_DEVCFG_SHENA (1U<<0)
#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
-#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
-#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
-#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
+#define EP93XX_SYSCON_CLKDIV_ENABLE (1U<<15)
+#define EP93XX_SYSCON_CLKDIV_ESEL (1U<<14)
+#define EP93XX_SYSCON_CLKDIV_PSEL (1U<<13)
#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
-#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31)
-#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
-#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
+#define EP93XX_SYSCON_I2SCLKDIV_SENA (1U<<31)
+#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1U<<29)
+#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1U<<19)
#define EP93XX_I2SCLKDIV_SDIV (1 << 16)
#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1U<<31)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1U<<16)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1U<<15)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1U<<0)
#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
-#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
-#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
-#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
-#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
-#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
-#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
-#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
-#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
+#define EP93XX_SYSCON_SYSCFG_SBOOT (1U<<8)
+#define EP93XX_SYSCON_SYSCFG_LCSN7 (1U<<7)
+#define EP93XX_SYSCON_SYSCFG_LCSN6 (1U<<6)
+#define EP93XX_SYSCON_SYSCFG_LASDO (1U<<5)
+#define EP93XX_SYSCON_SYSCFG_LEEDA (1U<<4)
+#define EP93XX_SYSCON_SYSCFG_LEECLK (1U<<3)
+#define EP93XX_SYSCON_SYSCFG_LCSN2 (1U<<1)
+#define EP93XX_SYSCON_SYSCFG_LCSN1 (1U<<0)
#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
/* EP93xx System Controller software locked register write */
--
2.11.0
^ permalink raw reply related
* [PATCH 02/15] ARM: davinci: cleanup cppcheck shifting errors
From: Phong Tran @ 2019-06-23 15:13 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
[arch/arm/mach-davinci/cpuidle.c:41]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/mach-davinci/cpuidle.c:43]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-davinci/ddr2.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-davinci/ddr2.h b/arch/arm/mach-davinci/ddr2.h
index 4f7d7824b0c9..76d78ffe2702 100644
--- a/arch/arm/mach-davinci/ddr2.h
+++ b/arch/arm/mach-davinci/ddr2.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
#define DDR2_SDRCR_OFFSET 0xc
-#define DDR2_SRPD_BIT (1 << 23)
-#define DDR2_MCLKSTOPEN_BIT (1 << 30)
-#define DDR2_LPMODEN_BIT (1 << 31)
+#define DDR2_SRPD_BIT (1U << 23)
+#define DDR2_MCLKSTOPEN_BIT (1U << 30)
+#define DDR2_LPMODEN_BIT (1U << 31)
--
2.11.0
^ permalink raw reply related
* [PATCH 01/15] arm: perf: cleanup cppcheck shifting error
From: Phong Tran @ 2019-06-23 15:12 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
fix "Shifting signed 32-bit value by 31 bits is undefined behaviour
errors"
[arch/arm/kernel/perf_event_v7.c:1080]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/kernel/perf_event_v7.c:1436]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/kernel/perf_event_v7.c:1783]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/kernel/perf_event_v7.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index a4fb0f8b8f84..83dc472a39b2 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -697,9 +697,9 @@ static struct attribute_group armv7_pmuv2_events_attr_group = {
/*
* Event filters for PMUv2
*/
-#define ARMV7_EXCLUDE_PL1 (1 << 31)
-#define ARMV7_EXCLUDE_USER (1 << 30)
-#define ARMV7_INCLUDE_HYP (1 << 27)
+#define ARMV7_EXCLUDE_PL1 (1U << 31)
+#define ARMV7_EXCLUDE_USER (1U << 30)
+#define ARMV7_INCLUDE_HYP (1U << 27)
/*
* Secure debug enable reg
--
2.11.0
^ permalink raw reply related
* [PATCH 00/15] cleanup cppcheck signed shifting errors
From: Phong Tran @ 2019-06-23 15:12 UTC (permalink / raw)
To: mark.rutland, kstewart, songliubraving, andrew, peterz, nsekhar,
ast, jolsa, netdev, gerg, lorenzo.pieralisi, will,
linux-samsung-soc, daniel, tranmanphong, festevam,
gregory.clement, allison, linux, krzk, haojian.zhuang,
bgolaszewski, tony, mingo, linux-imx, yhs, sebastian.hesselbarth,
illusionist.neo, jason, liviu.dudau, s.hauer, acme, lkundrak,
robert.jarzmik, dmg, swinslow, namhyung, tglx, linux-omap,
alexander.sverdlin, linux-arm-kernel, info, gregkh, linux-kernel,
alexander.shishkin, hsweeten, kgene, kernel, sudeep.holla, bpf,
shawnguo, kafai, daniel
There are errors with cppcheck
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
This is just a mirror changing.
Phong Tran (15):
arm: perf: cleanup cppcheck shifting error
ARM: davinci: cleanup cppcheck shifting errors
ARM: ep93xx: cleanup cppcheck shifting errors
ARM: exynos: cleanup cppcheck shifting error
ARM: footbridge: cleanup cppcheck shifting error
ARM: imx: cleanup cppcheck shifting errors
ARM: ks8695: cleanup cppcheck shifting error
ARM: mmp: cleanup cppcheck shifting errors
ARM: omap2: cleanup cppcheck shifting error
ARM: orion5x: cleanup cppcheck shifting errors
ARM: pxa: cleanup cppcheck shifting errors
ARM: vexpress: cleanup cppcheck shifting error
ARM: mm: cleanup cppcheck shifting errors
ARM: bpf: cleanup cppcheck shifting error
ARM: vfp: cleanup cppcheck shifting errors
arch/arm/kernel/perf_event_v7.c | 6 +-
arch/arm/mach-davinci/ddr2.h | 6 +-
arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++-------------------
arch/arm/mach-exynos/suspend.c | 2 +-
arch/arm/mach-footbridge/dc21285.c | 2 +-
arch/arm/mach-imx/iomux-mx3.h | 64 +++++++++---------
arch/arm/mach-ks8695/regs-pci.h | 4 +-
arch/arm/mach-mmp/pm-mmp2.h | 40 +++++------
arch/arm/mach-mmp/pm-pxa910.h | 76 ++++++++++-----------
arch/arm/mach-omap2/powerdomain.c | 2 +-
arch/arm/mach-orion5x/pci.c | 8 +--
arch/arm/mach-pxa/irq.c | 4 +-
arch/arm/mach-vexpress/spc.c | 12 ++--
arch/arm/mm/fault.h | 6 +-
arch/arm/net/bpf_jit_32.c | 2 +-
arch/arm/vfp/vfpinstr.h | 28 ++++----
16 files changed, 197 insertions(+), 197 deletions(-)
--
2.11.0
^ permalink raw reply
* Re: [PATCH] net: dsa: microchip: Use gpiod_set_value_cansleep()
From: Marek Vasut @ 2019-06-23 15:12 UTC (permalink / raw)
To: Andrew Lunn
Cc: netdev, Florian Fainelli, Linus Walleij, Tristram Ha, Woojung Huh
In-Reply-To: <20190623150959.GC28942@lunn.ch>
On 6/23/19 5:09 PM, Andrew Lunn wrote:
> On Sun, Jun 23, 2019 at 02:10:36PM +0200, Marek Vasut wrote:
>> Replace gpiod_set_value() with gpiod_set_value_cansleep(), as the switch
>> reset GPIO can be connected to e.g. I2C GPIO expander and it is perfectly
>> fine for the kernel to sleep for a bit in ksz_switch_register().
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Actually, no, I missed a change in .remove , so I'll send a V2 with this
RB if you don't mind.
--
Best regards,
Marek Vasut
^ permalink raw reply
* Re: [PATCH] net: dsa: microchip: Use gpiod_set_value_cansleep()
From: Andrew Lunn @ 2019-06-23 15:09 UTC (permalink / raw)
To: Marek Vasut
Cc: netdev, Florian Fainelli, Linus Walleij, Tristram Ha, Woojung Huh
In-Reply-To: <20190623121036.3430-1-marex@denx.de>
On Sun, Jun 23, 2019 at 02:10:36PM +0200, Marek Vasut wrote:
> Replace gpiod_set_value() with gpiod_set_value_cansleep(), as the switch
> reset GPIO can be connected to e.g. I2C GPIO expander and it is perfectly
> fine for the kernel to sleep for a bit in ksz_switch_register().
>
> Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* Re: [PATCH v4 4/5] net: macb: add support for high speed interface
From: Andrew Lunn @ 2019-06-23 15:09 UTC (permalink / raw)
To: Parshuram Thombare
Cc: nicolas.ferre, davem, f.fainelli, linux, netdev, hkallweit1,
linux-kernel, rafalc, aniljoy, piotrs
In-Reply-To: <1561281806-13991-1-git-send-email-pthombar@cadence.com>
> +enum {
> + HS_MAC_SPEED_100M,
> + HS_MAC_SPEED_1000M,
> + HS_MAC_SPEED_2500M,
> + HS_MAC_SPEED_5000M,
> + HS_MAC_SPEED_10000M,
> + HS_MAC_SPEED_25000M,
> +};
> +
> +enum {
> + MACB_SERDES_RATE_5_PT_15625Gbps = 5,
> + MACB_SERDES_RATE_10_PT_3125Gbps = 10,
> +};
What do the units mean here? Why would you clock the SERDES at 15Tbps,
or 3Tbps? 3.125Mbps would give you 2.5Gbps when using 8b/10b encoding.
> + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
> + switch (bp->serdes_rate) {
> + case MACB_SERDES_RATE_5_PT_15625Gbps:
> + rate = 78125000;
> + break;
> + case MACB_SERDES_RATE_10_PT_3125Gbps:
> + rate = 156250000;
> + break;
> + default:
> + return;
> + }
Xilinx documentation:
https://www.xilinx.com/support/documentation/ip_documentation/usxgmii/v1_1/pg251-usxgmii.pdf
seems to suggest USXGMII uses a fixed rate of 10.3125Gb/s. So why do
you need to change the rate?
Andrew
^ permalink raw reply
* stmmac regression on ASUS TinkerBoard
From: Katsuhiro Suzuki @ 2019-06-23 14:14 UTC (permalink / raw)
To: Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, Maxime Coquelin,
netdev
Cc: Andrew Lunn, Heiko Stuebner, linux-arm-kernel,
Linux Kernel Mailing List
Hello stmmac maintainers,
I found this commit and that has some regressions:
74371272f97f net: stmmac: Convert to phylink and remove phylib logic
My environment is:
- ASUS TinkerBoard
- SoC is RK3288
- Using STMMAC driver
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
- Using this device-tree
arch/arm/boot/dts/rk3288.dtsi ('gmac: ethernet@ff290000' node)
Current linux-next on my environment, 'ifconfig eth0 up' does not work
correctly with following message...
-----
root@linaro-alip:~# ifconfig eth0 up
[ 105.028916] rk_gmac-dwmac ff290000.ethernet eth0: stmmac_open: Cannot
attach to PHY (error: -19)
SIOCSIFFLAGS: No such device
-----
I checked drivers/net/ethernet/stmicro/stmmac/stmmac_main.c and found
stmmac_init_phy() is going to fail if ethernet device node does not
have following property:
- phy-handle
- phy
- phy-device
This commit broke the device-trees such as TinkerBoard. The mdio
subnode creating a mdio bus is changed to required or still optional?
Best Regards,
Katsuhiro Suzuki
^ permalink raw reply
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