* linux-next: Signed-off-by missing for commit in the net-next tree
From: Stephen Rothwell @ 2019-09-10 14:41 UTC (permalink / raw)
To: David Miller, Networking
Cc: Linux Next Mailing List, Linux Kernel Mailing List,
The j1939 authors, Bastian Stender, Elenita Hinds, Kurt Van Dijck,
kbuild test robot, Maxime Jayat, Robin van der Gracht,
Oleksij Rempel, Marc Kleine-Budde
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Hi all,
Commit
9d71dd0c7009 ("can: add support of SAE J1939 protocol")
is missing a Signed-off-by from its author.
[Not sure if I should complain about this one ...]
--
Cheers,
Stephen Rothwell
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH net-next 4/6] net: stmmac: Add support for SA Insertion/Replacement in GMAC4+
From: Jose Abreu @ 2019-09-10 14:41 UTC (permalink / raw)
To: netdev
Cc: Joao Pinto, Jose Abreu, Giuseppe Cavallaro, Alexandre Torgue,
David S. Miller, Maxime Coquelin, linux-stm32, linux-arm-kernel,
linux-kernel
In-Reply-To: <cover.1568126224.git.joabreu@synopsys.com>
Add the support for Source Address Insertion and Replacement in GMAC4
and GMAC5 cores. Two methods are supported: Descriptor based and
register based.
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
---
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Jose Abreu <joabreu@synopsys.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: netdev@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 3 +++
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 13 +++++++++++++
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c | 8 ++++++++
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 1 +
5 files changed, 26 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index 4dfa69850040..fad121cbfe0e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -160,6 +160,8 @@ enum power_event {
#define GMAC_DEBUG_RPESTS BIT(0)
/* MAC config */
+#define GMAC_CONFIG_SARC GENMASK(30, 28)
+#define GMAC_CONFIG_SARC_SHIFT 28
#define GMAC_CONFIG_IPC BIT(27)
#define GMAC_CONFIG_2K BIT(22)
#define GMAC_CONFIG_ACS BIT(20)
@@ -175,6 +177,7 @@ enum power_event {
#define GMAC_CONFIG_RE BIT(0)
/* MAC HW features0 bitmap */
+#define GMAC_HW_FEAT_SAVLANINS BIT(27)
#define GMAC_HW_FEAT_ADDMAC BIT(18)
#define GMAC_HW_FEAT_RXCOESEL BIT(16)
#define GMAC_HW_FEAT_TXCOSEL BIT(14)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index 5b43a8df1536..73dbfd810fca 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -759,6 +759,16 @@ static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
}
}
+static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
+{
+ u32 value = readl(ioaddr + GMAC_CONFIG);
+
+ value &= ~GMAC_CONFIG_SARC;
+ value |= val << GMAC_CONFIG_SARC_SHIFT;
+
+ writel(value, ioaddr + GMAC_CONFIG);
+}
+
const struct stmmac_ops dwmac4_ops = {
.core_init = dwmac4_core_init,
.set_mac = stmmac_set_mac,
@@ -790,6 +800,7 @@ const struct stmmac_ops dwmac4_ops = {
.set_filter = dwmac4_set_filter,
.set_mac_loopback = dwmac4_set_mac_loopback,
.update_vlan_hash = dwmac4_update_vlan_hash,
+ .sarc_configure = dwmac4_sarc_configure,
};
const struct stmmac_ops dwmac410_ops = {
@@ -823,6 +834,7 @@ const struct stmmac_ops dwmac410_ops = {
.set_filter = dwmac4_set_filter,
.set_mac_loopback = dwmac4_set_mac_loopback,
.update_vlan_hash = dwmac4_update_vlan_hash,
+ .sarc_configure = dwmac4_sarc_configure,
};
const struct stmmac_ops dwmac510_ops = {
@@ -861,6 +873,7 @@ const struct stmmac_ops dwmac510_ops = {
.flex_pps_config = dwmac5_flex_pps_config,
.set_mac_loopback = dwmac4_set_mac_loopback,
.update_vlan_hash = dwmac4_update_vlan_hash,
+ .sarc_configure = dwmac4_sarc_configure,
};
int dwmac4_setup(struct stmmac_priv *priv)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
index dbde23e7e169..8edc9f8787cc 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
@@ -443,6 +443,13 @@ static void dwmac4_clear(struct dma_desc *p)
p->des3 = 0;
}
+static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
+{
+ sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT;
+
+ p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK);
+}
+
static int set_16kib_bfsize(int mtu)
{
int ret = 0;
@@ -476,6 +483,7 @@ const struct stmmac_desc_ops dwmac4_desc_ops = {
.get_addr = dwmac4_get_addr,
.set_addr = dwmac4_set_addr,
.clear = dwmac4_clear,
+ .set_sarc = dwmac4_set_sarc,
};
const struct stmmac_mode_ops dwmac4_ring_mode_ops = {
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h
index f58191174287..6089d76a00d3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h
@@ -32,6 +32,7 @@
#define TDES3_HDR_LEN_SHIFT 19
#define TDES3_SLOT_NUMBER_MASK GENMASK(22, 19)
#define TDES3_SA_INSERT_CTRL_MASK GENMASK(25, 23)
+#define TDES3_SA_INSERT_CTRL_SHIFT 23
#define TDES3_CRC_PAD_CTRL_MASK GENMASK(27, 26)
/* TDES3 (write back format) */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index 2456f421aac9..82d9761b2df2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -348,6 +348,7 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr,
/* TX and RX csum */
dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
+ dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
/* MAC HW feature1 */
hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
--
2.7.4
^ permalink raw reply related
* linux-next: Signed-off-by missing for commit in the net-next tree
From: Stephen Rothwell @ 2019-09-10 14:42 UTC (permalink / raw)
To: David Miller, Networking
Cc: Linux Next Mailing List, Linux Kernel Mailing List, Luca Coelho,
Alex Malamud
[-- Attachment #1: Type: text/plain, Size: 146 bytes --]
Hi all,
Commit
aa43ae121675 ("iwlwifi: LTR updates")
is missing a Signed-off-by from its committer.
--
Cheers,
Stephen Rothwell
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH bpf-next 01/11] samples: bpf: makefile: fix HDR_PROBE "echo"
From: Ivan Khoronzhuk @ 2019-09-10 14:54 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: ast, daniel, yhs, davem, jakub.kicinski, hawk, john.fastabend,
linux-kernel, netdev, bpf, clang-built-linux
In-Reply-To: <55803f7e-a971-d71a-fcc2-76ae1cf813bf@cogentembedded.com>
On Tue, Sep 10, 2019 at 01:46:48PM +0300, Sergei Shtylyov wrote:
>Hello!
>
>On 10.09.2019 13:38, Ivan Khoronzhuk wrote:
>
>>echo should be replaced on echo -e to handle \n correctly, but instead,
>
> s/on/with/?
s/echo/printf/ instead of s/echo/echo -e/
printf looks better.
>
>>replace it on printf as some systems can't handle echo -e.
>
> Likewise?
Like some, better avoid ambiguity, for me it works fine - is not enough.
https://pubs.opengroup.org/onlinepubs/9699919799/utilities/echo.html
"A string to be written to standard output. If the first operand is
-n, or if any of the operands contain a <backslash> character, the
results are implementation-defined"
I can guess its Mac vs Linux, but it does mean nothing if it's defined as
implementation dependent, can be any.
>
>>Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
>[...]
>
>MBR, Sergei
>
--
Regards,
Ivan Khoronzhuk
^ permalink raw reply
* Re: [PATCH net-next] ipv6: Don't use dst gateway directly in ip6_confirm_neigh()
From: Guillaume Nault @ 2019-09-10 15:03 UTC (permalink / raw)
To: Stefano Brivio
Cc: David Miller, Julian Anastasov, Nicolas Dichtel, David Ahern,
netdev
In-Reply-To: <938b711c35ce3fa2b6f057cc23919e897a1e5c2b.1568061608.git.sbrivio@redhat.com>
On Mon, Sep 09, 2019 at 10:44:06PM +0200, Stefano Brivio wrote:
> This is the equivalent of commit 2c6b55f45d53 ("ipv6: fix neighbour
> resolution with raw socket") for ip6_confirm_neigh(): we can send a
> packet with MSG_CONFIRM on a raw socket for a connected route, so the
> gateway would be :: here, and we should pick the next hop using
> rt6_nexthop() instead.
>
> This was found by code review and, to the best of my knowledge, doesn't
> actually fix a practical issue: the destination address from the packet
> is not considered while confirming a neighbour, as ip6_confirm_neigh()
> calls choose_neigh_daddr() without passing the packet, so there are no
> similar issues as the one fixed by said commit.
>
> A possible source of issues with the existing implementation might come
> from the fact that, if we have a cached dst, we won't consider it,
> while rt6_nexthop() takes care of that. I might just not be creative
> enough to find a practical problem here: the only way to affect this
> with cached routes is to have one coming from an ICMPv6 redirect, but
> if the next hop is a directly connected host, there should be no
> topology for which a redirect applies here, and tests with redirected
> routes show no differences for MSG_CONFIRM (and MSG_PROBE) packets on
> raw sockets destined to a directly connected host.
>
> However, directly using the dst gateway here is not consistent anymore
> with neighbour resolution, and, in general, as we want the next hop,
> using rt6_nexthop() looks like the only sane way to fetch it.
>
> Reported-by: Guillaume Nault <gnault@redhat.com>
> Signed-off-by: Stefano Brivio <sbrivio@redhat.com>
> ---
> net/ipv6/route.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/net/ipv6/route.c b/net/ipv6/route.c
> index 7a5d331cdefa..874641d4d2a1 100644
> --- a/net/ipv6/route.c
> +++ b/net/ipv6/route.c
> @@ -227,7 +227,7 @@ static void ip6_confirm_neigh(const struct dst_entry *dst, const void *daddr)
> struct net_device *dev = dst->dev;
> struct rt6_info *rt = (struct rt6_info *)dst;
>
> - daddr = choose_neigh_daddr(&rt->rt6i_gateway, NULL, daddr);
> + daddr = choose_neigh_daddr(rt6_nexthop(rt, &in6addr_any), NULL, daddr);
> if (!daddr)
> return;
> if (dev->flags & (IFF_NOARP | IFF_LOOPBACK))
>
Acked-by: Guillaume Nault <gnault@redhat.com>
^ permalink raw reply
* RE: [PATCH] net/mlx5: reduce stack usage in FW tracer
From: David Laight @ 2019-09-10 15:38 UTC (permalink / raw)
To: 'Arnd Bergmann', Saeed Mahameed
Cc: cai@lca.pw, linux-rdma@vger.kernel.org, davem@davemloft.net,
Moshe Shemesh, Feras Daoud, linux-kernel@vger.kernel.org,
Eran Ben Elisha, netdev@vger.kernel.org, leon@kernel.org,
Erez Shitrit
In-Reply-To: <CAK8P3a3q4NqiU-OydMqU3J=gT-8eBmsiL5tPsyJb1PNgR+48hA@mail.gmail.com>
From: Arnd Bergmann
> Sent: 10 September 2019 09:15
...
> > I am not sure how this would work, since the format parameters can
> > changes depending on the FW string and the specific traces.
>
> Ah, so the format string comes from the firmware? I didn't look
> at the code in enough detail to understand why it's done like this,
> only enough to notice that it's rather unusual.
If the format string comes from the firmware you really shouldn't
pass it to any standard printf function.
You must ensure that it doesn't contain any format effectors
that might dereference parameters.
(The code might try to do that.)
Given that 'pointer' format effectors can't be used, the firmware
must also supply the relevant integer ones?
This should mean that all the processing is deferrable until the
trace record is read.
'noinline' just papers over the cracks.
Especially since vasprintf() is likely to use a lot of stack.
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
^ permalink raw reply
* [PATCH 0/7] net: dsa: mv88e6xxx: features to handle network storms
From: Robert Beckett @ 2019-09-10 15:41 UTC (permalink / raw)
To: netdev
Cc: Robert Beckett, Andrew Lunn, Vivien Didelot, Florian Fainelli,
David S. Miller
This patch-set adds support for some features of the Marvell switch
chips that can be used to handle packet storms.
The rationale for this was a setup that requires the ability to receive
traffic from one port, while a packet storm is occuring on another port
(via an external switch with a deliberate loop). This is needed to
ensure vital data delivery from a specific port, while mitigating any
loops or DoS that a user may introduce on another port (can't guarantee
sensible users).
[patch 1/7] configures auto negotiation for CPU ports connected with
phys to enable pause frame propogation.
[patch 2/7] allows setting of port's default output queue priority for
any ingressing packets on that port.
[patch 3/7] dt-bindings for patch 2.
[patch 4/7] allows setting of a port's queue scheduling so that it can
prioritise egress of traffic routed from high priority ports.
[patch 5/7] dt-bindings for patch 4.
[patch 6/7] allows ports to rate limit their egress. This can be used to
stop the host CPU from becoming swamped by packet delivery and exhasting
descriptors.
[patch 7/7] dt-bindings for patch 6.
Robert Beckett (7):
net/dsa: configure autoneg for CPU port
net: dsa: mv88e6xxx: add ability to set default queue priorities per
port
dt-bindings: mv88e6xxx: add ability to set default queue priorities
per port
net: dsa: mv88e6xxx: add ability to set queue scheduling
dt-bindings: mv88e6xxx: add ability to set queue scheduling
net: dsa: mv88e6xxx: add egress rate limiting
dt-bindings: mv88e6xxx: add egress rate limiting
.../devicetree/bindings/net/dsa/marvell.txt | 38 +++++
drivers/net/dsa/mv88e6xxx/chip.c | 122 ++++++++++++---
drivers/net/dsa/mv88e6xxx/chip.h | 5 +-
drivers/net/dsa/mv88e6xxx/port.c | 140 +++++++++++++++++-
drivers/net/dsa/mv88e6xxx/port.h | 24 ++-
include/dt-bindings/net/dsa-mv88e6xxx.h | 22 +++
net/dsa/port.c | 10 ++
7 files changed, 327 insertions(+), 34 deletions(-)
create mode 100644 include/dt-bindings/net/dsa-mv88e6xxx.h
--
2.18.0
^ permalink raw reply
* [PATCH 1/7] net/dsa: configure autoneg for CPU port
From: Robert Beckett @ 2019-09-10 15:41 UTC (permalink / raw)
To: netdev
Cc: Robert Beckett, Andrew Lunn, Vivien Didelot, Florian Fainelli,
David S. Miller
In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com>
Configure autoneg for phy connected CPU ports.
This allows us to use autoneg between the CPU port's phy and the link
partner's phy.
This enables us to negoatiate pause frame transmission to prioritise
packet delivery over throughput.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
net/dsa/port.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/net/dsa/port.c b/net/dsa/port.c
index f071acf2842b..1b6832eac2c5 100644
--- a/net/dsa/port.c
+++ b/net/dsa/port.c
@@ -538,10 +538,20 @@ static int dsa_port_setup_phy_of(struct dsa_port *dp, bool enable)
return PTR_ERR(phydev);
if (enable) {
+ phydev->supported = PHY_GBIT_FEATURES | SUPPORTED_MII |
+ SUPPORTED_AUI | SUPPORTED_FIBRE |
+ SUPPORTED_BNC | SUPPORTED_Pause |
+ SUPPORTED_Asym_Pause;
+ phydev->advertising = phydev->supported;
+
err = genphy_config_init(phydev);
if (err < 0)
goto err_put_dev;
+ err = genphy_config_aneg(phydev);
+ if (err < 0)
+ goto err_put_dev;
+
err = genphy_resume(phydev);
if (err < 0)
goto err_put_dev;
--
2.18.0
^ permalink raw reply related
* [PATCH 2/7] net: dsa: mv88e6xxx: add ability to set default queue priorities per port
From: Robert Beckett @ 2019-09-10 15:41 UTC (permalink / raw)
To: netdev
Cc: Robert Beckett, Andrew Lunn, Vivien Didelot, Florian Fainelli,
David S. Miller
In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com>
Add code to set DefQPri for any port that specifies "defqpri" in their
device tree node.
This allows setting the default output queue priority for all packets
entering the switch via the port that uses this, which is useful for
prioritizing traffic based on port.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 25 +++++++++++++++++++++++++
drivers/net/dsa/mv88e6xxx/chip.h | 1 +
drivers/net/dsa/mv88e6xxx/port.c | 19 +++++++++++++++++++
drivers/net/dsa/mv88e6xxx/port.h | 4 ++++
4 files changed, 49 insertions(+)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index d0a97eb73a37..5005a35493e3 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -2086,6 +2086,23 @@ static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
return 0;
}
+static int mv88e6xxx_set_port_defqpri(struct mv88e6xxx_chip *chip, int port)
+{
+ struct dsa_switch *ds = chip->ds;
+ struct device_node *dn = ds->ports[port].dn;
+ int err;
+ u32 pri;
+
+ if (!dn || !chip->info->ops->port_set_defqpri)
+ return 0;
+
+ err = of_property_read_u32(dn, "defqpri", &pri);
+ if (err < 0)
+ return 0;
+
+ return chip->info->ops->port_set_defqpri(chip, port, (u16)pri);
+}
+
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
{
struct dsa_switch *ds = chip->ds;
@@ -2176,6 +2193,10 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
return err;
}
+ err = mv88e6xxx_set_port_defqpri(chip, port);
+ if (err)
+ return err;
+
/* Port Association Vector: when learning source addresses
* of packets, add the address to the address database using
* a port bitmap that has only the bit for this port set and
@@ -3107,6 +3128,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
+ .port_set_defqpri = mv88e6xxx_port_set_defqpri,
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
@@ -3190,6 +3212,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
+ .port_set_defqpri = mv88e6xxx_port_set_defqpri,
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
@@ -3407,6 +3430,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
+ .port_set_defqpri = mv88e6xxx_port_set_defqpri,
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
@@ -3750,6 +3774,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
+ .port_set_defqpri = mv88e6xxx_port_set_defqpri,
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index 4646e46d47f2..2d2c24f5a79d 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -383,6 +383,7 @@ struct mv88e6xxx_ops {
u16 etype);
int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
size_t size);
+ int (*port_set_defqpri)(struct mv88e6xxx_chip *chip, int port, u16 pri);
int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 04309ef0a1cc..3a45fcd5cd9c 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -1147,6 +1147,25 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
}
+int mv88e6xxx_port_set_defqpri(struct mv88e6xxx_chip *chip, int port, u16 pri)
+{
+ u16 reg;
+ int err;
+
+ if (pri > 3)
+ return -EINVAL;
+
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
+ if (err)
+ return err;
+
+ reg &= ~MV88E6XXX_PORT_CTL2_DEFQPRI_MASK;
+ reg |= pri << MV88E6XXX_PORT_CTL2_DEFQPRI_SHIFT;
+ reg |= MV88E6XXX_PORT_CTL2_USE_DEFQPRI;
+
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
+}
+
/* Offset 0x09: Port Rate Control */
int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 8d5a6cd6fb19..03884bbaa762 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -197,6 +197,9 @@
#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040
#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020
#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010
+#define MV88E6XXX_PORT_CTL2_USE_DEFQPRI 0x0008
+#define MV88E6XXX_PORT_CTL2_DEFQPRI_MASK 0x0006
+#define MV88E6XXX_PORT_CTL2_DEFQPRI_SHIFT 1
#define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f
/* Offset 0x09: Egress Rate Control */
@@ -326,6 +329,7 @@ int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
bool message_port);
int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
size_t size);
+int mv88e6xxx_port_set_defqpri(struct mv88e6xxx_chip *chip, int port, u16 pri);
int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
--
2.18.0
^ permalink raw reply related
* [PATCH 3/7] dt-bindings: mv88e6xxx: add ability to set default queue priorities per port
From: Robert Beckett @ 2019-09-10 15:41 UTC (permalink / raw)
To: netdev
Cc: Robert Beckett, Andrew Lunn, Vivien Didelot, Florian Fainelli,
David S. Miller, Rob Herring, Mark Rutland, devicetree
In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com>
Document a new setting for Marvell switch chips to set the default queue
priorities per port.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
Documentation/devicetree/bindings/net/dsa/marvell.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt
index 6f9538974bb9..e097c3c52eac 100644
--- a/Documentation/devicetree/bindings/net/dsa/marvell.txt
+++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt
@@ -47,6 +47,10 @@ Optional properties:
bus. The node must contains a compatible string of
"marvell,mv88e6xxx-mdio-external"
+Optional properties for ports:
+- defqpri=<n> : Enforced default queue priority for the given port.
+ Valid range is 0..3
+
Example:
mdio {
--
2.18.0
^ permalink raw reply related
* [PATCH 4/7] net: dsa: mv88e6xxx: add ability to set queue scheduling
From: Robert Beckett @ 2019-09-10 15:41 UTC (permalink / raw)
To: netdev
Cc: Robert Beckett, Andrew Lunn, Vivien Didelot, Florian Fainelli,
David S. Miller
In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com>
Add code to set Schedule for any port that specifies "schedule" in their
device tree node.
This allows port prioritization in conjunction with port default queue
priorities or packet priorities.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 25 +++++++++++++++++++++++++
drivers/net/dsa/mv88e6xxx/chip.h | 1 +
drivers/net/dsa/mv88e6xxx/port.c | 21 +++++++++++++++++++++
drivers/net/dsa/mv88e6xxx/port.h | 6 ++++++
4 files changed, 53 insertions(+)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 5005a35493e3..2bc22c59200c 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -2103,6 +2103,23 @@ static int mv88e6xxx_set_port_defqpri(struct mv88e6xxx_chip *chip, int port)
return chip->info->ops->port_set_defqpri(chip, port, (u16)pri);
}
+static int mv88e6xxx_set_port_sched(struct mv88e6xxx_chip *chip, int port)
+{
+ struct dsa_switch *ds = chip->ds;
+ struct device_node *dn = ds->ports[port].dn;
+ int err;
+ u32 sched;
+
+ if (!dn || !chip->info->ops->port_set_sched)
+ return 0;
+
+ err = of_property_read_u32(dn, "schedule", &sched);
+ if (err < 0)
+ return 0;
+
+ return chip->info->ops->port_set_sched(chip, port, (u16)sched);
+}
+
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
{
struct dsa_switch *ds = chip->ds;
@@ -2218,6 +2235,10 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
if (err)
return err;
+ err = mv88e6xxx_set_port_sched(chip, port);
+ if (err)
+ return err;
+
if (chip->info->ops->port_pause_limit) {
err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
if (err)
@@ -3130,6 +3151,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
.port_set_defqpri = mv88e6xxx_port_set_defqpri,
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_set_sched = mv88e6xxx_port_set_sched,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3214,6 +3236,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
.port_set_defqpri = mv88e6xxx_port_set_defqpri,
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_set_sched = mv88e6xxx_port_set_sched,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3432,6 +3455,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
.port_set_defqpri = mv88e6xxx_port_set_defqpri,
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_set_sched = mv88e6xxx_port_set_sched,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3776,6 +3800,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
.port_set_defqpri = mv88e6xxx_port_set_defqpri,
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_set_sched = mv88e6xxx_port_set_sched,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index 2d2c24f5a79d..ff3e35eceee0 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -386,6 +386,7 @@ struct mv88e6xxx_ops {
int (*port_set_defqpri)(struct mv88e6xxx_chip *chip, int port, u16 pri);
int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
+ int (*port_set_sched)(struct mv88e6xxx_chip *chip, int port, u16 sched);
int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
u8 out);
int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 3a45fcd5cd9c..236732fc598d 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -1180,6 +1180,27 @@ int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
0x0001);
}
+/* Offset 0x0A: Egress Rate Control 2 */
+int mv88e6xxx_port_set_sched(struct mv88e6xxx_chip *chip, int port, u16 sched)
+{
+ u16 reg;
+ int err;
+
+ if (sched > MV88E6XXX_PORT_SCHED_STRICT_ALL)
+ return -EINVAL;
+
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
+ ®);
+ if (err)
+ return err;
+
+ reg &= ~MV88E6XXX_PORT_SCHED_MASK;
+ reg |= sched << MV88E6XXX_PORT_SCHED_SHIFT;
+
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
+ reg);
+}
+
/* Offset 0x0C: Port ATU Control */
int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 03884bbaa762..710d6eccafae 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -11,6 +11,7 @@
#ifndef _MV88E6XXX_PORT_H
#define _MV88E6XXX_PORT_H
+#include <dt-bindings/net/dsa-mv88e6xxx.h>
#include "chip.h"
/* Offset 0x00: Port Status Register */
@@ -207,6 +208,10 @@
/* Offset 0x0A: Egress Rate Control 2 */
#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a
+#define MV88E6XXX_PORT_SCHED_SHIFT 12
+#define MV88E6XXX_PORT_SCHED_MASK \
+ (0x3 << MV88E6XXX_PORT_SCHED_SHIFT)
+/* see MV88E6XXX_PORT_SCHED_* in include/dt-bindings/net/dsa-mv88e6xxx.h */
/* Offset 0x0B: Port Association Vector */
#define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b
@@ -332,6 +337,7 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
int mv88e6xxx_port_set_defqpri(struct mv88e6xxx_chip *chip, int port, u16 pri);
int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
+int mv88e6xxx_port_set_sched(struct mv88e6xxx_chip *chip, int port, u16 sched);
int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
u8 out);
int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
--
2.18.0
^ permalink raw reply related
* [PATCH 5/7] dt-bindings: mv88e6xxx: add ability to set queue scheduling
From: Robert Beckett @ 2019-09-10 15:41 UTC (permalink / raw)
To: netdev
Cc: Robert Beckett, Andrew Lunn, Vivien Didelot, Florian Fainelli,
David S. Miller, Rob Herring, Mark Rutland, devicetree
In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com>
Document port queue scheduling settings.
Add definitions for specific valid values.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
.../devicetree/bindings/net/dsa/marvell.txt | 12 ++++++++++++
include/dt-bindings/net/dsa-mv88e6xxx.h | 17 +++++++++++++++++
2 files changed, 29 insertions(+)
create mode 100644 include/dt-bindings/net/dsa-mv88e6xxx.h
diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt
index e097c3c52eac..7de90929c3c9 100644
--- a/Documentation/devicetree/bindings/net/dsa/marvell.txt
+++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt
@@ -50,6 +50,18 @@ Optional properties:
Optional properties for ports:
- defqpri=<n> : Enforced default queue priority for the given port.
Valid range is 0..3
+- schedule=<n> : Set ports scheduling mode. Valid values are:
+ MV88E6XXX_PORT_SCHED_ROUND_ROBIN - All output queues
+ use a weighter round robin scheme.
+ MV88E6XXX_PORT_SCHED_STRICT_3 - Output queue 3 uses
+ a strict scheme, where any packets in queue 3 will be
+ egressed first, followed by weighted round robin for
+ the other ports.
+ MV88E6XXX_PORT_SCHED_STRICT_3_2 - Output queue's 2
+ and 3 use strict, other use weighted round robin.
+ MV88E6XXX_PORT_SCHED_STRICT_ALL - All queues use
+ strict priority, where queues drain in descending
+ queue number order.
Example:
diff --git a/include/dt-bindings/net/dsa-mv88e6xxx.h b/include/dt-bindings/net/dsa-mv88e6xxx.h
new file mode 100644
index 000000000000..3f62003841ce
--- /dev/null
+++ b/include/dt-bindings/net/dsa-mv88e6xxx.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree constants for Marvell 88E6xxx Switch Port Registers
+ *
+ * Copyright (c) 2019, Collabora Ltd.
+ * Copyright (c) 2019, General Electric Company
+ */
+
+#ifndef _DT_BINDINGS_MV88E6XXX_H
+#define _DT_BINDINGS_MV88E6XXX_H
+
+#define MV88E6XXX_PORT_SCHED_ROUND_ROBIN 0
+#define MV88E6XXX_PORT_SCHED_STRICT_3 1
+#define MV88E6XXX_PORT_SCHED_STRICT_3_2 2
+#define MV88E6XXX_PORT_SCHED_STRICT_ALL 3
+
+#endif /* _DT_BINDINGS_MV88E6XXX_H */
--
2.18.0
^ permalink raw reply related
* Re: [PATCH v3 1/2] PTP: introduce new versions of IOCTLs
From: Richard Cochran @ 2019-09-10 15:44 UTC (permalink / raw)
To: Felipe Balbi; +Cc: Christopher S Hall, netdev, linux-kernel
In-Reply-To: <20190909075940.12843-1-felipe.balbi@linux.intel.com>
On Mon, Sep 09, 2019 at 10:59:39AM +0300, Felipe Balbi wrote:
> case PTP_PEROUT_REQUEST:
> + case PTP_PEROUT_REQUEST2:
...
> + if (((req.perout.flags & ~PTP_PEROUT_VALID_FLAGS) ||
> + req.perout.rsv[0] || req.perout.rsv[1] ||
> + req.perout.rsv[2] || req.perout.rsv[3]) &&
> + cmd == PTP_PEROUT_REQUEST2) {
> + err = -EINVAL;
> + break;
...
> +/*
> + * Bits of the ptp_perout_request.flags field:
> + */
> +#define PTP_PEROUT_VALID_FLAGS (~0)
I think you meant (0) here, or I am confused...
Thanks,
Richard
^ permalink raw reply
* [PATCH 6/7] net: dsa: mv88e6xxx: add egress rate limiting
From: Robert Beckett @ 2019-09-10 15:41 UTC (permalink / raw)
To: netdev
Cc: Robert Beckett, Andrew Lunn, Vivien Didelot, Florian Fainelli,
David S. Miller
In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com>
Add code for specifying egress rate limiting per port.
The rate can be specified as ethernet frames or bits per second.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 72 ++++++++++++++-------
drivers/net/dsa/mv88e6xxx/chip.h | 3 +-
drivers/net/dsa/mv88e6xxx/port.c | 106 ++++++++++++++++++++++++++++---
drivers/net/dsa/mv88e6xxx/port.h | 14 +++-
4 files changed, 158 insertions(+), 37 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 2bc22c59200c..8c116496ab2f 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -2120,6 +2120,32 @@ static int mv88e6xxx_set_port_sched(struct mv88e6xxx_chip *chip, int port)
return chip->info->ops->port_set_sched(chip, port, (u16)sched);
}
+static int mv88e6xxx_set_port_egress_rate_limiting(struct mv88e6xxx_chip *chip,
+ int port)
+{
+ struct dsa_switch *ds = chip->ds;
+ struct device_node *dn = ds->ports[port].dn;
+ int err;
+ u32 mode, count;
+
+ if (!dn || !chip->info->ops->port_egress_rate_limiting)
+ return 0;
+
+ err = of_property_read_u32(dn, "egress-limit-mode", &mode);
+ if (err < 0)
+ goto disable;
+
+ err = of_property_read_u32(dn, "egress-limit-count", &count);
+ if (err < 0)
+ goto disable;
+
+ return chip->info->ops->port_egress_rate_limiting(chip, port, count,
+ mode);
+
+disable:
+ return chip->info->ops->port_egress_rate_limiting(chip, port, 0, 0);
+}
+
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
{
struct dsa_switch *ds = chip->ds;
@@ -2263,11 +2289,9 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
return err;
}
- if (chip->info->ops->port_egress_rate_limiting) {
- err = chip->info->ops->port_egress_rate_limiting(chip, port);
- if (err)
- return err;
- }
+ err = mv88e6xxx_set_port_egress_rate_limiting(chip, port);
+ if (err)
+ return err;
err = mv88e6xxx_setup_message_port(chip, port);
if (err)
@@ -2809,7 +2833,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -2879,7 +2903,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -2951,7 +2975,7 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_upstream_port = mv88e6095_port_set_upstream_port,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_set_pause = mv88e6185_port_set_pause,
.port_link_state = mv88e6352_port_link_state,
@@ -2994,7 +3018,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3034,7 +3058,7 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3108,7 +3132,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3150,7 +3174,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
.port_set_defqpri = mv88e6xxx_port_set_defqpri,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_set_sched = mv88e6xxx_port_set_sched,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
@@ -3193,7 +3217,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3235,7 +3259,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
.port_set_defqpri = mv88e6xxx_port_set_defqpri,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_set_sched = mv88e6xxx_port_set_sched,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
@@ -3275,7 +3299,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {
.port_set_speed = mv88e6185_port_set_speed,
.port_set_frame_mode = mv88e6085_port_set_frame_mode,
.port_set_egress_floods = mv88e6185_port_set_egress_floods,
- .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_set_upstream_port = mv88e6095_port_set_upstream_port,
.port_set_pause = mv88e6185_port_set_pause,
.port_link_state = mv88e6185_port_link_state,
@@ -3454,7 +3478,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
.port_set_defqpri = mv88e6xxx_port_set_defqpri,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_set_sched = mv88e6xxx_port_set_sched,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
@@ -3587,7 +3611,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3630,7 +3654,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3673,7 +3697,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3716,7 +3740,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3755,7 +3779,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3799,7 +3823,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
.port_set_defqpri = mv88e6xxx_port_set_defqpri,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_set_sched = mv88e6xxx_port_set_sched,
.port_pause_limit = mv88e6097_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
@@ -3851,7 +3875,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6390_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
@@ -3900,7 +3924,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type,
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
- .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting,
.port_pause_limit = mv88e6390_port_pause_limit,
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index ff3e35eceee0..75fbd5df4aae 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -385,7 +385,8 @@ struct mv88e6xxx_ops {
size_t size);
int (*port_set_defqpri)(struct mv88e6xxx_chip *chip, int port, u16 pri);
- int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
+ int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port,
+ u32 count, u32 mode);
int (*port_set_sched)(struct mv88e6xxx_chip *chip, int port, u16 sched);
int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
u8 out);
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 236732fc598d..41418cfaca56 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -1166,21 +1166,107 @@ int mv88e6xxx_port_set_defqpri(struct mv88e6xxx_chip *chip, int port, u16 pri)
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
}
-/* Offset 0x09: Port Rate Control */
+/* Offset 0x09: Port Rate Control
+ * Offset 0x0A: Egress Rate Control 2
+ */
-int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
+#define Kb 1000
+#define Mb (1000 * Kb)
+#define Gb (1000ull * Mb)
+#define EGRESS_FRAME_RATE_MIN 7632
+#define EGRESS_FRAME_RATE_MAX 31250000
+#define EGRESS_BPS_RATE_MIN (64 * Kb)
+#define EGRESS_BPS_RATE_MAX (1 * Gb)
+#define EGRESS_RATE_PERIOD 32
+int mv88e6xxx_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port,
+ u32 count, u32 mode)
{
- return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
- 0x0000);
-}
+ u16 reg1, reg2;
+ int err;
-int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
-{
- return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
- 0x0001);
+ /* quick exit for disabling */
+ if (count == 0) {
+ err = mv88e6xxx_port_read(chip, port,
+ MV88E6XXX_PORT_EGRESS_RATE_CTL2,
+ ®2);
+ if (err)
+ return err;
+ reg2 &= ~MV88E6XXX_PORT_EGRESS_RATE_MASK;
+ err = mv88e6xxx_port_write(chip, port,
+ MV88E6XXX_PORT_EGRESS_RATE_CTL2,
+ reg2);
+ return err;
+ }
+
+ if (mode > MV88E6XXX_PORT_EGRESS_COUNT_MODE_L3)
+ return -EINVAL;
+
+ if (mode == MV88E6XXX_PORT_EGRESS_COUNT_MODE_FRAMES &&
+ (count < EGRESS_FRAME_RATE_MIN || count > EGRESS_FRAME_RATE_MAX))
+ return -EINVAL;
+
+ if (mode != MV88E6XXX_PORT_EGRESS_COUNT_MODE_FRAMES &&
+ (count < EGRESS_BPS_RATE_MIN || count > EGRESS_BPS_RATE_MAX))
+ return -EINVAL;
+
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
+ ®1);
+ if (err)
+ return err;
+
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
+ ®2);
+ if (err)
+ return err;
+
+ reg1 &= ~MV88E6XXX_PORT_EGRESS_DEC_MASK;
+ reg2 &= ~MV88E6XXX_PORT_EGRESS_COUNT_MODE_MASK;
+
+ if (mode == MV88E6XXX_PORT_EGRESS_COUNT_MODE_FRAMES) {
+ u32 val;
+
+ /* recommended to use dec of 1 for frame based */
+ reg1 |= 1 << MV88E6XXX_PORT_EGRESS_DEC_SHIFT;
+
+ reg2 |= mode << MV88E6XXX_PORT_EGRESS_COUNT_MODE_SHIFT;
+ reg2 &= ~MV88E6XXX_PORT_EGRESS_RATE_MASK;
+
+ val = NSEC_PER_SEC / (EGRESS_RATE_PERIOD * count);
+ if (NSEC_PER_SEC % (EGRESS_RATE_PERIOD * count))
+ val++;
+ reg2 |= (u16)(val << MV88E6XXX_PORT_EGRESS_RATE_SHIFT);
+ } else {
+ u16 egress_dec, egress_rate;
+ u64 dec_bytes, ns_bits;
+
+ if (count < (1 * Mb))
+ egress_dec = (u16)roundup(count, (64 * Kb));
+ else if (count < (100 * Mb))
+ egress_dec = (u16)roundup(count, (1 * Mb));
+ else
+ egress_dec = (u16)roundup(count, (10 * Mb));
+
+ reg1 |= egress_dec;
+
+ dec_bytes = 8ull * NSEC_PER_SEC * egress_dec;
+ ns_bits = 32ull * count;
+ egress_rate = (u16)div64_u64(dec_bytes, ns_bits);
+ reg2 |= egress_rate;
+ }
+
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
+ reg1);
+ if (err)
+ return err;
+
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
+ reg2);
+ if (err)
+ return err;
+
+ return 0;
}
-/* Offset 0x0A: Egress Rate Control 2 */
int mv88e6xxx_port_set_sched(struct mv88e6xxx_chip *chip, int port, u16 sched)
{
u16 reg;
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 710d6eccafae..724f839c570a 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -205,13 +205,23 @@
/* Offset 0x09: Egress Rate Control */
#define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09
+#define MV88E6XXX_PORT_EGRESS_DEC_SHIFT 0
+#define MV88E6XXX_PORT_EGRESS_DEC_MASK 0x7f
/* Offset 0x0A: Egress Rate Control 2 */
#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a
+#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_SHIFT 14
+#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_MASK \
+ (0x3 << MV88E6XXX_PORT_EGRESS_COUNT_MODE_SHIFT)
+/* see MV88E6XXX_PORT_EGRESS_COUNT_* in
+ * include/dt-bindings/net/dsa-mv88e6xxx.h
+ */
#define MV88E6XXX_PORT_SCHED_SHIFT 12
#define MV88E6XXX_PORT_SCHED_MASK \
(0x3 << MV88E6XXX_PORT_SCHED_SHIFT)
/* see MV88E6XXX_PORT_SCHED_* in include/dt-bindings/net/dsa-mv88e6xxx.h */
+#define MV88E6XXX_PORT_EGRESS_RATE_SHIFT 0
+#define MV88E6XXX_PORT_EGRESS_RATE_MASK 0xfff
/* Offset 0x0B: Port Association Vector */
#define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b
@@ -335,8 +345,8 @@ int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
size_t size);
int mv88e6xxx_port_set_defqpri(struct mv88e6xxx_chip *chip, int port, u16 pri);
-int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
-int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
+int mv88e6xxx_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port,
+ u32 count, u32 mode);
int mv88e6xxx_port_set_sched(struct mv88e6xxx_chip *chip, int port, u16 sched);
int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
u8 out);
--
2.18.0
^ permalink raw reply related
* [PATCH 7/7] dt-bindings: mv88e6xxx: add egress rate limiting
From: Robert Beckett @ 2019-09-10 15:41 UTC (permalink / raw)
To: netdev
Cc: Robert Beckett, Andrew Lunn, Vivien Didelot, Florian Fainelli,
David S. Miller, Rob Herring, Mark Rutland, devicetree
In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com>
Document port egress rate limiting settings.
Add defines for specifying egress rate limiting mode.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
.../devicetree/bindings/net/dsa/marvell.txt | 22 +++++++++++++++++++
include/dt-bindings/net/dsa-mv88e6xxx.h | 5 +++++
2 files changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt
index 7de90929c3c9..d33c1958f420 100644
--- a/Documentation/devicetree/bindings/net/dsa/marvell.txt
+++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt
@@ -62,6 +62,28 @@ Optional properties for ports:
MV88E6XXX_PORT_SCHED_STRICT_ALL - All queues use
strict priority, where queues drain in descending
queue number order.
+- egress-limit-mode=<n> : Set port egress rate limiting mode. Valid values are:
+ MV88E6XXX_PORT_EGRESS_COUNT_MODE_FRAMES - Count layer
+ 2 frames (assumed to be 64kb).
+ MV88E6XXX_PORT_EGRESS_COUNT_MODE_L1 - Count all layer
+ 1 bits
+ MV88E6XXX_PORT_EGRESS_COUNT_MODE_L2 - Count all layer
+ 2 bits
+ MV88E6XXX_PORT_EGRESS_COUNT_MODE_L3 - Count all layer
+ 3 bits
+ Must also specify egress-limit-count.
+- egress-limit-count=<n>: Set port egress rate limiting count. If
+ egress-limit-mode is FRAMES, this specifies the
+ maximum number of ethernet frames to allow to egress
+ from this port per second, otherwise it is number of
+ bits as counted based on the mode allowed to egress
+ from this port per second.
+ The HW has limitations which the driver adheres to:
+ between 64 Kbps to 1 Mbps in 16 Kbps increments
+ between 1 Mbps to 100 Mbps in 1Mbps increments
+ between 100 Mbps to 1 Gbps in 10 Mbps increments.
+ Other values will be rounded down the previous
+ increment.
Example:
diff --git a/include/dt-bindings/net/dsa-mv88e6xxx.h b/include/dt-bindings/net/dsa-mv88e6xxx.h
index 3f62003841ce..33ecd94f5e22 100644
--- a/include/dt-bindings/net/dsa-mv88e6xxx.h
+++ b/include/dt-bindings/net/dsa-mv88e6xxx.h
@@ -9,6 +9,11 @@
#ifndef _DT_BINDINGS_MV88E6XXX_H
#define _DT_BINDINGS_MV88E6XXX_H
+#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_FRAMES 0
+#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_L1 1
+#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_L2 2
+#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_L3 3
+
#define MV88E6XXX_PORT_SCHED_ROUND_ROBIN 0
#define MV88E6XXX_PORT_SCHED_STRICT_3 1
#define MV88E6XXX_PORT_SCHED_STRICT_3_2 2
--
2.18.0
^ permalink raw reply related
* Re: [PATCH] net: stmmac: socfpga: re-use the `interface` parameter from platform data
From: David Miller @ 2019-09-10 15:45 UTC (permalink / raw)
To: alexandru.ardelean
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel,
peppe.cavallaro, alexandre.torgue, joabreu, mcoquelin.stm32
In-Reply-To: <20190906123054.5514-1-alexandru.ardelean@analog.com>
From: Alexandru Ardelean <alexandru.ardelean@analog.com>
Date: Fri, 6 Sep 2019 15:30:54 +0300
> The socfpga sub-driver defines an `interface` field in the `socfpga_dwmac`
> struct and parses it on init.
>
> The shared `stmmac_probe_config_dt()` function also parses this from the
> device-tree and makes it available on the returned `plat_data` (which is
> the same data available via `netdev_priv()`).
>
> All that's needed now is to dig that information out, via some
> `dev_get_drvdata()` && `netdev_priv()` calls and re-use it.
>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
This doesn't build even on net-next.
And if your patch does target net-next you must indicate this properly in the
Subject line as "[PATCH net-next]" vs. "[PATCH net]"
^ permalink raw reply
* Re: [PATCH] net: stmmac: socfpga: re-use the `interface` parameter from platform data
From: David Miller @ 2019-09-10 15:46 UTC (permalink / raw)
To: alexandru.ardelean
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel,
peppe.cavallaro, alexandre.torgue, joabreu, mcoquelin.stm32
In-Reply-To: <20190910.174544.945128884852877943.davem@davemloft.net>
From: David Miller <davem@davemloft.net>
Date: Tue, 10 Sep 2019 17:45:44 +0200 (CEST)
> From: Alexandru Ardelean <alexandru.ardelean@analog.com>
> Date: Fri, 6 Sep 2019 15:30:54 +0300
>
>> The socfpga sub-driver defines an `interface` field in the `socfpga_dwmac`
>> struct and parses it on init.
>>
>> The shared `stmmac_probe_config_dt()` function also parses this from the
>> device-tree and makes it available on the returned `plat_data` (which is
>> the same data available via `netdev_priv()`).
>>
>> All that's needed now is to dig that information out, via some
>> `dev_get_drvdata()` && `netdev_priv()` calls and re-use it.
>>
>> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
>
> This doesn't build even on net-next.
Specifically:
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c: In function ‘socfpga_gen5_set_phy_mode’:
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:264:44: error: ‘phymode’ undeclared (first use in this function); did you mean ‘phy_modes’?
264 | dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
| ^~~~~~~
./include/linux/device.h:1499:32: note: in definition of macro ‘dev_err’
1499 | _dev_err(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~~~~~
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:264:44: note: each undeclared identifier is reported only once for each function it appears in
264 | dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
| ^~~~~~~
./include/linux/device.h:1499:32: note: in definition of macro ‘dev_err’
1499 | _dev_err(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~~~~~
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c: In function ‘socfpga_gen10_set_phy_mode’:
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:340:6: error: ‘phymode’ undeclared (first use in this function); did you mean ‘phy_modes’?
340 | phymode == PHY_INTERFACE_MODE_MII ||
| ^~~~~~~
| phy_modes
^ permalink raw reply
* Re: [PATCH v3 2/2] PTP: add support for one-shot output
From: Richard Cochran @ 2019-09-10 15:47 UTC (permalink / raw)
To: Felipe Balbi; +Cc: Christopher S Hall, netdev, linux-kernel
In-Reply-To: <20190909075940.12843-2-felipe.balbi@linux.intel.com>
On Mon, Sep 09, 2019 at 10:59:40AM +0300, Felipe Balbi wrote:
> /*
> * Bits of the ptp_perout_request.flags field:
> */
> -#define PTP_PEROUT_VALID_FLAGS (~0)
> -
> +#define PTP_PEROUT_ONE_SHOT (1<<0)
> +#define PTP_PEROUT_VALID_FLAGS (~PTP_PEROUT_ONE_SHOT)
Here also, the bitwise not is backwards. ^
Thanks,
Richard
^ permalink raw reply
* Re: Is bug 200755 in anyone's queue??
From: Willem de Bruijn @ 2019-09-10 15:52 UTC (permalink / raw)
To: Willem de Bruijn
Cc: Steve Zabele, Eric Dumazet, Mark KEATON, Network Development,
shum@canndrew.org, vladimir116@gmail.com, saifi.khan@strikr.in,
Daniel Borkmann, on2k16nm@gmail.com, Stephen Hemminger,
Craig Gallek
In-Reply-To: <CA+FuTSf24VrjOxS9Kg3+DFEYn7ihe6vMj5o7rggOz_6KH_rNpQ@mail.gmail.com>
On Wed, Sep 4, 2019 at 11:46 AM Willem de Bruijn
<willemdebruijn.kernel@gmail.com> wrote:
>
> On Wed, Sep 4, 2019 at 10:51 AM Steve Zabele <zabele@comcast.net> wrote:
> >
> > I think a dual table approach makes a lot of sense here, especially if we look at the different use cases. For the DNS server example, almost certainly there will not be any connected sockets using the server port, so a test of whether the connected table is empty (maybe a boolean stored with the unconnected table?) should get to the existing code very quickly and not require accessing the memory holding the connected table. For our use case, the connected sockets persist for long periods (at network timescales at least) and so any rehashing should be infrequent and so have limited impact on performance overall.
> >
> > So does a dual table approach seem workable to other folks that know the internals?
>
> Let me take a stab and compare. A dual table does bring it more in
> line with how the TCP code is structured.
On closer look, I think two tables is too much code churn and risk for
a stable fix. It requires lookup changes across ipv4 and ipv6 unicast,
multicast, early demux, .. Though I'm happy to be proven wrong, of
course.
One variant that is easy to see only modifies behavior for reuseport
groups with connections is to mark those as such:
"
@@ -21,7 +21,8 @@ struct sock_reuseport {
unsigned int synq_overflow_ts;
/* ID stays the same even after the size of socks[] grows. */
unsigned int reuseport_id;
- bool bind_inany;
+ unsigned int bind_inany:1;
+ unsigned int has_conns:1;
struct bpf_prog __rcu *prog; /* optional BPF sock selector */
struct sock *socks[0]; /* array of sock pointers */
};
@@ -37,6 +38,23 @@ extern struct sock *reuseport_select_sock(struct sock *sk,
extern int reuseport_attach_prog(struct sock *sk, struct bpf_prog *prog);
extern int reuseport_detach_prog(struct sock *sk);
+static inline bool reuseport_has_conns(struct sock *sk, bool set)
+{
+ struct sock_reuseport *reuse;
+ bool ret = false;
+
+ rcu_read_lock();
+ reuse = rcu_dereference(sk->sk_reuseport_cb);
+ if (reuse) {
+ if (set)
+ reuse->has_conns = 1;
+ ret = reuse->has_conns;
+ }
+ rcu_read_unlock();
+
+ return ret;
+}
@@ -67,6 +68,7 @@ int __ip4_datagram_connect(struct sock *sk, struct
sockaddr *uaddr, int addr_len
if (sk->sk_prot->rehash)
sk->sk_prot->rehash(sk);
}
+ reuseport_has_conns(sk, true);
inet->inet_daddr = fl4->daddr;
inet->inet_dport = usin->sin_port;
sk->sk_state = TCP_ESTABLISHED;
"
Then at lookup treat connected reuseport sockets are regular sockets
and do not return early on a reuseport match if there may be higher
scoring connections:
"
@@ -423,13 +423,15 @@ static struct sock *udp4_lib_lookup2(struct net *net,
score = compute_score(sk, net, saddr, sport,
daddr, hnum, dif, sdif);
if (score > badness) {
- if (sk->sk_reuseport) {
+ if (sk->sk_reuseport &&
+ sk->sk_state != TCP_ESTABLISHED) {
hash = udp_ehashfn(net, daddr, hnum,
saddr, sport);
result = reuseport_select_sock(sk, hash, skb,
sizeof(struct udphdr));
- if (result)
+ if (result && !reuseport_has_conns(sk, false))
return result;
+ sk = result ? : sk;
}
badness = score;
result = sk;
"
and finally for reuseport matches only return unconnected sockets in the group:
"
@@ -295,8 +295,19 @@ struct sock *reuseport_select_sock(struct sock *sk,
select_by_hash:
/* no bpf or invalid bpf result: fall back to hash usage */
- if (!sk2)
- sk2 = reuse->socks[reciprocal_scale(hash, socks)];
+ if (!sk2) {
+ int i, j;
+
+ i = j = reciprocal_scale(hash, socks);
+ while (reuse->socks[i]->sk_state == TCP_ESTABLISHED) {
+ i++;
+ if (i == reuse->num_socks)
+ i = 0;
+ if (i == j)
+ goto out;
+ }
+ sk2 = reuse->socks[i];
+ }
}
"
This is hardly a short patch, but the behavioral change is contained.
I also coded up the alternative to rely on order in the list: entries
are listed at the head and the list is traversed at the head. To keep
all connections within a group ahead of all the unconnected sockets in
a group (1) rehash on connect and (2) do a more complex
insert-after-connected-reuseport for new reuseport sockets:
"
@@ -67,12 +68,16 @@ int __ip4_datagram_connect(struct sock *sk, struct
sockaddr *uaddr, int addr_len
if (sk->sk_prot->rehash)
sk->sk_prot->rehash(sk);
}
+
inet->inet_daddr = fl4->daddr;
inet->inet_dport = usin->sin_port;
sk->sk_state = TCP_ESTABLISHED;
sk_set_txhash(sk);
inet->inet_id = jiffies;
+ if (rcu_access_pointer(sk->sk_reuseport_cb) && sk->sk_prot->rehash)
+ sk->sk_prot->rehash(sk);
+
sk_dst_set(sk, &rt->dst);
err = 0;
@@ -323,7 +323,21 @@ int udp_lib_get_port(struct sock *sk, unsigned short snum,
sk->sk_family == AF_INET6)
hlist_add_tail_rcu(&udp_sk(sk)->udp_portaddr_node,
&hslot2->head);
- else
+ else if (sk->sk_reuseport) {
+ struct sock *cur, *last_conn = NULL;
+
+ udp_portaddr_for_each_entry_rcu(cur, &hslot2->head) {
+ if (cur->sk_state == TCP_ESTABLISHED &&
+ rcu_access_pointer(cur->sk_reuseport_cb))
+ last_conn = cur;
+ }
+ if (last_conn)
+
hlist_add_behind_rcu(&udp_sk(sk)->udp_portaddr_node,
+
&udp_sk(last_conn)->udp_portaddr_node);
+ else
+
hlist_add_head_rcu(&udp_sk(sk)->udp_portaddr_node,
+ &hslot2->head);
+ } else
hlist_add_head_rcu(&udp_sk(sk)->udp_portaddr_node,
&hslot2->head);
@@ -423,7 +437,8 @@ static struct sock *udp4_lib_lookup2(struct net *net,
score = compute_score(sk, net, saddr, sport,
daddr, hnum, dif, sdif);
if (score > badness) {
- if (sk->sk_reuseport) {
+ if (sk->sk_reuseport &&
+ sk->sk_state != TCP_ESTABLISHED) {
hash = udp_ehashfn(net, daddr, hnum,
saddr, sport);
result = reuseport_select_sock(sk, hash, skb,
@@ -1891,10 +1906,12 @@ void udp_lib_rehash(struct sock *sk, u16 newhash)
udp_sk(sk)->udp_port_hash);
/* we must lock primary chain too */
spin_lock_bh(&hslot->lock);
+#if 0
/* TODO: differentiate inet_rcv_saddr change
from regular connect */
if (rcu_access_pointer(sk->sk_reuseport_cb))
reuseport_detach_sock(sk);
+#endif
- if (hslot2 != nhslot2) {
+ if (1) {
spin_lock(&hslot2->lock);
hlist_del_init_rcu(&udp_sk(sk)->udp_portaddr_node);
hslot2->count--;
"
This clearly has some loose ends and is no shorter or simpler. So
unless anyone has comments or a different solution, I'll finish
up the first variant.
^ permalink raw reply
* Re: [PATCH net-next 0/3] net: dsa: mv88e6xxx: add PCL support
From: David Miller @ 2019-09-10 15:53 UTC (permalink / raw)
To: vivien.didelot; +Cc: netdev, f.fainelli, andrew
In-Reply-To: <20190907200049.25273-1-vivien.didelot@gmail.com>
From: Vivien Didelot <vivien.didelot@gmail.com>
Date: Sat, 7 Sep 2019 16:00:46 -0400
> This small series implements the ethtool RXNFC operations in the
> mv88e6xxx DSA driver to configure a port's Layer 2 Policy Control List
> (PCL) supported by models such as 88E6352 and 88E6390 and equivalent.
>
> This allows to configure a port to discard frames based on a configured
> destination or source MAC address and an optional VLAN, with e.g.:
>
> # ethtool --config-nfc lan1 flow-type ether src 00:11:22:33:44:55 action -1
Series applied, thanks.
^ permalink raw reply
* Re: [PATCH 1/7] net/dsa: configure autoneg for CPU port
From: Vivien Didelot @ 2019-09-10 16:14 UTC (permalink / raw)
To: Robert Beckett
Cc: netdev, Robert Beckett, Andrew Lunn, Florian Fainelli,
David S. Miller
In-Reply-To: <20190910154238.9155-2-bob.beckett@collabora.com>
Hi Robert,
On Tue, 10 Sep 2019 16:41:47 +0100, Robert Beckett <bob.beckett@collabora.com> wrote:
> Configure autoneg for phy connected CPU ports.
> This allows us to use autoneg between the CPU port's phy and the link
> partner's phy.
> This enables us to negoatiate pause frame transmission to prioritise
> packet delivery over throughput.
>
> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
> ---
> net/dsa/port.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/net/dsa/port.c b/net/dsa/port.c
> index f071acf2842b..1b6832eac2c5 100644
> --- a/net/dsa/port.c
> +++ b/net/dsa/port.c
> @@ -538,10 +538,20 @@ static int dsa_port_setup_phy_of(struct dsa_port *dp, bool enable)
> return PTR_ERR(phydev);
>
> if (enable) {
> + phydev->supported = PHY_GBIT_FEATURES | SUPPORTED_MII |
> + SUPPORTED_AUI | SUPPORTED_FIBRE |
> + SUPPORTED_BNC | SUPPORTED_Pause |
> + SUPPORTED_Asym_Pause;
> + phydev->advertising = phydev->supported;
> +
This seems a bit intruisive to me. I'll get back to you.
> err = genphy_config_init(phydev);
> if (err < 0)
> goto err_put_dev;
>
> + err = genphy_config_aneg(phydev);
> + if (err < 0)
> + goto err_put_dev;
> +
> err = genphy_resume(phydev);
> if (err < 0)
> goto err_put_dev;
^ permalink raw reply
* Re: [PATCH net-next v2 00/11] nfp: implement firmware loading policy
From: David Miller @ 2019-09-10 16:30 UTC (permalink / raw)
To: simon.horman; +Cc: jakub.kicinski, netdev, oss-drivers, dirk.vandermerwe
In-Reply-To: <20190908235427.9757-1-simon.horman@netronome.com>
From: Simon Horman <simon.horman@netronome.com>
Date: Mon, 9 Sep 2019 00:54:16 +0100
> Dirk says:
>
> This series adds configuration capabilities to the firmware loading policy of
> the NFP driver.
>
> NFP firmware loading is controlled via three HWinfo keys which can be set per
> device: 'abi_drv_reset', 'abi_drv_load_ifc' and 'app_fw_from_flash'.
> Refer to patch #11 for more detail on how these control the firmware loading.
>
> In order to configure the full extend of FW loading policy, a new devlink
> parameter has been introduced, 'reset_dev_on_drv_probe', which controls if the
> driver should reset the device when it's probed. This, in conjunction with the
> existing 'fw_load_policy' (extended to include a 'disk' option) provides the
> means to tweak the NFP HWinfo keys as required by users.
>
> Patches 1 and 2 adds the devlink modifications and patches 3 through 9 adds the
> support into the NFP driver. Furthermore, the last 2 patches are documentation
> only.
>
> v2:
> Renamed all 'reset_dev_on_drv_probe' defines the same as the devlink parameter
> name (Jiri)
Series applied, thanks Simon.
^ permalink raw reply
* [net-next 01/14] ixgbe: fix memory leaks
From: Jeff Kirsher @ 2019-09-10 16:34 UTC (permalink / raw)
To: davem; +Cc: Wenwen Wang, netdev, nhorman, sassmann, Andrew Bowers,
Jeff Kirsher
In-Reply-To: <20190910163434.2449-1-jeffrey.t.kirsher@intel.com>
From: Wenwen Wang <wenwen@cs.uga.edu>
In ixgbe_configure_clsu32(), 'jump', 'input', and 'mask' are allocated
through kzalloc() respectively in a for loop body. Then,
ixgbe_clsu32_build_input() is invoked to build the input. If this process
fails, next iteration of the for loop will be executed. However, the
allocated 'jump', 'input', and 'mask' are not deallocated on this execution
path, leading to memory leaks.
Signed-off-by: Wenwen Wang <wenwen@cs.uga.edu>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 99df595abfba..95c0827dfd4c 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -9490,6 +9490,10 @@ static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
jump->mat = nexthdr[i].jump;
adapter->jump_tables[link_uhtid] = jump;
break;
+ } else {
+ kfree(mask);
+ kfree(input);
+ kfree(jump);
}
}
return 0;
--
2.21.0
^ permalink raw reply related
* [net-next 03/14] ixgbe: use skb_get_queue_mapping in tx path
From: Jeff Kirsher @ 2019-09-10 16:34 UTC (permalink / raw)
To: davem; +Cc: Tonghao Zhang, netdev, nhorman, sassmann, Andrew Bowers,
Jeff Kirsher
In-Reply-To: <20190910163434.2449-1-jeffrey.t.kirsher@intel.com>
From: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Use the common api, and don't access queue_mapping directly.
Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 95c0827dfd4c..dc034f4e8cf6 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -8748,7 +8748,7 @@ static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
if (skb_put_padto(skb, 17))
return NETDEV_TX_OK;
- tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
+ tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)];
if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state)))
return NETDEV_TX_BUSY;
--
2.21.0
^ permalink raw reply related
* [net-next 05/14] i40e: remove I40E_AQC_ADD_CLOUD_FILTER_OIP
From: Jeff Kirsher @ 2019-09-10 16:34 UTC (permalink / raw)
To: davem; +Cc: Jacob Keller, netdev, nhorman, sassmann, Andrew Bowers,
Jeff Kirsher
In-Reply-To: <20190910163434.2449-1-jeffrey.t.kirsher@intel.com>
From: Jacob Keller <jacob.e.keller@intel.com>
The bit 0x0001 used in the cloud filters adminq command is reserved, and
is not actually a valid type.
The Linux driver has never used this type, and it's not clear if any
driver ever has.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
index 21cccec328e3..7ff768761659 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
@@ -1382,7 +1382,7 @@ struct i40e_aqc_cloud_filters_element_data {
#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
/* 0x0000 reserved */
-#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
+/* 0x0001 reserved */
/* 0x0002 reserved */
#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
--
2.21.0
^ permalink raw reply related
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