* Re: [PATCH net-next v3 0/2] net/smc: send and write inline optimization for smc
From: Karsten Graul @ 2022-05-16 16:58 UTC (permalink / raw)
To: Guangguan Wang, davem, edumazet, kuba, pabeni, leon, tonylu
Cc: linux-s390, netdev, linux-kernel
In-Reply-To: <20220516055137.51873-1-guangguan.wang@linux.alibaba.com>
On 16/05/2022 07:51, Guangguan Wang wrote:
> Send cdc msgs and write data inline if qp has sufficent inline
> space, helps latency reducing.
>
> In my test environment, which are 2 VMs running on the same
> physical host and whose NICs(ConnectX-4Lx) are working on
> SR-IOV mode, qperf shows 0.4us-1.3us improvement in latency.
>
> Test command:
> server: smc_run taskset -c 1 qperf
> client: smc_run taskset -c 1 qperf <server ip> -oo \
> msg_size:1:2K:*2 -t 30 -vu tcp_lat
>
> The results shown below:
> msgsize before after
> 1B 11.9 us 10.6 us (-1.3 us)
> 2B 11.7 us 10.7 us (-1.0 us)
> 4B 11.7 us 10.7 us (-1.0 us)
> 8B 11.6 us 10.6 us (-1.0 us)
> 16B 11.7 us 10.7 us (-1.0 us)
> 32B 11.7 us 10.6 us (-1.1 us)
> 64B 11.7 us 11.2 us (-0.5 us)
> 128B 11.6 us 11.2 us (-0.4 us)
> 256B 11.8 us 11.2 us (-0.6 us)
> 512B 11.8 us 11.3 us (-0.5 us)
> 1KB 11.9 us 11.5 us (-0.4 us)
> 2KB 12.1 us 11.5 us (-0.6 us)
>
> Guangguan Wang (2):
> net/smc: send cdc msg inline if qp has sufficient inline space
> net/smc: rdma write inline if qp has sufficient inline space
>
> net/smc/smc_ib.c | 1 +
> net/smc/smc_tx.c | 17 ++++++++++++-----
> net/smc/smc_wr.c | 5 ++++-
> 3 files changed, 17 insertions(+), 6 deletions(-)
>
I like that change, thank you!
For the series:
Acked-by: Karsten Graul <kgraul@linux.ibm.com>
^ permalink raw reply
* Re: [RFC PATCH 2/3] dt-bindings: can: ctucanfd: add properties for HW timestamping
From: Marc Kleine-Budde @ 2022-05-16 16:34 UTC (permalink / raw)
To: Rob Herring
Cc: Matej Vasilevski, linux-can, pisa, devicetree, netdev,
ondrej.ille, martin.jerabek01
In-Reply-To: <20220516160250.GA2724701-robh@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 3685 bytes --]
On 16.05.2022 11:02:50, Rob Herring wrote:
> On Fri, May 13, 2022 at 01:27:06AM +0200, Matej Vasilevski wrote:
> > Extend dt-bindings for CTU CAN-FD IP core with necessary properties
> > to enable HW timestamping for platform devices. Since the timestamping
> > counter is provided by the system integrator usign those IP cores in
> > their FPGA design, we need to have the properties specified in device tree.
> >
> > Signed-off-by: Matej Vasilevski <matej.vasilevski@seznam.cz>
> > ---
> > .../bindings/net/can/ctu,ctucanfd.yaml | 34 +++++++++++++++++--
> > 1 file changed, 31 insertions(+), 3 deletions(-)
>
> What's the base for this patch? Doesn't apply for me.
>
> >
> > diff --git a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml
> > index fb34d971dcb3..c3693dadbcd8 100644
> > --- a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml
> > +++ b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml
> > @@ -41,9 +41,35 @@ properties:
> >
> > clocks:
> > description: |
> > - phandle of reference clock (100 MHz is appropriate
> > - for FPGA implementation on Zynq-7000 system).
> > + Phandle of reference clock (100 MHz is appropriate for FPGA
> > + implementation on Zynq-7000 system). If you wish to use timestamps
> > + from the core, add a second phandle with the clock used for timestamping
> > + (can be the same as the first clock).
> > + maxItems: 2
>
> With more than 1, you have to define what each entry is. IOW, use
> 'items'.
>
> > +
> > + clock-names:
> > + description: |
> > + Specify clock names for the "clocks" property. The first clock name
> > + doesn't matter, the second has to be "ts_clk". Timestamping frequency
> > + is then obtained from the "ts_clk" clock. This takes precedence over
> > + the ts-frequency property.
> > + You can omit this property if you don't need timestamps.
> > + maxItems: 2
>
> You must define what the names are as a schema.
>
> > +
> > + ts-used-bits:
> > + description: width of the timestamping counter
> > + maxItems: 1
> > + items:
>
> Not an array, so you don't need maxItems nor items.
>
> > + minimum: 8
> > + maximum: 64
> > +
> > + ts-frequency:
>
> Use a standard unit suffix.
>
> > + description: |
> > + Frequency of the timestamping counter. Set this if you want to get
> > + timestamps, but you didn't set the timestamping clock in clocks property.
> > maxItems: 1
> > + items:
>
> Not an array.
>
>
> Is timestamping a common feature for CAN or is this specific to this
> controller? In the latter case, you need vendor prefixes on these
> properties. In the former case, you need to define them in a common
> schema.
This property describes the usable with of the free running timer and
the timestamps generated by it. This is similar to the free running
timer and time stamps as found on PTP capable Ethernet NICs. But the
ctucanfd comes in a hardware description language that can be
parametrized and synthesized into your own FPGA.
To answer your question, timestamping is common in newer CAN cores, but
the width of the timestamping register is usually fixed and thus hard
coded in the driver.
regards,
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung West/Dortmund | Phone: +49-231-2826-924 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH 21/30] panic: Introduce the panic pre-reboot notifier list
From: Guilherme G. Piccoli @ 2022-05-16 16:33 UTC (permalink / raw)
To: Luck, Tony, Petr Mladek, Dinh Nguyen
Cc: akpm@linux-foundation.org, bhe@redhat.com,
kexec@lists.infradead.org, linux-kernel@vger.kernel.org,
bcm-kernel-feedback-list@broadcom.com,
linuxppc-dev@lists.ozlabs.org, linux-alpha@vger.kernel.org,
linux-edac@vger.kernel.org, linux-hyperv@vger.kernel.org,
linux-leds@vger.kernel.org, linux-mips@vger.kernel.org,
linux-parisc@vger.kernel.org, linux-pm@vger.kernel.org,
linux-remoteproc@vger.kernel.org, linux-s390@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-um@lists.infradead.org,
linux-xtensa@linux-xtensa.org, netdev@vger.kernel.org,
openipmi-developer@lists.sourceforge.net, rcu@vger.kernel.org,
sparclinux@vger.kernel.org, xen-devel@lists.xenproject.org,
x86@kernel.org, kernel-dev@igalia.com, kernel@gpiccoli.net,
halves@canonical.com, fabiomirmar@gmail.com,
alejandro.j.jimenez@oracle.com, andriy.shevchenko@linux.intel.com,
arnd@arndb.de, bp@alien8.de, corbet@lwn.net,
d.hatayama@jp.fujitsu.com, dave.hansen@linux.intel.com,
dyoung@redhat.com, Tang, Feng, gregkh@linuxfoundation.org,
mikelley@microsoft.com, hidehiro.kawai.ez@hitachi.com,
jgross@suse.com, john.ogness@linutronix.de, keescook@chromium.org,
luto@kernel.org, mhiramat@kernel.org, mingo@redhat.com,
paulmck@kernel.org, peterz@infradead.org, rostedt@goodmis.org,
senozhatsky@chromium.org, stern@rowland.harvard.edu,
tglx@linutronix.de, vgoyal@redhat.com, vkuznets@redhat.com,
will@kernel.org, Alex Elder, Alexander Gordeev, Anton Ivanov,
Benjamin Herrenschmidt, Bjorn Andersson, Boris Ostrovsky,
Chris Zankel, Christian Borntraeger, Corey Minyard, Dexuan Cui,
H. Peter Anvin, Haiyang Zhang, Heiko Carstens, Helge Deller,
Ivan Kokshaysky, James E.J. Bottomley, James Morse, Johannes Berg,
K. Y. Srinivasan, Mathieu Poirier, Matt Turner,
Mauro Carvalho Chehab, Max Filippov, Michael Ellerman,
Paul Mackerras, Pavel Machek, Richard Weinberger, Robert Richter,
Stefano Stabellini, Stephen Hemminger, Sven Schnelle,
Vasily Gorbik, Wei Liu
In-Reply-To: <bed66b9467254a5a8bafc1983dad643a@intel.com>
On 16/05/2022 13:18, Luck, Tony wrote:
>> [...]
> Would it be possible to have some global "kdump is configured + enabled" flag?
>
> Then notifiers could make an informed choice on whether to deep dive to
> get all the possible details (when there is no kdump) or just skim the high
> level stuff (to maximize chance of getting a successful kdump).
>
> -Tony
Good idea Tony! What if I wire a kexec_crash_loaded() in the notifier?
With that, are you/Petr/Dinh OK in moving it for the info list?
Cheers,
Guilherme
^ permalink raw reply
* Re: [PATCH 24/30] panic: Refactor the panic path
From: Guilherme G. Piccoli @ 2022-05-16 16:32 UTC (permalink / raw)
To: Petr Mladek
Cc: michael Kelley (LINUX), Baoquan He, Dave Young, d.hatayama, akpm,
kexec, linux-kernel, bcm-kernel-feedback-list, linuxppc-dev,
linux-alpha, linux-arm-kernel, linux-edac, linux-hyperv,
linux-leds, linux-mips, linux-parisc, linux-pm, linux-remoteproc,
linux-s390, linux-tegra, linux-um, linux-xtensa, netdev,
openipmi-developer, rcu, sparclinux, xen-devel, x86, kernel-dev,
kernel, halves, fabiomirmar, alejandro.j.jimenez,
andriy.shevchenko, arnd, bp, corbet, dave.hansen, feng.tang,
gregkh, hidehiro.kawai.ez, jgross, john.ogness, keescook, luto,
mhiramat, mingo, paulmck, peterz, rostedt, senozhatsky, stern,
tglx, vgoyal, vkuznets, will, Marc Zyngier, Mark Rutland,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <YoIlvFxbqoiDsD1l@alley>
On 16/05/2022 07:21, Petr Mladek wrote:
> [...]
> Ah, it should have been:
>
> + notifiers vs. kmsg_dump
> + notifiers vs. crash_dump
> + crash_dump vs. kmsg_dump
>
> I am sorry for the confusion. Even "crash_dump" is slightly
> misleading because there is no function with this name.
> But it seems to be easier to understand than __crash_kexec().
Cool, thanks! Now it's totally clear for me =)
I feel crash dump is the proper term, but I personally prefer kdump to
avoid mess-up with user space "core dump" concept heheh
Also, KDUMP is an entry on MAINTAINERS file.
> [...]
>> Heheh OK, I appreciate your opinion, but I guess we'll need to agree in
>> disagree here - I'm much more fond to this kind of code than a bunch of
>> if/else blocks that almost give headaches. Encoding such "level" logic
>> in the if/else scheme is very convoluted, generates a very big code. And
>> the functions aren't so black magic - they map a level in bits, and the
>> functions _once() are called...once! Although we switch the position in
>> the code, so there are 2 calls, one of them is called and the other not.
>
> I see. Well, I would consider this as a warning that the approach is
> too complex. If the code, using if/then/else, would cause headaches
> then also understanding of the behavior would cause headaches for
> both users and programmers.
>
>
>> But that's totally fine to change - especially if we're moving away from
>> the "level" logic. I see below you propose a much simpler approach - if
>> we follow that, definitely we won't need the "black magic" approach heheh
>
> I do not say that my proposal is fully correct. But we really need
> this kind of simpler approach.
It's cool, I agree that your idea is much simpler and makes sense - mine
seems to be an over-engineering effort. Let's see the opinions of the
interested parties, I'm curious to see if everybody agrees here, that'd
would be ideal (and kind of "wishful thinking" I guess heheh - panic
path is polemic).
> [...]
>> Here we have a very important point. Why do we need 2 variants of SMP
>> CPU stopping functions? I disagree with that - my understanding of this
>> after some study in architectures is that the crash_() variant is
>> "stronger", should work in all cases and if not, we should fix that -
>> that'd be a bug.
>>
>> Such variant either maps to smp_send_stop() (in various architectures,
>> including XEN/x86) or overrides the basic function with more proper
>> handling for panic() case...I don't see why we still need such
>> distinction, if you / others have some insight about that, I'd like to
>> hear =)
>
> The two variants were introduced by the commit 0ee59413c967c35a6dd
> ("x86/panic: replace smp_send_stop() with kdump friendly version in
> panic path")
>
> It points to https://lkml.org/lkml/2015/6/24/44 that talks about
> still running watchdogs.
>
> It is possible that the problem could be fixed another way. It is
> even possible that it has already been fixed by the notifiers
> that disable the watchdogs.
>
> Anyway, any change of the smp_send_stop() behavior should be done
> in a separate patch. It will help with bisection of possible
> regression. Also it would require a good explanation in
> the commit message. I would personally do it in a separate
> patch(set).
Thanks for the archeology and interesting findings. I agree that is
better to split in smaller patches. I'm planning a split in 3 patches
for V2: clean-up (comment, console flushing idea, useless header), the
refactor itself and finally, this SMP change.
> [...]
>> You had the order of panic_reboot_list VS. consoles flushing inverted.
>> It might make sense, although I didn't do that in V1...
>
> IMHO, it makes sense:
>
> 1. panic_reboot_list contains notifiers that do the reboot
> immediately, for example, xen_panic_event, alpha_panic_event.
> The consoles have to be flushed earlier.
>
> 2. console_flush_on_panic() ignores the result of console_trylock()
> and always calls console_unlock(). As a result the lock should
> be unlocked at the end. And any further printk() should be able
> to printk the messages to the console immediately. It means
> that any messages printed by the reboot notifiers should appear
> on the console as well.
> [...]
>> OK, I agree with you! It's indeed simpler and if others agree, I can
>> happily change the logic to what you proposed. Although...currently the
>> "crash_kexec_post_notifiers" allows to call _all_ panic_reboot_list
>> callbacks _before kdump_.
>>
>> We need to mention this change in the commit messages, but I really
>> would like to hear the opinions of heavy users of notifiers (as
>> Michael/Hyper-V) and the kdump interested parties (like Baoquan / Dave
>> Young / Hayatama). If we all agree on such approach, will change that
>> for V2 =)
>
> Sure, we need to make sure that we call everything that is needed.
> And it should be documented.
>
> I believe that this is the right way because:
>
> + It was actually the motivation for this patchset. We split
> the notifiers into separate lists because we want to call
> only the really needed ones before kmsg_dump and crash_dump.
>
> + If anything is needed for crash_dump that it should be called
> even when crash_dump is called first. It should be either
> hardcoded into crash_dump() or we would need another notifier
> list that will be always called before crash_dump.
Ack, makes sense! Will do that in V2 =)
For the "hardcoded" part, we have the custom machine_crash_kexec() in
some archs (like x86), unfortunately not in all of them - this path is
ideally for mandatory code that is required for a successful crash_kexec().
The problem is the "same old, same old" - architecture folks push that
to panic notifiers; notifiers folks push it to the arch custom shutdown
handler (see [0] heheh).
(CCed Marc / Mark in case they want to chime-in here...)
>[...]
> Thanks a lot for working on this.
>
> Best Regards,
> Petr
You're welcome, _thank you_ for the great and detailed reviews!
Cheers,
Guilherme
[0]
https://lore.kernel.org/lkml/427a8277-49f0-4317-d6c3-4a15d7070e55@igalia.com/
^ permalink raw reply
* RE: [PATCH 21/30] panic: Introduce the panic pre-reboot notifier list
From: Luck, Tony @ 2022-05-16 16:18 UTC (permalink / raw)
To: Guilherme G. Piccoli, Petr Mladek, Dinh Nguyen
Cc: akpm@linux-foundation.org, bhe@redhat.com,
kexec@lists.infradead.org, linux-kernel@vger.kernel.org,
bcm-kernel-feedback-list@broadcom.com,
linuxppc-dev@lists.ozlabs.org, linux-alpha@vger.kernel.org,
linux-edac@vger.kernel.org, linux-hyperv@vger.kernel.org,
linux-leds@vger.kernel.org, linux-mips@vger.kernel.org,
linux-parisc@vger.kernel.org, linux-pm@vger.kernel.org,
linux-remoteproc@vger.kernel.org, linux-s390@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-um@lists.infradead.org,
linux-xtensa@linux-xtensa.org, netdev@vger.kernel.org,
openipmi-developer@lists.sourceforge.net, rcu@vger.kernel.org,
sparclinux@vger.kernel.org, xen-devel@lists.xenproject.org,
x86@kernel.org, kernel-dev@igalia.com, kernel@gpiccoli.net,
halves@canonical.com, fabiomirmar@gmail.com,
alejandro.j.jimenez@oracle.com, andriy.shevchenko@linux.intel.com,
arnd@arndb.de, bp@alien8.de, corbet@lwn.net,
d.hatayama@jp.fujitsu.com, dave.hansen@linux.intel.com,
dyoung@redhat.com, Tang, Feng, gregkh@linuxfoundation.org,
mikelley@microsoft.com, hidehiro.kawai.ez@hitachi.com,
jgross@suse.com, john.ogness@linutronix.de, keescook@chromium.org,
luto@kernel.org, mhiramat@kernel.org, mingo@redhat.com,
paulmck@kernel.org, peterz@infradead.org, rostedt@goodmis.org,
senozhatsky@chromium.org, stern@rowland.harvard.edu,
tglx@linutronix.de, vgoyal@redhat.com, vkuznets@redhat.com,
will@kernel.org, Alex Elder, Alexander Gordeev, Anton Ivanov,
Benjamin Herrenschmidt, Bjorn Andersson, Boris Ostrovsky,
Chris Zankel, Christian Borntraeger, Corey Minyard, Dexuan Cui,
H. Peter Anvin, Haiyang Zhang, Heiko Carstens, Helge Deller,
Ivan Kokshaysky, James E.J. Bottomley, James Morse, Johannes Berg,
K. Y. Srinivasan, Mathieu Poirier, Matt Turner,
Mauro Carvalho Chehab, Max Filippov, Michael Ellerman,
Paul Mackerras, Pavel Machek, Richard Weinberger, Robert Richter,
Stefano Stabellini, Stephen Hemminger, Sven Schnelle,
Vasily Gorbik, Wei Liu
In-Reply-To: <63a74b56-89ef-8d1f-d487-cdb986aab798@igalia.com>
> So, my reasoning here is: this notifier should fit the info list,
> definitely! But...it's very high risk for kdump. It deep dives into the
> regmap API (there are locks in such code) plus there is an (MM)IO write
> to the device and an ARM firmware call. So, despite the nature of this
> notifier _fits the informational list_, the _code is risky_ so we should
> avoid running it before a kdump.
>
> Now, we indeed have a chicken/egg problem: want to avoid it before
> kdump, BUT in case kdump is not set, kmsg_dump() (and console flushing,
> after your suggestion Petr) will run before it and not save collected
> information from EDAC PoV.
Would it be possible to have some global "kdump is configured + enabled" flag?
Then notifiers could make an informed choice on whether to deep dive to
get all the possible details (when there is no kdump) or just skim the high
level stuff (to maximize chance of getting a successful kdump).
-Tony
^ permalink raw reply
* Re: [PATCH 18/30] notifier: Show function names on notifier routines if DEBUG_NOTIFIERS is set
From: Guilherme G. Piccoli @ 2022-05-16 16:14 UTC (permalink / raw)
To: Steven Rostedt, Xiaoming Ni
Cc: akpm, bhe, pmladek, kexec, linux-kernel, bcm-kernel-feedback-list,
coresight, linuxppc-dev, linux-alpha, linux-arm-kernel,
linux-edac, linux-hyperv, linux-leds, linux-mips, linux-parisc,
linux-pm, linux-remoteproc, linux-s390, linux-tegra, linux-um,
linux-xtensa, netdev, openipmi-developer, rcu, sparclinux,
xen-devel, x86, kernel-dev, kernel, halves, fabiomirmar,
alejandro.j.jimenez, andriy.shevchenko, arnd, bp, corbet,
d.hatayama, dave.hansen, dyoung, feng.tang, gregkh, mikelley,
hidehiro.kawai.ez, jgross, john.ogness, keescook, luto, mhiramat,
mingo, paulmck, peterz, senozhatsky, stern, tglx, vgoyal,
vkuznets, will, Arjan van de Ven, Cong Wang,
Sebastian Andrzej Siewior, Valentin Schneider
In-Reply-To: <20220510132922.61883db0@gandalf.local.home>
On 10/05/2022 14:29, Steven Rostedt wrote:
> [...]
> Also, don't sprinkle #ifdef in C code. Instead:
>
> if (IS_ENABLED(CONFIG_DEBUG_NOTIFIERS))
> pr_info("notifers: regsiter %ps()\n",
> n->notifer_call);
>
>
> Or define a print macro at the start of the C file that is a nop if it is
> not defined, and use the macro.
Thanks, I'll go with the IS_ENABLED() idea in V2 - appreciate the hint.
Cheers,
Guilherme
^ permalink raw reply
* Re: [PATCH 25/30] panic, printk: Add console flush parameter and convert panic_print to a notifier
From: Guilherme G. Piccoli @ 2022-05-16 16:11 UTC (permalink / raw)
To: Petr Mladek
Cc: akpm, bhe, kexec, linux-kernel, bcm-kernel-feedback-list,
linuxppc-dev, linux-alpha, linux-edac, linux-hyperv, linux-leds,
linux-mips, linux-parisc, linux-pm, linux-remoteproc, linux-s390,
linux-tegra, linux-um, linux-xtensa, netdev, openipmi-developer,
rcu, sparclinux, xen-devel, x86, kernel-dev, kernel, halves,
fabiomirmar, alejandro.j.jimenez, andriy.shevchenko, arnd, bp,
corbet, d.hatayama, dave.hansen, dyoung, feng.tang, gregkh,
mikelley, hidehiro.kawai.ez, jgross, john.ogness, keescook, luto,
mhiramat, mingo, paulmck, peterz, rostedt, senozhatsky, stern,
tglx, vgoyal, vkuznets, will
In-Reply-To: <YoJmKYLzPZqCDDim@alley>
On 16/05/2022 11:56, Petr Mladek wrote:
> [...]
> I really like both changes. Just please split it them into two
> patchset. I mean one patch for the new "panic_console_replay"
> parameter and 2nd that moves "printk_info" into the notifier.
>
OK sure, will do that in V2.
Thanks,
Guilherme
^ permalink raw reply
* Re: [PATCH 19/30] panic: Add the panic hypervisor notifier list
From: Evan Green @ 2022-05-16 16:02 UTC (permalink / raw)
To: Guilherme G. Piccoli
Cc: Petr Mladek, David Gow, Julius Werner, Scott Branden,
bcm-kernel-feedback-list, Sebastian Reichel, Linux PM,
Florian Fainelli, Andrew Morton, bhe, kexec, LKML, linuxppc-dev,
linux-alpha, linux-arm Mailing List, linux-edac, linux-hyperv,
linux-leds, linux-mips, linux-parisc, linux-remoteproc,
linux-s390, linux-tegra, linux-um, linux-xtensa, netdev,
openipmi-developer, rcu, sparclinux, xen-devel, x86, kernel-dev,
kernel, halves, fabiomirmar, alejandro.j.jimenez, Andy Shevchenko,
Arnd Bergmann, Borislav Petkov, Jonathan Corbet, d.hatayama,
dave.hansen, dyoung, feng.tang, Greg Kroah-Hartman, mikelley,
hidehiro.kawai.ez, jgross, john.ogness, Kees Cook, luto, mhiramat,
mingo, paulmck, peterz, rostedt, senozhatsky, Alan Stern,
Thomas Gleixner, vgoyal, vkuznets, Will Deacon, Alexander Gordeev,
Andrea Parri, Ard Biesheuvel, Benjamin Herrenschmidt,
Brian Norris, Christian Borntraeger, Christophe JAILLET,
David S. Miller, Dexuan Cui, Doug Berger, Haiyang Zhang,
Hari Bathini, Heiko Carstens, Justin Chen, K. Y. Srinivasan,
Lee Jones, Markus Mayer, Michael Ellerman, Mihai Carabas,
Nicholas Piggin, Paul Mackerras, Pavel Machek, Shile Zhang,
Stephen Hemminger, Sven Schnelle, Thomas Bogendoerfer, Tianyu Lan,
Vasily Gorbik, Wang ShaoBo, Wei Liu, zhenwei pi, Stephen Boyd
In-Reply-To: <ad082ce7-db50-13bb-3dbb-9b595dfa78be@igalia.com>
On Mon, May 16, 2022 at 8:07 AM Guilherme G. Piccoli
<gpiccoli@igalia.com> wrote:
>
> Thanks for the review!
>
> I agree with the blinking stuff, I can rework and add all LED/blinking
> stuff into the loop list, it does make sense. I'll comment a bit in the
> others below...
>
> On 16/05/2022 11:01, Petr Mladek wrote:
> > [...]
> >> --- a/arch/mips/sgi-ip22/ip22-reset.c
> >> +++ b/arch/mips/sgi-ip22/ip22-reset.c
> >> @@ -195,7 +195,7 @@ static int __init reboot_setup(void)
> >> }
> >>
> >> timer_setup(&blink_timer, blink_timeout, 0);
> >> - atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
> >> + atomic_notifier_chain_register(&panic_hypervisor_list, &panic_block);
> >
> > This notifier enables blinking. It is not much safe. It calls
> > mod_timer() that takes a lock internally.
> >
> > This kind of functionality should go into the last list called
> > before panic() enters the infinite loop. IMHO, all the blinking
> > stuff should go there.
> > [...]
> >> --- a/arch/mips/sgi-ip32/ip32-reset.c
> >> +++ b/arch/mips/sgi-ip32/ip32-reset.c
> >> @@ -145,7 +144,7 @@ static __init int ip32_reboot_setup(void)
> >> pm_power_off = ip32_machine_halt;
> >>
> >> timer_setup(&blink_timer, blink_timeout, 0);
> >> - atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
> >> + atomic_notifier_chain_register(&panic_hypervisor_list, &panic_block);
> >
> > Same here. Should be done only before the "loop".
> > [...]
>
> Ack.
>
>
> >> --- a/drivers/firmware/google/gsmi.c
> >> +++ b/drivers/firmware/google/gsmi.c
> >> @@ -1034,7 +1034,7 @@ static __init int gsmi_init(void)
> >>
> >> register_reboot_notifier(&gsmi_reboot_notifier);
> >> register_die_notifier(&gsmi_die_notifier);
> >> - atomic_notifier_chain_register(&panic_notifier_list,
> >> + atomic_notifier_chain_register(&panic_hypervisor_list,
> >> &gsmi_panic_notifier);
> >
> > I am not sure about this one. It looks like some logging or
> > pre_reboot stuff.
> >
>
> Disagree here. I'm looping Google maintainers, so they can comment.
> (CCed Evan, David, Julius)
>
> This notifier is clearly a hypervisor notification mechanism. I've fixed
> a locking stuff there (in previous patch), I feel it's low-risk but even
> if it's mid-risk, the class of such callback remains a perfect fit with
> the hypervisor list IMHO.
This logs a panic to our "eventlog", a tiny logging area in SPI flash
for critical and power-related events. In some cases this ends up
being the only clue we get in a Chromebook feedback report that a
panic occurred, so from my perspective moving it to the front of the
line seems like a good idea.
-Evan
^ permalink raw reply
* Re: [PATCH 23/30] printk: kmsg_dump: Introduce helper to inform number of dumpers
From: Guilherme G. Piccoli @ 2022-05-16 16:09 UTC (permalink / raw)
To: Petr Mladek
Cc: Steven Rostedt, akpm, bhe, kexec, linux-kernel,
bcm-kernel-feedback-list, linuxppc-dev, linux-alpha, linux-edac,
linux-hyperv, linux-leds, linux-mips, linux-parisc, linux-pm,
linux-remoteproc, linux-s390, linux-tegra, linux-um, linux-xtensa,
netdev, openipmi-developer, rcu, sparclinux, xen-devel, x86,
kernel-dev, kernel, halves, fabiomirmar, alejandro.j.jimenez,
andriy.shevchenko, arnd, bp, corbet, d.hatayama, dave.hansen,
dyoung, feng.tang, gregkh, mikelley, hidehiro.kawai.ez, jgross,
john.ogness, keescook, luto, mhiramat, mingo, paulmck, peterz,
senozhatsky, stern, tglx, vgoyal, vkuznets, will
In-Reply-To: <YoJkpAp8XdS7ROgd@alley>
On 16/05/2022 11:50, Petr Mladek wrote:
> [...]
> Shame on me that I do not care that much about the style of the commit
> message :-)
>
> Anyway, the code looks good to me. With the better commit message:
>
> Reviewed-by: Petr Mladek <pmladek@suse.com>
>
Heheh, cool - I'll add your tag and improve the message in V2.
Thanks,
Guilherme
^ permalink raw reply
* Re: [PATCH 22/30] panic: Introduce the panic post-reboot notifier list
From: Guilherme G. Piccoli @ 2022-05-16 16:08 UTC (permalink / raw)
To: Petr Mladek
Cc: akpm, bhe, kexec, linux-kernel, bcm-kernel-feedback-list,
linuxppc-dev, linux-alpha, linux-edac, linux-hyperv, linux-leds,
linux-mips, linux-parisc, linux-pm, linux-remoteproc, linux-s390,
linux-tegra, linux-um, linux-xtensa, netdev, openipmi-developer,
rcu, sparclinux, xen-devel, x86, kernel-dev, kernel, halves,
fabiomirmar, alejandro.j.jimenez, andriy.shevchenko, arnd, bp,
corbet, d.hatayama, dave.hansen, dyoung, feng.tang, gregkh,
mikelley, hidehiro.kawai.ez, jgross, john.ogness, keescook, luto,
mhiramat, mingo, paulmck, peterz, rostedt, senozhatsky, stern,
tglx, vgoyal, vkuznets, will, Alexander Gordeev,
Christian Borntraeger, David S. Miller, Heiko Carstens,
Sven Schnelle, Vasily Gorbik
In-Reply-To: <YoJjpBrz34QO+rn9@alley>
On 16/05/2022 11:45, Petr Mladek wrote:
> [...]
>
> The patch looks good to me. I would just suggest two changes.
>
> 1. I would rename the list to "panic_loop_list" instead of
> "panic_post_reboot_list".
>
> It will be more clear that it includes things that are
> needed before panic() enters the infinite loop.
>
>
> 2. I would move all the notifiers that enable blinking here.
>
> The blinking should be done only during the infinite
> loop when there is nothing else to do. If we enable
> earlier then it might disturb/break more important
> functionality (dumping information, reboot).
>
Perfect, I agree with you. I'll change both points in V2 =)
^ permalink raw reply
* [PATCH v2 net-next 15/15] net: ethernet: mtk_eth_soc: introduce support for mt7986 chipset
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
Add support for mt7986-eth driver available on mt7986 soc.
Tested-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 29 ++++++++++++++++++++-
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 18 +++++++++++++
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 373d9733e66f..ce3c242f14fa 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -45,6 +45,17 @@ static const u32 mtk_reg_map[] = {
[MTK_PDMA_RSS_GLO_BASE] = 0x3000,
};
+static const u32 mt7986_reg_map[] = {
+ [MTK_PDMA_BASE] = 0x6000,
+ [MTK_PDMA_LRO_CTRL] = 0x6408,
+ [MTK_PDMA_ALT_SCORE_DELTA_BASE] = 0x641c,
+ [MTK_PDMA_LRO_RX_RING_DIP_BASE] = 0x6414,
+ [MTK_PDMA_LRO_RX_RING_CTRL_BASE] = 0x6438,
+ [MTK_QDMA_BASE] = 0x4400,
+ [MTK_GDM1_TX_STAT_BASE] = 0x1c00,
+ [MTK_PDMA_RSS_GLO_BASE] = 0x6800,
+};
+
/* strings used by ethtool */
static const struct mtk_ethtool_stats {
char str[ETH_GSTRING_LEN];
@@ -68,7 +79,7 @@ static const char * const mtk_clks_source_name[] = {
"ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
"sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
"sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
- "sgmii_ck", "eth2pll",
+ "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
};
void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
@@ -3625,6 +3636,21 @@ static const struct mtk_soc_data mt7629_data = {
},
};
+static const struct mtk_soc_data mt7986_data = {
+ .reg_map = mt7986_reg_map,
+ .ana_rgc3 = 0x128,
+ .caps = MT7986_CAPS,
+ .required_clks = MT7986_CLKS_BITMAP,
+ .required_pctl = false,
+ .txrx = {
+ .txd_size = sizeof(struct mtk_tx_dma_v2),
+ .rxd_size = sizeof(struct mtk_rx_dma_v2),
+ .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+ .dma_len_offset = 8,
+ },
+};
+
static const struct mtk_soc_data rt5350_data = {
.reg_map = mtk_reg_map,
.caps = MT7628_CAPS,
@@ -3647,6 +3673,7 @@ const struct of_device_id of_mtk_match[] = {
{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
+ { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
{},
};
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index d955af42ad93..1972bc18af0c 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -763,6 +763,10 @@ enum mtk_clks_map {
MTK_CLK_SGMII2_CDR_FB,
MTK_CLK_SGMII_CK,
MTK_CLK_ETH2PLL,
+ MTK_CLK_WOCPU0,
+ MTK_CLK_WOCPU1,
+ MTK_CLK_NETSYS0,
+ MTK_CLK_NETSYS1,
MTK_CLK_MAX
};
@@ -793,6 +797,16 @@ enum mtk_clks_map {
BIT(MTK_CLK_SGMII2_CDR_FB) | \
BIT(MTK_CLK_SGMII_CK) | \
BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
+#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
+ BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
+ BIT(MTK_CLK_SGMII_TX_250M) | \
+ BIT(MTK_CLK_SGMII_RX_250M) | \
+ BIT(MTK_CLK_SGMII_CDR_REF) | \
+ BIT(MTK_CLK_SGMII_CDR_FB) | \
+ BIT(MTK_CLK_SGMII2_TX_250M) | \
+ BIT(MTK_CLK_SGMII2_RX_250M) | \
+ BIT(MTK_CLK_SGMII2_CDR_REF) | \
+ BIT(MTK_CLK_SGMII2_CDR_FB))
enum mtk_dev_state {
MTK_HW_INIT,
@@ -991,6 +1005,10 @@ enum mkt_eth_capabilities {
MTK_MUX_U3_GMAC2_TO_QPHY | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
+#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
+ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+ MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
+
struct mtk_tx_dma_desc_info {
dma_addr_t addr;
u32 size;
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 14/15] net: ethernet: mtk_eth_soc: convert scratch_ring pointer to void
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
Simplify the code converting scratch_ring pointer to void
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 4190172ba902..373d9733e66f 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -827,7 +827,7 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
for (i = 0; i < cnt; i++) {
struct mtk_tx_dma_v2 *txd;
- txd = (void *)eth->scratch_ring + i * soc->txrx.txd_size;
+ txd = eth->scratch_ring + i * soc->txrx.txd_size;
txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
if (i < cnt - 1)
txd->txd2 = eth->phy_scratch_ring +
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 57501dd5adcc..d955af42ad93 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1131,7 +1131,7 @@ struct mtk_eth {
struct mtk_rx_ring rx_ring_qdma;
struct napi_struct tx_napi;
struct napi_struct rx_napi;
- struct mtk_tx_dma *scratch_ring;
+ void *scratch_ring;
dma_addr_t phy_scratch_ring;
void *scratch_head;
struct clk *clks[MTK_CLK_MAX];
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 13/15] net: ethernet: mtk_eth_soc: convert ring dma pointer to void
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
Simplify the code converting {tx,rx} ring dma pointer to void
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 32 +++++++++------------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 +--
2 files changed, 16 insertions(+), 20 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 50ffdcb8d35a..4190172ba902 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -851,18 +851,15 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
return 0;
}
-static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
+static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
{
- void *ret = ring->dma;
-
- return ret + (desc - ring->phys);
+ return ring->dma + (desc - ring->phys);
}
static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
- struct mtk_tx_dma *txd,
- u32 txd_size)
+ void *txd, u32 txd_size)
{
- int idx = ((void *)txd - (void *)ring->dma) / txd_size;
+ int idx = (txd - ring->dma) / txd_size;
return &ring->buf[idx];
}
@@ -870,13 +867,12 @@ static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
struct mtk_tx_dma *dma)
{
- return ring->dma_pdma - ring->dma + dma;
+ return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma;
}
-static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma,
- u32 txd_size)
+static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size)
{
- return ((void *)dma - (void *)ring->dma) / txd_size;
+ return (dma - ring->dma) / txd_size;
}
static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
@@ -1293,7 +1289,7 @@ static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
ring = ð->rx_ring[i];
idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
- rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size;
+ rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
if (rxd->rxd2 & RX_DMA_DONE) {
ring->calc_idx_update = true;
return ring;
@@ -1345,7 +1341,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
goto rx_done;
idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
- rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size;
+ rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
data = ring->data[idx];
if (!mtk_rx_get_desc(eth, &trxd, rxd))
@@ -1548,7 +1544,7 @@ static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
mtk_tx_unmap(eth, tx_buf, true);
- desc = (void *)ring->dma + cpu * eth->soc->txrx.txd_size;
+ desc = ring->dma + cpu * eth->soc->txrx.txd_size;
ring->last_free = desc;
atomic_inc(&ring->free_count);
@@ -1692,7 +1688,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
int next = (i + 1) % MTK_DMA_SIZE;
u32 next_ptr = ring->phys + next * soc->txrx.txd_size;
- txd = (void *)ring->dma + i * soc->txrx.txd_size;
+ txd = ring->dma + i * soc->txrx.txd_size;
txd->txd2 = next_ptr;
txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
txd->txd4 = 0;
@@ -1723,7 +1719,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
ring->dma_size = MTK_DMA_SIZE;
atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
- ring->next_free = &ring->dma[0];
+ ring->next_free = ring->dma;
ring->last_free = (void *)txd;
ring->last_free_ptr = (u32)(ring->phys +
(MTK_DMA_SIZE - 1) * soc->txrx.txd_size);
@@ -1835,7 +1831,7 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
return -ENOMEM;
- rxd = (void *)ring->dma + i * eth->soc->txrx.rxd_size;
+ rxd = ring->dma + i * eth->soc->txrx.rxd_size;
rxd->rxd1 = (unsigned int)dma_addr;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
@@ -1889,7 +1885,7 @@ static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
if (!ring->data[i])
continue;
- rxd = (void *)ring->dma + i * eth->soc->txrx.rxd_size;
+ rxd = ring->dma + i * eth->soc->txrx.rxd_size;
if (!rxd->rxd1)
continue;
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 654ad3b00154..57501dd5adcc 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -828,7 +828,7 @@ struct mtk_tx_buf {
* are present
*/
struct mtk_tx_ring {
- struct mtk_tx_dma *dma;
+ void *dma;
struct mtk_tx_buf *buf;
dma_addr_t phys;
struct mtk_tx_dma *next_free;
@@ -858,7 +858,7 @@ enum mtk_rx_flags {
* @calc_idx: The current head of ring
*/
struct mtk_rx_ring {
- struct mtk_rx_dma *dma;
+ void *dma;
u8 **data;
dma_addr_t phys;
u16 frag_size;
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 12/15] net: ethernet: mtk_eth_soc: introduce MTK_NETSYS_V2 support
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
Introduce MTK_NETSYS_V2 support. MTK_NETSYS_V2 defines 32B TX/RX DMA
descriptors.
This is a preliminary patch to add mt7986 ethernet support.
Tested-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 312 ++++++++++++++++----
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 129 +++++++-
2 files changed, 366 insertions(+), 75 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 4dfd43023d80..50ffdcb8d35a 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -778,8 +778,8 @@ static inline int mtk_max_buf_size(int frag_size)
return buf_size;
}
-static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd,
- struct mtk_rx_dma *dma_rxd)
+static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd,
+ struct mtk_rx_dma_v2 *dma_rxd)
{
rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
if (!(rxd->rxd2 & RX_DMA_DONE))
@@ -788,6 +788,10 @@ static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd,
rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
+ rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
+ rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
+ }
return true;
}
@@ -821,7 +825,7 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
for (i = 0; i < cnt; i++) {
- struct mtk_tx_dma *txd;
+ struct mtk_tx_dma_v2 *txd;
txd = (void *)eth->scratch_ring + i * soc->txrx.txd_size;
txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
@@ -831,6 +835,12 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
txd->txd4 = 0;
+ if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
+ txd->txd5 = 0;
+ txd->txd6 = 0;
+ txd->txd7 = 0;
+ txd->txd8 = 0;
+ }
}
mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
@@ -934,10 +944,12 @@ static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
}
}
-static void mtk_tx_set_dma_desc(struct net_device *dev, struct mtk_tx_dma *desc,
- struct mtk_tx_dma_desc_info *info)
+static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd,
+ struct mtk_tx_dma_desc_info *info)
{
struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ struct mtk_tx_dma *desc = txd;
u32 data;
WRITE_ONCE(desc->txd1, info->addr);
@@ -961,6 +973,59 @@ static void mtk_tx_set_dma_desc(struct net_device *dev, struct mtk_tx_dma *desc,
WRITE_ONCE(desc->txd4, data);
}
+static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd,
+ struct mtk_tx_dma_desc_info *info)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_tx_dma_v2 *desc = txd;
+ struct mtk_eth *eth = mac->hw;
+ u32 data;
+
+ WRITE_ONCE(desc->txd1, info->addr);
+
+ data = TX_DMA_PLEN0(info->size);
+ if (info->last)
+ data |= TX_DMA_LS0;
+ WRITE_ONCE(desc->txd3, data);
+
+ if (!info->qid && mac->id)
+ info->qid = MTK_QDMA_GMAC2_QID;
+
+ data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
+ data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
+ WRITE_ONCE(desc->txd4, data);
+
+ data = 0;
+ if (info->first) {
+ if (info->gso)
+ data |= TX_DMA_TSO_V2;
+ /* tx checksum offload */
+ if (info->csum)
+ data |= TX_DMA_CHKSUM_V2;
+ }
+ WRITE_ONCE(desc->txd5, data);
+
+ data = 0;
+ if (info->first && info->vlan)
+ data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci;
+ WRITE_ONCE(desc->txd6, data);
+
+ WRITE_ONCE(desc->txd7, 0);
+ WRITE_ONCE(desc->txd8, 0);
+}
+
+static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd,
+ struct mtk_tx_dma_desc_info *info)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
+ mtk_tx_set_dma_desc_v2(dev, txd, info);
+ else
+ mtk_tx_set_dma_desc_v1(dev, txd, info);
+}
+
static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
int tx_num, struct mtk_tx_ring *ring, bool gso)
{
@@ -969,6 +1034,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
.gso = gso,
.csum = skb->ip_summed == CHECKSUM_PARTIAL,
.vlan = skb_vlan_tag_present(skb),
+ .qid = skb->mark & MTK_QDMA_TX_MASK,
.vlan_tci = skb_vlan_tag_get(skb),
.first = true,
.last = !skb_is_nonlinear(skb),
@@ -1028,7 +1094,9 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
}
memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
- txd_info.size = min(frag_size, MTK_TX_DMA_BUF_LEN);
+ txd_info.size = min_t(unsigned int, frag_size,
+ soc->txrx.dma_max_len);
+ txd_info.qid = skb->mark & MTK_QDMA_TX_MASK;
txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
!(frag_size - txd_info.size);
txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
@@ -1109,17 +1177,16 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
return -ENOMEM;
}
-static inline int mtk_cal_txd_req(struct sk_buff *skb)
+static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb)
{
- int i, nfrags;
+ int i, nfrags = 1;
skb_frag_t *frag;
- nfrags = 1;
if (skb_is_gso(skb)) {
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
frag = &skb_shinfo(skb)->frags[i];
nfrags += DIV_ROUND_UP(skb_frag_size(frag),
- MTK_TX_DMA_BUF_LEN);
+ eth->soc->txrx.dma_max_len);
}
} else {
nfrags += skb_shinfo(skb)->nr_frags;
@@ -1171,7 +1238,7 @@ static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
if (unlikely(test_bit(MTK_RESETTING, ð->state)))
goto drop;
- tx_num = mtk_cal_txd_req(skb);
+ tx_num = mtk_cal_txd_req(eth, skb);
if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
netif_stop_queue(dev);
netif_err(eth, tx_queued, dev,
@@ -1263,7 +1330,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
int idx;
struct sk_buff *skb;
u8 *data, *new_data;
- struct mtk_rx_dma *rxd, trxd;
+ struct mtk_rx_dma_v2 *rxd, trxd;
int done = 0, bytes = 0;
while (done < budget) {
@@ -1271,7 +1338,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
unsigned int pktlen;
dma_addr_t dma_addr;
u32 hash, reason;
- int mac;
+ int mac = 0;
ring = mtk_get_rx_ring(eth);
if (unlikely(!ring))
@@ -1281,16 +1348,15 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size;
data = ring->data[idx];
- if (!mtk_rx_get_desc(&trxd, rxd))
+ if (!mtk_rx_get_desc(eth, &trxd, rxd))
break;
/* find out which mac the packet come from. values start at 1 */
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) ||
- (trxd.rxd4 & RX_DMA_SPECIAL_TAG))
- mac = 0;
- else
- mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
- RX_DMA_FPORT_MASK) - 1;
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
+ mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
+ else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
+ !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
+ mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
!eth->netdev[mac]))
@@ -1333,7 +1399,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
skb->dev = netdev;
skb_put(skb, pktlen);
- if (trxd.rxd4 & eth->rx_dma_l4_valid)
+ if (trxd.rxd4 & eth->soc->txrx.rx_dma_l4_valid)
skb->ip_summed = CHECKSUM_UNNECESSARY;
else
skb_checksum_none_assert(skb);
@@ -1351,10 +1417,25 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
mtk_ppe_check_skb(eth->ppe, skb,
trxd.rxd4 & MTK_RXD4_FOE_ENTRY);
- if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
- (trxd.rxd2 & RX_DMA_VTAG))
- __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
- RX_DMA_VID(trxd.rxd3));
+ if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
+ if (trxd.rxd3 & RX_DMA_VTAG_V2)
+ __vlan_hwaccel_put_tag(skb,
+ htons(RX_DMA_VPID(trxd.rxd4)),
+ RX_DMA_VID(trxd.rxd4));
+ } else if (trxd.rxd2 & RX_DMA_VTAG) {
+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
+ RX_DMA_VID(trxd.rxd3));
+ }
+
+ /* If the device is attached to a dsa switch, the special
+ * tag inserted in VLAN field by hw switch can * be offloaded
+ * by RX HW VLAN offload. Clear vlan info.
+ */
+ if (netdev_uses_dsa(netdev))
+ __vlan_hwaccel_clear_tag(skb);
+ }
+
skb_record_rx_queue(skb, 0);
napi_gro_receive(napi, skb);
@@ -1366,7 +1447,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
rxd->rxd2 = RX_DMA_LSO;
else
- rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
+ rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
ring->calc_idx = idx;
@@ -1565,7 +1646,8 @@ static int mtk_napi_rx(struct napi_struct *napi, int budget)
do {
int rx_done;
- mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
+ mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
+ MTK_PDMA_INT_STATUS);
rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
rx_done_total += rx_done;
@@ -1579,10 +1661,11 @@ static int mtk_napi_rx(struct napi_struct *napi, int budget)
if (rx_done_total == budget)
return budget;
- } while (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT);
+ } while (mtk_r32(eth, MTK_PDMA_INT_STATUS) &
+ eth->soc->txrx.rx_irq_done_mask);
if (napi_complete_done(napi, rx_done_total))
- mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
+ mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
return rx_done_total;
}
@@ -1591,7 +1674,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
{
const struct mtk_soc_data *soc = eth->soc;
struct mtk_tx_ring *ring = ð->tx_ring;
- struct mtk_tx_dma *txd;
+ struct mtk_tx_dma_v2 *txd;
int i;
ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
@@ -1613,13 +1696,19 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
txd->txd2 = next_ptr;
txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
txd->txd4 = 0;
+ if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
+ txd->txd5 = 0;
+ txd->txd6 = 0;
+ txd->txd7 = 0;
+ txd->txd8 = 0;
+ }
}
/* On MT7688 (PDMA only) this driver uses the ring->dma structs
* only as the framework. The real HW descriptors are the PDMA
* descriptors in ring->dma_pdma.
*/
- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
+ if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
ring->dma_pdma = dma_alloc_coherent(eth->dma_dev,
MTK_DMA_SIZE * soc->txrx.txd_size,
&ring->phys_pdma, GFP_ATOMIC);
@@ -1700,13 +1789,11 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
struct mtk_rx_ring *ring;
int rx_data_len, rx_dma_size;
int i;
- u32 offset = 0;
if (rx_flag == MTK_RX_FLAGS_QDMA) {
if (ring_no)
return -EINVAL;
ring = ð->rx_ring_qdma;
- offset = 0x1000;
} else {
ring = ð->rx_ring[ring_no];
}
@@ -1739,7 +1826,7 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
return -ENOMEM;
for (i = 0; i < rx_dma_size; i++) {
- struct mtk_rx_dma *rxd;
+ struct mtk_rx_dma_v2 *rxd;
dma_addr_t dma_addr = dma_map_single(eth->dma_dev,
ring->data[i] + NET_SKB_PAD + eth->ip_align,
@@ -1754,24 +1841,39 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
rxd->rxd2 = RX_DMA_LSO;
else
- rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
+ rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
rxd->rxd3 = 0;
rxd->rxd4 = 0;
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
+ rxd->rxd5 = 0;
+ rxd->rxd6 = 0;
+ rxd->rxd7 = 0;
+ rxd->rxd8 = 0;
+ }
}
ring->dma_size = rx_dma_size;
ring->calc_idx_update = false;
ring->calc_idx = rx_dma_size - 1;
- ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
+ if (rx_flag == MTK_RX_FLAGS_QDMA)
+ ring->crx_idx_reg = MTK_QRX_CRX_IDX_CFG(ring_no);
+ else
+ ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
/* make sure that all changes to the dma ring are flushed before we
* continue
*/
wmb();
- mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
- mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
- mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
- mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
+ if (rx_flag == MTK_RX_FLAGS_QDMA) {
+ mtk_w32(eth, ring->phys, MTK_QRX_BASE_PTR_CFG(ring_no));
+ mtk_w32(eth, rx_dma_size, MTK_QRX_MAX_CNT_CFG(ring_no));
+ mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_QDMA_RST_IDX);
+ } else {
+ mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no));
+ mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no));
+ mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX);
+ }
+ mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
return 0;
}
@@ -2190,7 +2292,7 @@ static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
eth->rx_events++;
if (likely(napi_schedule_prep(ð->rx_napi))) {
__napi_schedule(ð->rx_napi);
- mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
+ mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
}
return IRQ_HANDLED;
@@ -2213,8 +2315,10 @@ static irqreturn_t mtk_handle_irq(int irq, void *_eth)
{
struct mtk_eth *eth = _eth;
- if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) {
- if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT)
+ if (mtk_r32(eth, MTK_PDMA_INT_MASK) &
+ eth->soc->txrx.rx_irq_done_mask) {
+ if (mtk_r32(eth, MTK_PDMA_INT_STATUS) &
+ eth->soc->txrx.rx_irq_done_mask)
mtk_handle_irq_rx(irq, _eth);
}
if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) {
@@ -2232,16 +2336,16 @@ static void mtk_poll_controller(struct net_device *dev)
struct mtk_eth *eth = mac->hw;
mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
- mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
+ mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
mtk_handle_irq_rx(eth->irq[2], dev);
mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
- mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
+ mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
}
#endif
static int mtk_start_dma(struct mtk_eth *eth)
{
- u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
+ u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
int err;
err = mtk_dma_init(eth);
@@ -2251,12 +2355,18 @@ static int mtk_start_dma(struct mtk_eth *eth)
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
- mtk_w32(eth,
- MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
- MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
- MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
- MTK_RX_BT_32DWORDS,
- MTK_QDMA_GLO_CFG);
+ val = mtk_r32(eth, MTK_QDMA_GLO_CFG);
+ val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN |
+ MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
+ MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
+
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
+ val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
+ MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
+ MTK_CHK_DDONE_EN;
+ else
+ val |= MTK_RX_BT_32DWORDS;
+ mtk_w32(eth, val, MTK_QDMA_GLO_CFG);
mtk_w32(eth,
MTK_RX_DMA_EN | rx_2b_offset |
@@ -2328,7 +2438,7 @@ static int mtk_open(struct net_device *dev)
napi_enable(ð->tx_napi);
napi_enable(ð->rx_napi);
mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
- mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
+ mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
refcount_set(ð->dma_refcnt, 1);
}
else
@@ -2380,7 +2490,7 @@ static int mtk_stop(struct net_device *dev)
mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
- mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
+ mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
napi_disable(ð->tx_napi);
napi_disable(ð->rx_napi);
@@ -2517,7 +2627,7 @@ static int mtk_hw_init(struct mtk_eth *eth)
if (eth->ethsys)
regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
- of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask);
+ of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask);
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
ret = device_reset(eth->dev);
@@ -2537,9 +2647,25 @@ static int mtk_hw_init(struct mtk_eth *eth)
return 0;
}
- /* Non-MT7628 handling... */
- ethsys_reset(eth, RSTCTRL_FE);
- ethsys_reset(eth, RSTCTRL_PPE);
+ val = RSTCTRL_FE | RSTCTRL_PPE;
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
+ regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
+
+ val |= RSTCTRL_ETH;
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+ val |= RSTCTRL_PPE1;
+ }
+
+ ethsys_reset(eth, val);
+
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
+ regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
+ 0x3ffffff);
+
+ /* Set FE to PDMAv2 if necessary */
+ val = mtk_r32(eth, MTK_FE_GLO_MISC);
+ mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
+ }
if (eth->pctl) {
/* Set GE2 driving and slew rate */
@@ -2578,11 +2704,47 @@ static int mtk_hw_init(struct mtk_eth *eth)
/* FE int grouping */
mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
- mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
+ mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, MTK_PDMA_INT_GRP2);
mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
- mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
+ mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, MTK_QDMA_INT_GRP2);
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
+ /* PSE should not drop port8 and port9 packets */
+ mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
+
+ /* PSE Free Queue Flow Control */
+ mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
+
+ /* PSE config input queue threshold */
+ mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1));
+ mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2));
+ mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3));
+ mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4));
+ mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5));
+ mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6));
+ mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7));
+ mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8));
+
+ /* PSE config output queue threshold */
+ mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1));
+ mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2));
+ mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3));
+ mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4));
+ mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5));
+ mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6));
+ mtk_w32(eth, 0x00060006, PSE_OQ_TH(7));
+ mtk_w32(eth, 0x00060006, PSE_OQ_TH(8));
+
+ /* GDM and CDM Threshold */
+ mtk_w32(eth, 0x00000004, MTK_GDM2_THRES);
+ mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES);
+ mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES);
+ mtk_w32(eth, 0x00000004, MTK_CDME0_THRES);
+ mtk_w32(eth, 0x00000004, MTK_CDME1_THRES);
+ mtk_w32(eth, 0x00000004, MTK_CDMM_THRES);
+ }
+
return 0;
err_disable_pm:
@@ -3154,12 +3316,8 @@ static int mtk_probe(struct platform_device *pdev)
eth->tx_int_status_reg = MTK_PDMA_INT_STATUS;
}
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
- eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA;
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
eth->ip_align = NET_IP_ALIGN;
- } else {
- eth->rx_dma_l4_valid = RX_DMA_L4_VALID;
- }
spin_lock_init(ð->page_lock);
spin_lock_init(ð->tx_irq_lock);
@@ -3395,6 +3553,10 @@ static const struct mtk_soc_data mt2701_data = {
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
+ .rx_irq_done_mask = MTK_RX_DONE_INT,
+ .rx_dma_l4_valid = RX_DMA_L4_VALID,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
},
};
@@ -3408,6 +3570,10 @@ static const struct mtk_soc_data mt7621_data = {
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
+ .rx_irq_done_mask = MTK_RX_DONE_INT,
+ .rx_dma_l4_valid = RX_DMA_L4_VALID,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
},
};
@@ -3422,6 +3588,10 @@ static const struct mtk_soc_data mt7622_data = {
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
+ .rx_irq_done_mask = MTK_RX_DONE_INT,
+ .rx_dma_l4_valid = RX_DMA_L4_VALID,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
},
};
@@ -3435,6 +3605,10 @@ static const struct mtk_soc_data mt7623_data = {
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
+ .rx_irq_done_mask = MTK_RX_DONE_INT,
+ .rx_dma_l4_valid = RX_DMA_L4_VALID,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
},
};
@@ -3448,6 +3622,10 @@ static const struct mtk_soc_data mt7629_data = {
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
+ .rx_irq_done_mask = MTK_RX_DONE_INT,
+ .rx_dma_l4_valid = RX_DMA_L4_VALID,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
},
};
@@ -3460,6 +3638,10 @@ static const struct mtk_soc_data rt5350_data = {
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
+ .rx_irq_done_mask = MTK_RX_DONE_INT,
+ .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
},
};
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 2b98f0812655..654ad3b00154 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -35,6 +35,7 @@ enum mtk_reg_base {
#define MTK_MAX_RX_LENGTH 1536
#define MTK_MAX_RX_LENGTH_2K 2048
#define MTK_TX_DMA_BUF_LEN 0x3fff
+#define MTK_TX_DMA_BUF_LEN_V2 0xffff
#define MTK_DMA_SIZE 512
#define MTK_MAC_COUNT 2
#define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN)
@@ -92,6 +93,10 @@ enum mtk_reg_base {
#define MTK_CDMQ_IG_CTRL 0x1400
#define MTK_CDMQ_STAG_EN BIT(0)
+/* CDMP Ingress Control Register */
+#define MTK_CDMP_IG_CTRL 0x400
+#define MTK_CDMP_STAG_EN BIT(0)
+
/* CDMP Exgress Control Register */
#define MTK_CDMP_EG_CTRL 0x404
@@ -111,6 +116,28 @@ enum mtk_reg_base {
/* Unicast Filter MAC Address Register - High */
#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
+/* FE global misc reg*/
+#define MTK_FE_GLO_MISC 0x124
+
+/* PSE Free Queue Flow Control */
+#define PSE_FQFC_CFG1 0x100
+#define PSE_FQFC_CFG2 0x104
+#define PSE_DROP_CFG 0x108
+
+/* PSE Input Queue Reservation Register*/
+#define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2))
+
+/* PSE Output Queue Threshold Register*/
+#define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2))
+
+/* GDM and CDM Threshold */
+#define MTK_GDM2_THRES 0x1530
+#define MTK_CDMW0_THRES 0x164c
+#define MTK_CDMW1_THRES 0x1650
+#define MTK_CDME0_THRES 0x1654
+#define MTK_CDME1_THRES 0x1658
+#define MTK_CDMM_THRES 0x165c
+
/* PDMA RX Base Pointer Register */
#define MTK_PRX_BASE_PTR0 (eth->soc->reg_map[MTK_PDMA_BASE] + 0x100)
#define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
@@ -131,9 +158,12 @@ enum mtk_reg_base {
#define MTK_PDMA_LRO_CTRL_DW0 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL])
#define MTK_LRO_EN BIT(0)
#define MTK_L3_CKS_UPD_EN BIT(7)
+#define MTK_L3_CKS_UPD_EN_V2 BIT(19)
#define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
#define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
+#define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24)
#define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
+#define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28)
#define MTK_PDMA_LRO_CTRL_DW1 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x04)
#define MTK_PDMA_LRO_CTRL_DW2 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x08)
@@ -158,6 +188,7 @@ enum mtk_reg_base {
/* PDMA Global Configuration Register */
#define MTK_PDMA_GLO_CFG (eth->soc->reg_map[MTK_PDMA_BASE] + 0x204)
+#define MTK_RX_DMA_LRO_EN BIT(8)
#define MTK_MULTI_EN BIT(10)
#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
@@ -261,6 +292,13 @@ enum mtk_reg_base {
#define MTK_TX_DMA_EN BIT(0)
#define MTK_DMA_BUSY_TIMEOUT_US 1000000
+/* QDMA V2 Global Configuration Register */
+#define MTK_CHK_DDONE_EN BIT(28)
+#define MTK_DMAD_WR_WDONE BIT(26)
+#define MTK_WCOMP_EN BIT(24)
+#define MTK_RESV_BUF (0x40 << 16)
+#define MTK_MUTLI_CNT (0x4 << 12)
+
/* QDMA Reset Index Register */
#define MTK_QDMA_RST_IDX (eth->soc->reg_map[MTK_QDMA_BASE] + 0x208)
@@ -288,6 +326,8 @@ enum mtk_reg_base {
#define MTK_RX_DONE_INT MTK_RX_DONE_DLY
#define MTK_TX_DONE_INT MTK_TX_DONE_DLY
+#define MTK_RX_DONE_INT_V2 BIT(14)
+
/* QDMA Interrupt grouping registers */
#define MTK_QDMA_INT_GRP1 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x220)
#define MTK_QDMA_INT_GRP2 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x224)
@@ -340,6 +380,25 @@ enum mtk_reg_base {
#define MTK_GDM1_TX_GPCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x38)
#define MTK_STAT_OFFSET 0x40
+/* QDMA TX NUM */
+#define MTK_QDMA_TX_NUM 16
+#define MTK_QDMA_TX_MASK (MTK_QDMA_TX_NUM - 1)
+#define QID_BITS_V2(x) (((x) & 0x3f) << 16)
+#define MTK_QDMA_GMAC2_QID 8
+
+#define MTK_TX_DMA_BUF_SHIFT 8
+
+/* QDMA V2 descriptor txd6 */
+#define TX_DMA_INS_VLAN_V2 BIT(16)
+/* QDMA V2 descriptor txd5 */
+#define TX_DMA_CHKSUM_V2 (0x7 << 28)
+#define TX_DMA_TSO_V2 BIT(31)
+
+/* QDMA V2 descriptor txd4 */
+#define TX_DMA_FPORT_SHIFT_V2 8
+#define TX_DMA_FPORT_MASK_V2 0xf
+#define TX_DMA_SWC_V2 BIT(30)
+
#define MTK_WDMA0_BASE 0x2800
#define MTK_WDMA1_BASE 0x2c00
@@ -353,10 +412,9 @@ enum mtk_reg_base {
/* QDMA descriptor txd3 */
#define TX_DMA_OWNER_CPU BIT(31)
#define TX_DMA_LS0 BIT(30)
-#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
-#define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN)
+#define TX_DMA_PLEN0(_x) (((_x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
+#define TX_DMA_PLEN1(_x) ((_x) & eth->soc->txrx.dma_max_len)
#define TX_DMA_SWC BIT(14)
-#define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
/* PDMA on MT7628 */
#define TX_DMA_DONE BIT(31)
@@ -366,12 +424,14 @@ enum mtk_reg_base {
/* QDMA descriptor rxd2 */
#define RX_DMA_DONE BIT(31)
#define RX_DMA_LSO BIT(30)
-#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
-#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
+#define RX_DMA_PREP_PLEN0(_x) (((_x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
+#define RX_DMA_GET_PLEN0(_x) (((_x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
#define RX_DMA_VTAG BIT(15)
/* QDMA descriptor rxd3 */
-#define RX_DMA_VID(_x) ((_x) & 0xfff)
+#define RX_DMA_VID(x) ((x) & VLAN_VID_MASK)
+#define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK))
+#define RX_DMA_VPID(x) (((x) >> 16) & 0xffff)
/* QDMA descriptor rxd4 */
#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
@@ -382,10 +442,15 @@ enum mtk_reg_base {
/* QDMA descriptor rxd4 */
#define RX_DMA_L4_VALID BIT(24)
#define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
-#define RX_DMA_FPORT_SHIFT 19
-#define RX_DMA_FPORT_MASK 0x7
#define RX_DMA_SPECIAL_TAG BIT(22)
+#define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0xf)
+#define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0x7)
+
+/* PDMA V2 descriptor rxd3 */
+#define RX_DMA_VTAG_V2 BIT(0)
+#define RX_DMA_L4_VALID_V2 BIT(2)
+
/* PHY Indirect Access Control registers */
#define MTK_PHY_IAC 0x10004
#define PHY_IAC_ACCESS BIT(31)
@@ -508,6 +573,16 @@ enum mtk_reg_base {
#define ETHSYS_TRGMII_MT7621_APLL BIT(6)
#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
+/* ethernet reset control register */
+#define ETHSYS_RSTCTRL 0x34
+#define RSTCTRL_FE BIT(6)
+#define RSTCTRL_PPE BIT(31)
+#define RSTCTRL_PPE1 BIT(30)
+#define RSTCTRL_ETH BIT(23)
+
+/* ethernet reset check idle register */
+#define ETHSYS_FE_RST_CHK_IDLE_EN 0x28
+
/* ethernet reset control register */
#define ETHSYS_RSTCTRL 0x34
#define RSTCTRL_FE BIT(6)
@@ -592,6 +667,17 @@ struct mtk_rx_dma {
unsigned int rxd4;
} __packed __aligned(4);
+struct mtk_rx_dma_v2 {
+ unsigned int rxd1;
+ unsigned int rxd2;
+ unsigned int rxd3;
+ unsigned int rxd4;
+ unsigned int rxd5;
+ unsigned int rxd6;
+ unsigned int rxd7;
+ unsigned int rxd8;
+} __packed __aligned(4);
+
struct mtk_tx_dma {
unsigned int txd1;
unsigned int txd2;
@@ -599,6 +685,17 @@ struct mtk_tx_dma {
unsigned int txd4;
} __packed __aligned(4);
+struct mtk_tx_dma_v2 {
+ unsigned int txd1;
+ unsigned int txd2;
+ unsigned int txd3;
+ unsigned int txd4;
+ unsigned int txd5;
+ unsigned int txd6;
+ unsigned int txd7;
+ unsigned int txd8;
+} __packed __aligned(4);
+
struct mtk_eth;
struct mtk_mac;
@@ -785,7 +882,9 @@ enum mkt_eth_capabilities {
MTK_SHARED_INT_BIT,
MTK_TRGMII_MT7621_CLK_BIT,
MTK_QDMA_BIT,
+ MTK_NETSYS_V2_BIT,
MTK_SOC_MT7628_BIT,
+ MTK_RSTCTRL_PPE1_BIT,
/* MUX BITS*/
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
@@ -817,7 +916,9 @@ enum mkt_eth_capabilities {
#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
#define MTK_QDMA BIT(MTK_QDMA_BIT)
+#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
+#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
@@ -894,6 +995,7 @@ struct mtk_tx_dma_desc_info {
dma_addr_t addr;
u32 size;
u16 vlan_tci;
+ u16 qid;
u8 gso:1;
u8 csum:1;
u8 vlan:1;
@@ -913,7 +1015,11 @@ struct mtk_tx_dma_desc_info {
* @required_pctl A bool value to show whether the SoC requires
* the extra setup for those pins used by GMAC.
* @txd_size TX DMA descriptor size.
- * @rxd_size RX DMA descriptor size.
+ * @rxd_size Rx DMA descriptor size.
+ * @rx_irq_done_mask Rx irq done register mask.
+ * @rx_dma_l4_valid Rx DMA valid register mask.
+ * @dma_max_len Max DMA tx/rx buffer length.
+ * @dma_len_offset Tx/Rx DMA length field offset.
*/
struct mtk_soc_data {
const u32 *reg_map;
@@ -926,6 +1032,10 @@ struct mtk_soc_data {
struct {
u32 txd_size;
u32 rxd_size;
+ u32 rx_irq_done_mask;
+ u32 rx_dma_l4_valid;
+ u32 dma_max_len;
+ u32 dma_len_offset;
} txrx;
};
@@ -1046,7 +1156,6 @@ struct mtk_eth {
u32 tx_int_mask_reg;
u32 tx_int_status_reg;
- u32 rx_dma_l4_valid;
int ip_align;
struct mtk_ppe *ppe;
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 11/15] net: ethernet: mtk_eth_soc: introduce device register map
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
Introduce reg_map structure to add the capability to support different
register definitions.
This is a preliminary patch to introduce mt7986 ethernet support.
Tested-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 17 +++
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 160 +++++++++++++-------
2 files changed, 121 insertions(+), 56 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 1e2fddc2bdcb..4dfd43023d80 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -34,6 +34,17 @@ MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
#define MTK_ETHTOOL_STAT(x) { #x, \
offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
+static const u32 mtk_reg_map[] = {
+ [MTK_PDMA_BASE] = 0x0800,
+ [MTK_PDMA_LRO_CTRL] = 0x0980,
+ [MTK_PDMA_ALT_SCORE_DELTA_BASE] = 0x0a4c,
+ [MTK_PDMA_LRO_RX_RING_DIP_BASE] = 0x0b04,
+ [MTK_PDMA_LRO_RX_RING_CTRL_BASE] = 0x0b28,
+ [MTK_QDMA_BASE] = 0x1800,
+ [MTK_GDM1_TX_STAT_BASE] = 0x2400,
+ [MTK_PDMA_RSS_GLO_BASE] = 0x3000,
+};
+
/* strings used by ethtool */
static const struct mtk_ethtool_stats {
char str[ETH_GSTRING_LEN];
@@ -3376,6 +3387,7 @@ static int mtk_remove(struct platform_device *pdev)
}
static const struct mtk_soc_data mt2701_data = {
+ .reg_map = mtk_reg_map,
.caps = MT7623_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
@@ -3387,6 +3399,7 @@ static const struct mtk_soc_data mt2701_data = {
};
static const struct mtk_soc_data mt7621_data = {
+ .reg_map = mtk_reg_map,
.caps = MT7621_CAPS,
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7621_CLKS_BITMAP,
@@ -3399,6 +3412,7 @@ static const struct mtk_soc_data mt7621_data = {
};
static const struct mtk_soc_data mt7622_data = {
+ .reg_map = mtk_reg_map,
.ana_rgc3 = 0x2028,
.caps = MT7622_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
@@ -3412,6 +3426,7 @@ static const struct mtk_soc_data mt7622_data = {
};
static const struct mtk_soc_data mt7623_data = {
+ .reg_map = mtk_reg_map,
.caps = MT7623_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
@@ -3424,6 +3439,7 @@ static const struct mtk_soc_data mt7623_data = {
};
static const struct mtk_soc_data mt7629_data = {
+ .reg_map = mtk_reg_map,
.ana_rgc3 = 0x128,
.caps = MT7629_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
@@ -3436,6 +3452,7 @@ static const struct mtk_soc_data mt7629_data = {
};
static const struct mtk_soc_data rt5350_data = {
+ .reg_map = mtk_reg_map,
.caps = MT7628_CAPS,
.hw_features = MTK_HW_FEATURES_MT7628,
.required_clks = MT7628_CLKS_BITMAP,
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 150d692633fa..2b98f0812655 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -19,6 +19,18 @@
#include <linux/dim.h>
#include "mtk_ppe.h"
+enum mtk_reg_base {
+ MTK_PDMA_BASE,
+ MTK_PDMA_LRO_CTRL,
+ MTK_PDMA_ALT_SCORE_DELTA_BASE,
+ MTK_PDMA_LRO_RX_RING_DIP_BASE,
+ MTK_PDMA_LRO_RX_RING_CTRL_BASE,
+ MTK_PDMA_RSS_GLO_BASE,
+ MTK_GDM1_TX_STAT_BASE,
+ MTK_QDMA_BASE,
+ __MT_BASE_MAX,
+};
+
#define MTK_QDMA_PAGE_SIZE 2048
#define MTK_MAX_RX_LENGTH 1536
#define MTK_MAX_RX_LENGTH_2K 2048
@@ -100,43 +112,67 @@
#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
/* PDMA RX Base Pointer Register */
-#define MTK_PRX_BASE_PTR0 0x900
+#define MTK_PRX_BASE_PTR0 (eth->soc->reg_map[MTK_PDMA_BASE] + 0x100)
#define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
/* PDMA RX Maximum Count Register */
-#define MTK_PRX_MAX_CNT0 0x904
+#define MTK_PRX_MAX_CNT0 (MTK_PRX_BASE_PTR0 + 0x04)
#define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10))
/* PDMA RX CPU Pointer Register */
-#define MTK_PRX_CRX_IDX0 0x908
+#define MTK_PRX_CRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x08)
#define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
+/* PDMA RX DMA Pointer Register */
+#define MTK_PRX_DRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x0c)
+#define MTK_PRX_DRX_IDX_CFG(x) (MTK_PRX_DRX_IDX0 + (x * 0x10))
+
/* PDMA HW LRO Control Registers */
-#define MTK_PDMA_LRO_CTRL_DW0 0x980
+#define MTK_PDMA_LRO_CTRL_DW0 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL])
#define MTK_LRO_EN BIT(0)
#define MTK_L3_CKS_UPD_EN BIT(7)
#define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
#define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
#define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
-#define MTK_PDMA_LRO_CTRL_DW1 0x984
-#define MTK_PDMA_LRO_CTRL_DW2 0x988
-#define MTK_PDMA_LRO_CTRL_DW3 0x98c
+#define MTK_PDMA_LRO_CTRL_DW1 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x04)
+#define MTK_PDMA_LRO_CTRL_DW2 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x08)
+#define MTK_PDMA_LRO_CTRL_DW3 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x0c)
#define MTK_ADMA_MODE BIT(15)
#define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
+/* PDMA RSS Control Registers */
+#define MTK_RSS_EN BIT(0)
+#define MTK_RSS_CFG_REQ BIT(2)
+#define MTK_RSS_IPV6_STATIC_HASH (0x7 << 8)
+#define MTK_RSS_IPV4_STATIC_HASH (0x7 << 12)
+#define MTK_RSS_INDR_TABLE_DW0 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x50)
+#define MTK_RSS_INDR_TABLE_DW1 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x54)
+#define MTK_RSS_INDR_TABLE_DW2 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x58)
+#define MTK_RSS_INDR_TABLE_DW3 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x5c)
+#define MTK_RSS_INDR_TABLE_DW4 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x60)
+#define MTK_RSS_INDR_TABLE_DW5 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x64)
+#define MTK_RSS_INDR_TABLE_DW6 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x68)
+#define MTK_RSS_INDR_TABLE_DW7 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x6c)
+#define MTK_RSS_INDR_TABLE_SIZE4 0x44444444
+
/* PDMA Global Configuration Register */
-#define MTK_PDMA_GLO_CFG 0xa04
+#define MTK_PDMA_GLO_CFG (eth->soc->reg_map[MTK_PDMA_BASE] + 0x204)
#define MTK_MULTI_EN BIT(10)
#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
+/* PDMA Global Configuration Register */
+#define MTK_PDMA_RX_CFG (eth->soc->reg_map[MTK_PDMA_BASE] + 0x210)
+#define MTK_PDMA_LRO_SDL 0x3000
+#define MTK_RX_CFG_SDL_OFFSET 16
+
/* PDMA Reset Index Register */
-#define MTK_PDMA_RST_IDX 0xa08
+#define MTK_PDMA_RST_IDX (eth->soc->reg_map[MTK_PDMA_BASE] + 0x208)
#define MTK_PST_DRX_IDX0 BIT(16)
#define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
/* PDMA Delay Interrupt Register */
-#define MTK_PDMA_DELAY_INT 0xa0c
+#define MTK_PDMA_DELAY_INT (eth->soc->reg_map[MTK_PDMA_BASE] + 0x20c)
#define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0)
#define MTK_PDMA_DELAY_RX_EN BIT(15)
#define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
@@ -151,27 +187,34 @@
#define MTK_PDMA_DELAY_PTIME_MASK 0xff
/* PDMA Interrupt Status Register */
-#define MTK_PDMA_INT_STATUS 0xa20
+#define MTK_PDMA_INT_STATUS (eth->soc->reg_map[MTK_PDMA_BASE] + 0x220)
/* PDMA Interrupt Mask Register */
-#define MTK_PDMA_INT_MASK 0xa28
+#define MTK_PDMA_INT_MASK (eth->soc->reg_map[MTK_PDMA_BASE] + 0x228)
/* PDMA HW LRO Alter Flow Delta Register */
-#define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
+#define MTK_PDMA_LRO_ALT_SCORE_DELTA (eth->soc->reg_map[MTK_PDMA_ALT_SCORE_DELTA_BASE])
/* PDMA Interrupt grouping registers */
-#define MTK_PDMA_INT_GRP1 0xa50
-#define MTK_PDMA_INT_GRP2 0xa54
+#define MTK_PDMA_INT_GRP1 (eth->soc->reg_map[MTK_PDMA_BASE] + 0x250)
+#define MTK_PDMA_INT_GRP2 (eth->soc->reg_map[MTK_PDMA_BASE] + 0x254)
/* PDMA HW LRO IP Setting Registers */
-#define MTK_LRO_RX_RING0_DIP_DW0 0xb04
+#define MTK_LRO_RX_RING0_DIP_DW0 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_DIP_BASE])
#define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
#define MTK_RING_MYIP_VLD BIT(9)
+/* PDMA HW LRO ALT Debug Registers */
+#define MTK_LRO_ALT_DBG (eth->soc->reg_map[MTK_PDMA_BASE] + 0x440)
+#define MTK_LRO_ALT_INDEX_OFFSET (8)
+
+/* PDMA HW LRO ALT Data Registers */
+#define MTK_LRO_ALT_DBG_DATA (eth->soc->reg_map[MTK_PDMA_BASE] + 0x444)
+
/* PDMA HW LRO Ring Control Registers */
-#define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
-#define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
-#define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
+#define MTK_LRO_RX_RING0_CTRL_DW1 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_CTRL_BASE])
+#define MTK_LRO_RX_RING0_CTRL_DW2 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_CTRL_BASE] + 0x4)
+#define MTK_LRO_RX_RING0_CTRL_DW3 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_CTRL_BASE] + 0x8)
#define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
#define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
#define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
@@ -184,26 +227,29 @@
#define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
/* QDMA TX Queue Configuration Registers */
-#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
+#define MTK_QTX_CFG(x) (eth->soc->reg_map[MTK_QDMA_BASE] + ((x) * 0x10))
#define QDMA_RES_THRES 4
/* QDMA TX Queue Scheduler Registers */
-#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
+#define MTK_QTX_SCH(x) (eth->soc->reg_map[MTK_QDMA_BASE] + 4 + ((x) * 0x10))
/* QDMA RX Base Pointer Register */
-#define MTK_QRX_BASE_PTR0 0x1900
+#define MTK_QRX_BASE_PTR0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x100)
+#define MTK_QRX_BASE_PTR_CFG(x) (MTK_QRX_BASE_PTR0 + ((x) * 0x10))
/* QDMA RX Maximum Count Register */
-#define MTK_QRX_MAX_CNT0 0x1904
+#define MTK_QRX_MAX_CNT0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x104)
+#define MTK_QRX_MAX_CNT_CFG(x) (MTK_QRX_MAX_CNT0 + ((x) * 0x10))
/* QDMA RX CPU Pointer Register */
-#define MTK_QRX_CRX_IDX0 0x1908
+#define MTK_QRX_CRX_IDX0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x108)
+#define MTK_QRX_CRX_IDX_CFG(x) (MTK_QRX_CRX_IDX0 + ((x) * 0x10))
/* QDMA RX DMA Pointer Register */
-#define MTK_QRX_DRX_IDX0 0x190C
+#define MTK_QRX_DRX_IDX0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x10c)
/* QDMA Global Configuration Register */
-#define MTK_QDMA_GLO_CFG 0x1A04
+#define MTK_QDMA_GLO_CFG (eth->soc->reg_map[MTK_QDMA_BASE] + 0x204)
#define MTK_RX_2B_OFFSET BIT(31)
#define MTK_RX_BT_32DWORDS (3 << 11)
#define MTK_NDP_CO_PRO BIT(10)
@@ -216,19 +262,19 @@
#define MTK_DMA_BUSY_TIMEOUT_US 1000000
/* QDMA Reset Index Register */
-#define MTK_QDMA_RST_IDX 0x1A08
+#define MTK_QDMA_RST_IDX (eth->soc->reg_map[MTK_QDMA_BASE] + 0x208)
/* QDMA Delay Interrupt Register */
-#define MTK_QDMA_DELAY_INT 0x1A0C
+#define MTK_QDMA_DELAY_INT (eth->soc->reg_map[MTK_QDMA_BASE] + 0x20c)
/* QDMA Flow Control Register */
-#define MTK_QDMA_FC_THRES 0x1A10
+#define MTK_QDMA_FC_THRES (eth->soc->reg_map[MTK_QDMA_BASE] + 0x210)
#define FC_THRES_DROP_MODE BIT(20)
#define FC_THRES_DROP_EN (7 << 16)
#define FC_THRES_MIN 0x4444
/* QDMA Interrupt Status Register */
-#define MTK_QDMA_INT_STATUS 0x1A18
+#define MTK_QDMA_INT_STATUS (eth->soc->reg_map[MTK_QDMA_BASE] + 0x218)
#define MTK_RX_DONE_DLY BIT(30)
#define MTK_TX_DONE_DLY BIT(28)
#define MTK_RX_DONE_INT3 BIT(19)
@@ -243,55 +289,55 @@
#define MTK_TX_DONE_INT MTK_TX_DONE_DLY
/* QDMA Interrupt grouping registers */
-#define MTK_QDMA_INT_GRP1 0x1a20
-#define MTK_QDMA_INT_GRP2 0x1a24
+#define MTK_QDMA_INT_GRP1 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x220)
+#define MTK_QDMA_INT_GRP2 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x224)
#define MTK_RLS_DONE_INT BIT(0)
/* QDMA Interrupt Status Register */
-#define MTK_QDMA_INT_MASK 0x1A1C
+#define MTK_QDMA_INT_MASK (eth->soc->reg_map[MTK_QDMA_BASE] + 0x21c)
/* QDMA Interrupt Mask Register */
-#define MTK_QDMA_HRED2 0x1A44
+#define MTK_QDMA_HRED2 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x244)
/* QDMA TX Forward CPU Pointer Register */
-#define MTK_QTX_CTX_PTR 0x1B00
+#define MTK_QTX_CTX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x300)
/* QDMA TX Forward DMA Pointer Register */
-#define MTK_QTX_DTX_PTR 0x1B04
+#define MTK_QTX_DTX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x304)
/* QDMA TX Release CPU Pointer Register */
-#define MTK_QTX_CRX_PTR 0x1B10
+#define MTK_QTX_CRX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x310)
/* QDMA TX Release DMA Pointer Register */
-#define MTK_QTX_DRX_PTR 0x1B14
+#define MTK_QTX_DRX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x314)
/* QDMA FQ Head Pointer Register */
-#define MTK_QDMA_FQ_HEAD 0x1B20
+#define MTK_QDMA_FQ_HEAD (eth->soc->reg_map[MTK_QDMA_BASE] + 0x320)
/* QDMA FQ Head Pointer Register */
-#define MTK_QDMA_FQ_TAIL 0x1B24
+#define MTK_QDMA_FQ_TAIL (eth->soc->reg_map[MTK_QDMA_BASE] + 0x324)
/* QDMA FQ Free Page Counter Register */
-#define MTK_QDMA_FQ_CNT 0x1B28
+#define MTK_QDMA_FQ_CNT (eth->soc->reg_map[MTK_QDMA_BASE] + 0x328)
/* QDMA FQ Free Page Buffer Length Register */
-#define MTK_QDMA_FQ_BLEN 0x1B2C
+#define MTK_QDMA_FQ_BLEN (eth->soc->reg_map[MTK_QDMA_BASE] + 0x32c)
/* GMA1 counter / statics register */
-#define MTK_GDM1_RX_GBCNT_L 0x2400
-#define MTK_GDM1_RX_GBCNT_H 0x2404
-#define MTK_GDM1_RX_GPCNT 0x2408
-#define MTK_GDM1_RX_OERCNT 0x2410
-#define MTK_GDM1_RX_FERCNT 0x2414
-#define MTK_GDM1_RX_SERCNT 0x2418
-#define MTK_GDM1_RX_LENCNT 0x241c
-#define MTK_GDM1_RX_CERCNT 0x2420
-#define MTK_GDM1_RX_FCCNT 0x2424
-#define MTK_GDM1_TX_SKIPCNT 0x2428
-#define MTK_GDM1_TX_COLCNT 0x242c
-#define MTK_GDM1_TX_GBCNT_L 0x2430
-#define MTK_GDM1_TX_GBCNT_H 0x2434
-#define MTK_GDM1_TX_GPCNT 0x2438
+#define MTK_GDM1_RX_GBCNT_L (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE])
+#define MTK_GDM1_RX_GBCNT_H (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x4)
+#define MTK_GDM1_RX_GPCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x8)
+#define MTK_GDM1_RX_OERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x10)
+#define MTK_GDM1_RX_FERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x14)
+#define MTK_GDM1_RX_SERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x18)
+#define MTK_GDM1_RX_LENCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x1c)
+#define MTK_GDM1_RX_CERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x20)
+#define MTK_GDM1_RX_FCCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x24)
+#define MTK_GDM1_TX_SKIPCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x28)
+#define MTK_GDM1_TX_COLCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x2c)
+#define MTK_GDM1_TX_GBCNT_L (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x30)
+#define MTK_GDM1_TX_GBCNT_H (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x34)
+#define MTK_GDM1_TX_GPCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x38)
#define MTK_STAT_OFFSET 0x40
#define MTK_WDMA0_BASE 0x2800
@@ -857,6 +903,7 @@ struct mtk_tx_dma_desc_info {
/* struct mtk_eth_data - This is the structure holding all differences
* among various plaforms
+ * @reg_map: Device register map
* @ana_rgc3: The offset for register ANA_RGC3 related to
* sgmiisys syscon
* @caps Flags shown the extra capability for the SoC
@@ -869,6 +916,7 @@ struct mtk_tx_dma_desc_info {
* @rxd_size RX DMA descriptor size.
*/
struct mtk_soc_data {
+ const u32 *reg_map;
u32 ana_rgc3;
u32 caps;
u32 required_clks;
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 10/15] net: ethernet: mtk_eth_soc: rely on rxd_size field in mtk_rx_alloc/mtk_rx_clean
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
This is a preliminary patch to add mt7986 ethernet support.
Tested-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 26 ++++++++++++++-------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index d431311578e8..1e2fddc2bdcb 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1728,18 +1728,25 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
return -ENOMEM;
for (i = 0; i < rx_dma_size; i++) {
+ struct mtk_rx_dma *rxd;
+
dma_addr_t dma_addr = dma_map_single(eth->dma_dev,
ring->data[i] + NET_SKB_PAD + eth->ip_align,
ring->buf_size,
DMA_FROM_DEVICE);
if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
return -ENOMEM;
- ring->dma[i].rxd1 = (unsigned int)dma_addr;
+
+ rxd = (void *)ring->dma + i * eth->soc->txrx.rxd_size;
+ rxd->rxd1 = (unsigned int)dma_addr;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
- ring->dma[i].rxd2 = RX_DMA_LSO;
+ rxd->rxd2 = RX_DMA_LSO;
else
- ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
+ rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
+
+ rxd->rxd3 = 0;
+ rxd->rxd4 = 0;
}
ring->dma_size = rx_dma_size;
ring->calc_idx_update = false;
@@ -1764,14 +1771,17 @@ static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
if (ring->data && ring->dma) {
for (i = 0; i < ring->dma_size; i++) {
+ struct mtk_rx_dma *rxd;
+
if (!ring->data[i])
continue;
- if (!ring->dma[i].rxd1)
+
+ rxd = (void *)ring->dma + i * eth->soc->txrx.rxd_size;
+ if (!rxd->rxd1)
continue;
- dma_unmap_single(eth->dma_dev,
- ring->dma[i].rxd1,
- ring->buf_size,
- DMA_FROM_DEVICE);
+
+ dma_unmap_single(eth->dma_dev, rxd->rxd1,
+ ring->buf_size, DMA_FROM_DEVICE);
skb_free_frag(ring->data[i]);
}
kfree(ring->data);
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 09/15] net: ethernet: mtk_eth_soc: rely on txd_size field in mtk_poll_tx/mtk_poll_rx
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
This is a preliminary to ad mt7986 ethernet support.
Tested-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index bb628b65a9e5..d431311578e8 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1211,9 +1211,12 @@ static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
return ð->rx_ring[0];
for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
+ struct mtk_rx_dma *rxd;
+
ring = ð->rx_ring[i];
idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
- if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
+ rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size;
+ if (rxd->rxd2 & RX_DMA_DONE) {
ring->calc_idx_update = true;
return ring;
}
@@ -1264,7 +1267,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
goto rx_done;
idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
- rxd = &ring->dma[idx];
+ rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size;
data = ring->data[idx];
if (!mtk_rx_get_desc(&trxd, rxd))
@@ -1453,7 +1456,7 @@ static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
mtk_tx_unmap(eth, tx_buf, true);
- desc = &ring->dma[cpu];
+ desc = (void *)ring->dma + cpu * eth->soc->txrx.txd_size;
ring->last_free = desc;
atomic_inc(&ring->free_count);
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 08/15] net: ethernet: mtk_eth_soc: add rxd_size to mtk_soc_data
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
Similar to tx counterpart, introduce rxd_size in mtk_soc_data data
structure.
This is a preliminary patch to add mt7986 ethernet support.
Tested-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 13 +++++++++----
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 ++
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index a67b22dbaac7..bb628b65a9e5 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1719,7 +1719,7 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
}
ring->dma = dma_alloc_coherent(eth->dma_dev,
- rx_dma_size * sizeof(*ring->dma),
+ rx_dma_size * eth->soc->txrx.rxd_size,
&ring->phys, GFP_ATOMIC);
if (!ring->dma)
return -ENOMEM;
@@ -1777,9 +1777,8 @@ static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
if (ring->dma) {
dma_free_coherent(eth->dma_dev,
- ring->dma_size * sizeof(*ring->dma),
- ring->dma,
- ring->phys);
+ ring->dma_size * eth->soc->txrx.rxd_size,
+ ring->dma, ring->phys);
ring->dma = NULL;
}
}
@@ -3370,6 +3369,7 @@ static const struct mtk_soc_data mt2701_data = {
.required_pctl = true,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
+ .rxd_size = sizeof(struct mtk_rx_dma),
},
};
@@ -3381,6 +3381,7 @@ static const struct mtk_soc_data mt7621_data = {
.offload_version = 2,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
+ .rxd_size = sizeof(struct mtk_rx_dma),
},
};
@@ -3393,6 +3394,7 @@ static const struct mtk_soc_data mt7622_data = {
.offload_version = 2,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
+ .rxd_size = sizeof(struct mtk_rx_dma),
},
};
@@ -3404,6 +3406,7 @@ static const struct mtk_soc_data mt7623_data = {
.offload_version = 2,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
+ .rxd_size = sizeof(struct mtk_rx_dma),
},
};
@@ -3415,6 +3418,7 @@ static const struct mtk_soc_data mt7629_data = {
.required_pctl = false,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
+ .rxd_size = sizeof(struct mtk_rx_dma),
},
};
@@ -3425,6 +3429,7 @@ static const struct mtk_soc_data rt5350_data = {
.required_pctl = false,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
+ .rxd_size = sizeof(struct mtk_rx_dma),
},
};
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 495f623b62ef..150d692633fa 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -866,6 +866,7 @@ struct mtk_tx_dma_desc_info {
* @required_pctl A bool value to show whether the SoC requires
* the extra setup for those pins used by GMAC.
* @txd_size TX DMA descriptor size.
+ * @rxd_size RX DMA descriptor size.
*/
struct mtk_soc_data {
u32 ana_rgc3;
@@ -876,6 +877,7 @@ struct mtk_soc_data {
netdev_features_t hw_features;
struct {
u32 txd_size;
+ u32 rxd_size;
} txrx;
};
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 07/15] net: ethernet: mtk_eth_soc: rely on txd_size in txd_to_idx
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
This is a preliminary patch to add mt7986 ethernet support.
Tested-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 5f0082f92cc7..a67b22dbaac7 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -852,9 +852,10 @@ static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
return ring->dma_pdma - ring->dma + dma;
}
-static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma)
+static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma,
+ u32 txd_size)
{
- return ((void *)dma - (void *)ring->dma) / sizeof(*dma);
+ return ((void *)dma - (void *)ring->dma) / txd_size;
}
static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
@@ -1070,8 +1071,10 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
!netdev_xmit_more())
mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
} else {
- int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd),
- ring->dma_size);
+ int next_idx;
+
+ next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
+ ring->dma_size);
mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
}
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 06/15] net: ethernet: mtk_eth_soc: rely on txd_size in mtk_desc_to_tx_buf
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
This is a preliminary patch to add mt7986 ethernet support.
Tested-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 26 ++++++++++++---------
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index a48e93792db1..5f0082f92cc7 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -837,10 +837,11 @@ static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
return ret + (desc - ring->phys);
}
-static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
- struct mtk_tx_dma *txd)
+static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
+ struct mtk_tx_dma *txd,
+ u32 txd_size)
{
- int idx = txd - ring->dma;
+ int idx = ((void *)txd - (void *)ring->dma) / txd_size;
return &ring->buf[idx];
}
@@ -962,6 +963,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
};
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
+ const struct mtk_soc_data *soc = eth->soc;
struct mtk_tx_dma *itxd, *txd;
struct mtk_tx_dma *itxd_pdma, *txd_pdma;
struct mtk_tx_buf *itx_buf, *tx_buf;
@@ -973,7 +975,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
if (itxd == ring->last_free)
return -ENOMEM;
- itx_buf = mtk_desc_to_tx_buf(ring, itxd);
+ itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
memset(itx_buf, 0, sizeof(*itx_buf));
txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
@@ -1001,7 +1003,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
while (frag_size) {
bool new_desc = true;
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) ||
+ if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) ||
(i & 0x1)) {
txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
txd_pdma = qdma_to_pdma(ring, txd);
@@ -1025,7 +1027,8 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
mtk_tx_set_dma_desc(dev, txd, &txd_info);
- tx_buf = mtk_desc_to_tx_buf(ring, txd);
+ tx_buf = mtk_desc_to_tx_buf(ring, txd,
+ soc->txrx.txd_size);
if (new_desc)
memset(tx_buf, 0, sizeof(*tx_buf));
tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
@@ -1044,7 +1047,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
/* store skb to cleanup */
itx_buf->skb = skb;
- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
+ if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
if (k & 0x1)
txd_pdma->txd2 |= TX_DMA_LS0;
else
@@ -1062,7 +1065,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
*/
wmb();
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
+ if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) ||
!netdev_xmit_more())
mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
@@ -1076,13 +1079,13 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
err_dma:
do {
- tx_buf = mtk_desc_to_tx_buf(ring, itxd);
+ tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
/* unmap dma */
mtk_tx_unmap(eth, tx_buf, false);
itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
+ if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
@@ -1393,7 +1396,8 @@ static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
break;
- tx_buf = mtk_desc_to_tx_buf(ring, desc);
+ tx_buf = mtk_desc_to_tx_buf(ring, desc,
+ eth->soc->txrx.txd_size);
if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
mac = 1;
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 05/15] net: ethernet: mtk_eth_soc: rely on txd_size in mtk_tx_alloc/mtk_tx_clean
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
This is a preliminary patch to add mt7986 ethernet support.
Tested-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 39 ++++++++++++---------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index cde66463bf98..a48e93792db1 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1568,25 +1568,30 @@ static int mtk_napi_rx(struct napi_struct *napi, int budget)
static int mtk_tx_alloc(struct mtk_eth *eth)
{
+ const struct mtk_soc_data *soc = eth->soc;
struct mtk_tx_ring *ring = ð->tx_ring;
- int i, sz = sizeof(*ring->dma);
+ struct mtk_tx_dma *txd;
+ int i;
ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
GFP_KERNEL);
if (!ring->buf)
goto no_tx_mem;
- ring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz,
+ ring->dma = dma_alloc_coherent(eth->dma_dev,
+ MTK_DMA_SIZE * soc->txrx.txd_size,
&ring->phys, GFP_ATOMIC);
if (!ring->dma)
goto no_tx_mem;
for (i = 0; i < MTK_DMA_SIZE; i++) {
int next = (i + 1) % MTK_DMA_SIZE;
- u32 next_ptr = ring->phys + next * sz;
+ u32 next_ptr = ring->phys + next * soc->txrx.txd_size;
- ring->dma[i].txd2 = next_ptr;
- ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
+ txd = (void *)ring->dma + i * soc->txrx.txd_size;
+ txd->txd2 = next_ptr;
+ txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
+ txd->txd4 = 0;
}
/* On MT7688 (PDMA only) this driver uses the ring->dma structs
@@ -1594,9 +1599,9 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
* descriptors in ring->dma_pdma.
*/
if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
- ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz,
- &ring->phys_pdma,
- GFP_ATOMIC);
+ ring->dma_pdma = dma_alloc_coherent(eth->dma_dev,
+ MTK_DMA_SIZE * soc->txrx.txd_size,
+ &ring->phys_pdma, GFP_ATOMIC);
if (!ring->dma_pdma)
goto no_tx_mem;
@@ -1609,8 +1614,9 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
ring->dma_size = MTK_DMA_SIZE;
atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
ring->next_free = &ring->dma[0];
- ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
- ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz));
+ ring->last_free = (void *)txd;
+ ring->last_free_ptr = (u32)(ring->phys +
+ (MTK_DMA_SIZE - 1) * soc->txrx.txd_size);
ring->thresh = MAX_SKB_FRAGS;
/* make sure that all changes to the dma ring are flushed before we
@@ -1622,7 +1628,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
mtk_w32(eth,
- ring->phys + ((MTK_DMA_SIZE - 1) * sz),
+ ring->phys + (MTK_DMA_SIZE - 1) * soc->txrx.txd_size,
MTK_QTX_CRX_PTR);
mtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR);
mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES,
@@ -1642,6 +1648,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
static void mtk_tx_clean(struct mtk_eth *eth)
{
+ const struct mtk_soc_data *soc = eth->soc;
struct mtk_tx_ring *ring = ð->tx_ring;
int i;
@@ -1654,17 +1661,15 @@ static void mtk_tx_clean(struct mtk_eth *eth)
if (ring->dma) {
dma_free_coherent(eth->dma_dev,
- MTK_DMA_SIZE * sizeof(*ring->dma),
- ring->dma,
- ring->phys);
+ MTK_DMA_SIZE * soc->txrx.txd_size,
+ ring->dma, ring->phys);
ring->dma = NULL;
}
if (ring->dma_pdma) {
dma_free_coherent(eth->dma_dev,
- MTK_DMA_SIZE * sizeof(*ring->dma_pdma),
- ring->dma_pdma,
- ring->phys_pdma);
+ MTK_DMA_SIZE * soc->txrx.txd_size,
+ ring->dma_pdma, ring->phys_pdma);
ring->dma_pdma = NULL;
}
}
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 04/15] net: ethernet: mtk_eth_soc: add txd_size to mtk_soc_data
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
In order to remove mtk_tx_dma size dependency, introduce txd_size in
mtk_soc_data data structure. Rely on txd_size in mtk_init_fq_dma() and
mtk_dma_free() routines.
This is a preliminary patch to add mt7986 ethernet support.
Tested-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 47 +++++++++++++++------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++
2 files changed, 38 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 085c740779de..cde66463bf98 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -784,20 +784,20 @@ static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd,
/* the qdma core needs scratch memory to be setup */
static int mtk_init_fq_dma(struct mtk_eth *eth)
{
+ const struct mtk_soc_data *soc = eth->soc;
dma_addr_t phy_ring_tail;
int cnt = MTK_DMA_SIZE;
dma_addr_t dma_addr;
int i;
eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
- cnt * sizeof(struct mtk_tx_dma),
+ cnt * soc->txrx.txd_size,
ð->phy_scratch_ring,
GFP_ATOMIC);
if (unlikely(!eth->scratch_ring))
return -ENOMEM;
- eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
- GFP_KERNEL);
+ eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
if (unlikely(!eth->scratch_head))
return -ENOMEM;
@@ -807,16 +807,19 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
return -ENOMEM;
- phy_ring_tail = eth->phy_scratch_ring +
- (sizeof(struct mtk_tx_dma) * (cnt - 1));
+ phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
for (i = 0; i < cnt; i++) {
- eth->scratch_ring[i].txd1 =
- (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
+ struct mtk_tx_dma *txd;
+
+ txd = (void *)eth->scratch_ring + i * soc->txrx.txd_size;
+ txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
if (i < cnt - 1)
- eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
- ((i + 1) * sizeof(struct mtk_tx_dma)));
- eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
+ txd->txd2 = eth->phy_scratch_ring +
+ (i + 1) * soc->txrx.txd_size;
+
+ txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
+ txd->txd4 = 0;
}
mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
@@ -2108,6 +2111,7 @@ static int mtk_dma_init(struct mtk_eth *eth)
static void mtk_dma_free(struct mtk_eth *eth)
{
+ const struct mtk_soc_data *soc = eth->soc;
int i;
for (i = 0; i < MTK_MAC_COUNT; i++)
@@ -2115,9 +2119,8 @@ static void mtk_dma_free(struct mtk_eth *eth)
netdev_reset_queue(eth->netdev[i]);
if (eth->scratch_ring) {
dma_free_coherent(eth->dma_dev,
- MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
- eth->scratch_ring,
- eth->phy_scratch_ring);
+ MTK_DMA_SIZE * soc->txrx.txd_size,
+ eth->scratch_ring, eth->phy_scratch_ring);
eth->scratch_ring = NULL;
eth->phy_scratch_ring = 0;
}
@@ -3353,6 +3356,9 @@ static const struct mtk_soc_data mt2701_data = {
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true,
+ .txrx = {
+ .txd_size = sizeof(struct mtk_tx_dma),
+ },
};
static const struct mtk_soc_data mt7621_data = {
@@ -3361,6 +3367,9 @@ static const struct mtk_soc_data mt7621_data = {
.required_clks = MT7621_CLKS_BITMAP,
.required_pctl = false,
.offload_version = 2,
+ .txrx = {
+ .txd_size = sizeof(struct mtk_tx_dma),
+ },
};
static const struct mtk_soc_data mt7622_data = {
@@ -3370,6 +3379,9 @@ static const struct mtk_soc_data mt7622_data = {
.required_clks = MT7622_CLKS_BITMAP,
.required_pctl = false,
.offload_version = 2,
+ .txrx = {
+ .txd_size = sizeof(struct mtk_tx_dma),
+ },
};
static const struct mtk_soc_data mt7623_data = {
@@ -3378,6 +3390,9 @@ static const struct mtk_soc_data mt7623_data = {
.required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true,
.offload_version = 2,
+ .txrx = {
+ .txd_size = sizeof(struct mtk_tx_dma),
+ },
};
static const struct mtk_soc_data mt7629_data = {
@@ -3386,6 +3401,9 @@ static const struct mtk_soc_data mt7629_data = {
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7629_CLKS_BITMAP,
.required_pctl = false,
+ .txrx = {
+ .txd_size = sizeof(struct mtk_tx_dma),
+ },
};
static const struct mtk_soc_data rt5350_data = {
@@ -3393,6 +3411,9 @@ static const struct mtk_soc_data rt5350_data = {
.hw_features = MTK_HW_FEATURES_MT7628,
.required_clks = MT7628_CLKS_BITMAP,
.required_pctl = false,
+ .txrx = {
+ .txd_size = sizeof(struct mtk_tx_dma),
+ },
};
const struct of_device_id of_mtk_match[] = {
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 5d940315c7ba..495f623b62ef 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -865,6 +865,7 @@ struct mtk_tx_dma_desc_info {
* the target SoC
* @required_pctl A bool value to show whether the SoC requires
* the extra setup for those pins used by GMAC.
+ * @txd_size TX DMA descriptor size.
*/
struct mtk_soc_data {
u32 ana_rgc3;
@@ -873,6 +874,9 @@ struct mtk_soc_data {
bool required_pctl;
u8 offload_version;
netdev_features_t hw_features;
+ struct {
+ u32 txd_size;
+ } txrx;
};
/* currently no SoC has more than 2 macs */
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 03/15] net: ethernet: mtk_eth_soc: move tx dma desc configuration in mtk_tx_set_dma_desc
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
Move tx dma descriptor configuration in mtk_tx_set_dma_desc routine.
This is a preliminary patch to introduce mt7986 ethernet support since
it relies on a different tx dma descriptor layout.
Tested-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 105 +++++++++++---------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++
2 files changed, 67 insertions(+), 49 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 31c5da5d6b72..085c740779de 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -918,18 +918,51 @@ static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
}
}
+static void mtk_tx_set_dma_desc(struct net_device *dev, struct mtk_tx_dma *desc,
+ struct mtk_tx_dma_desc_info *info)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ u32 data;
+
+ WRITE_ONCE(desc->txd1, info->addr);
+
+ data = TX_DMA_SWC | TX_DMA_PLEN0(info->size);
+ if (info->last)
+ data |= TX_DMA_LS0;
+ WRITE_ONCE(desc->txd3, data);
+
+ data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */
+ if (info->first) {
+ if (info->gso)
+ data |= TX_DMA_TSO;
+ /* tx checksum offload */
+ if (info->csum)
+ data |= TX_DMA_CHKSUM;
+ /* vlan header offload */
+ if (info->vlan)
+ data |= TX_DMA_INS_VLAN | info->vlan_tci;
+ }
+ WRITE_ONCE(desc->txd4, data);
+}
+
static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
int tx_num, struct mtk_tx_ring *ring, bool gso)
{
+ struct mtk_tx_dma_desc_info txd_info = {
+ .size = skb_headlen(skb),
+ .gso = gso,
+ .csum = skb->ip_summed == CHECKSUM_PARTIAL,
+ .vlan = skb_vlan_tag_present(skb),
+ .vlan_tci = skb_vlan_tag_get(skb),
+ .first = true,
+ .last = !skb_is_nonlinear(skb),
+ };
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
struct mtk_tx_dma *itxd, *txd;
struct mtk_tx_dma *itxd_pdma, *txd_pdma;
struct mtk_tx_buf *itx_buf, *tx_buf;
- dma_addr_t mapped_addr;
- unsigned int nr_frags;
int i, n_desc = 1;
- u32 txd4 = 0, fport;
int k = 0;
itxd = ring->next_free;
@@ -937,49 +970,32 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
if (itxd == ring->last_free)
return -ENOMEM;
- /* set the forward port */
- fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
- txd4 |= fport;
-
itx_buf = mtk_desc_to_tx_buf(ring, itxd);
memset(itx_buf, 0, sizeof(*itx_buf));
- if (gso)
- txd4 |= TX_DMA_TSO;
-
- /* TX Checksum offload */
- if (skb->ip_summed == CHECKSUM_PARTIAL)
- txd4 |= TX_DMA_CHKSUM;
-
- /* VLAN header offload */
- if (skb_vlan_tag_present(skb))
- txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
-
- mapped_addr = dma_map_single(eth->dma_dev, skb->data,
- skb_headlen(skb), DMA_TO_DEVICE);
- if (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr)))
+ txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
+ DMA_TO_DEVICE);
+ if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
return -ENOMEM;
- WRITE_ONCE(itxd->txd1, mapped_addr);
+ mtk_tx_set_dma_desc(dev, itxd, &txd_info);
+
itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
MTK_TX_FLAGS_FPORT1;
- setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb),
+ setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
k++);
/* TX SG offload */
txd = itxd;
txd_pdma = qdma_to_pdma(ring, txd);
- nr_frags = skb_shinfo(skb)->nr_frags;
- for (i = 0; i < nr_frags; i++) {
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
unsigned int offset = 0;
int frag_size = skb_frag_size(frag);
while (frag_size) {
- bool last_frag = false;
- unsigned int frag_map_size;
bool new_desc = true;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) ||
@@ -994,23 +1010,17 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
new_desc = false;
}
-
- frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
- mapped_addr = skb_frag_dma_map(eth->dma_dev, frag, offset,
- frag_map_size,
- DMA_TO_DEVICE);
- if (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr)))
+ memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
+ txd_info.size = min(frag_size, MTK_TX_DMA_BUF_LEN);
+ txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
+ !(frag_size - txd_info.size);
+ txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
+ offset, txd_info.size,
+ DMA_TO_DEVICE);
+ if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
goto err_dma;
- if (i == nr_frags - 1 &&
- (frag_size - frag_map_size) == 0)
- last_frag = true;
-
- WRITE_ONCE(txd->txd1, mapped_addr);
- WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
- TX_DMA_PLEN0(frag_map_size) |
- last_frag * TX_DMA_LS0));
- WRITE_ONCE(txd->txd4, fport);
+ mtk_tx_set_dma_desc(dev, txd, &txd_info);
tx_buf = mtk_desc_to_tx_buf(ring, txd);
if (new_desc)
@@ -1020,20 +1030,17 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
MTK_TX_FLAGS_FPORT1;
- setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr,
- frag_map_size, k++);
+ setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
+ txd_info.size, k++);
- frag_size -= frag_map_size;
- offset += frag_map_size;
+ frag_size -= txd_info.size;
+ offset += txd_info.size;
}
}
/* store skb to cleanup */
itx_buf->skb = skb;
- WRITE_ONCE(itxd->txd4, txd4);
- WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
- (!nr_frags * TX_DMA_LS0)));
if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
if (k & 0x1)
txd_pdma->txd2 |= TX_DMA_LS0;
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index b04977fa84f6..5d940315c7ba 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -844,6 +844,17 @@ enum mkt_eth_capabilities {
MTK_MUX_U3_GMAC2_TO_QPHY | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
+struct mtk_tx_dma_desc_info {
+ dma_addr_t addr;
+ u32 size;
+ u16 vlan_tci;
+ u8 gso:1;
+ u8 csum:1;
+ u8 vlan:1;
+ u8 first:1;
+ u8 last:1;
+};
+
/* struct mtk_eth_data - This is the structure holding all differences
* among various plaforms
* @ana_rgc3: The offset for register ANA_RGC3 related to
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 02/15] dt-bindings: net: mediatek,net: add mt7986-eth binding
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
Introduce dts bindings for mt7986 soc in mediatek,net.yaml.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
.../devicetree/bindings/net/mediatek,net.yaml | 141 +++++++++++++++++-
1 file changed, 139 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
index 43cc4024ef98..699164dd1295 100644
--- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
@@ -21,6 +21,7 @@ properties:
- mediatek,mt7623-eth
- mediatek,mt7622-eth
- mediatek,mt7629-eth
+ - mediatek,mt7986-eth
- ralink,rt5350-eth
reg:
@@ -28,7 +29,7 @@ properties:
interrupts:
minItems: 3
- maxItems: 3
+ maxItems: 4
power-domains:
maxItems: 1
@@ -88,6 +89,9 @@ allOf:
- mediatek,mt7623-eth
then:
properties:
+ interrupts:
+ maxItems: 3
+
clocks:
minItems: 4
maxItems: 4
@@ -112,6 +116,9 @@ allOf:
const: mediatek,mt7622-eth
then:
properties:
+ interrupts:
+ maxItems: 3
+
clocks:
minItems: 11
maxItems: 11
@@ -155,6 +162,9 @@ allOf:
const: mediatek,mt7629-eth
then:
properties:
+ interrupts:
+ maxItems: 3
+
clocks:
minItems: 17
maxItems: 17
@@ -189,6 +199,42 @@ allOf:
minItems: 2
maxItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt7986-eth
+ then:
+ properties:
+ interrupts:
+ minItems: 4
+
+ clocks:
+ minItems: 15
+ maxItems: 15
+
+ clock-names:
+ items:
+ - const: fe
+ - const: gp2
+ - const: gp1
+ - const: wocpu1
+ - const: wocpu0
+ - const: sgmii_tx250m
+ - const: sgmii_rx250m
+ - const: sgmii_cdr_ref
+ - const: sgmii_cdr_fb
+ - const: sgmii2_tx250m
+ - const: sgmii2_rx250m
+ - const: sgmii2_cdr_ref
+ - const: sgmii2_cdr_fb
+ - const: netsys0
+ - const: netsys1
+
+ mediatek,sgmiisys:
+ minItems: 2
+ maxItems: 2
+
patternProperties:
"^mac@[0-1]$":
type: object
@@ -219,7 +265,6 @@ required:
- interrupts
- clocks
- clock-names
- - power-domains
- mediatek,ethsys
unevaluatedProperties: false
@@ -295,3 +340,95 @@ examples:
};
};
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/mt7622-clk.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ eth: ethernet@15100000 {
+ #define CLK_ETH_FE_EN 0
+ #define CLK_ETH_WOCPU1_EN 3
+ #define CLK_ETH_WOCPU0_EN 4
+ #define CLK_TOP_NETSYS_SEL 43
+ #define CLK_TOP_NETSYS_500M_SEL 44
+ #define CLK_TOP_NETSYS_2X_SEL 46
+ #define CLK_TOP_SGM_325M_SEL 47
+ #define CLK_APMIXED_NET2PLL 1
+ #define CLK_APMIXED_SGMPLL 3
+
+ compatible = "mediatek,mt7986-eth";
+ reg = <0 0x15100000 0 0x80000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <ðsys CLK_ETH_FE_EN>,
+ <ðsys CLK_ETH_GP2_EN>,
+ <ðsys CLK_ETH_GP1_EN>,
+ <ðsys CLK_ETH_WOCPU1_EN>,
+ <ðsys CLK_ETH_WOCPU0_EN>,
+ <&sgmiisys0 CLK_SGMII_TX250M_EN>,
+ <&sgmiisys0 CLK_SGMII_RX250M_EN>,
+ <&sgmiisys0 CLK_SGMII_CDR_REF>,
+ <&sgmiisys0 CLK_SGMII_CDR_FB>,
+ <&sgmiisys1 CLK_SGMII_TX250M_EN>,
+ <&sgmiisys1 CLK_SGMII_RX250M_EN>,
+ <&sgmiisys1 CLK_SGMII_CDR_REF>,
+ <&sgmiisys1 CLK_SGMII_CDR_FB>,
+ <&topckgen CLK_TOP_NETSYS_SEL>,
+ <&topckgen CLK_TOP_NETSYS_SEL>;
+ clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
+ "sgmii_tx250m", "sgmii_rx250m",
+ "sgmii_cdr_ref", "sgmii_cdr_fb",
+ "sgmii2_tx250m", "sgmii2_rx250m",
+ "sgmii2_cdr_ref", "sgmii2_cdr_fb",
+ "netsys0", "netsys1";
+ mediatek,ethsys = <ðsys>;
+ mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+ <&topckgen CLK_TOP_SGM_325M_SEL>;
+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
+ <&apmixedsys CLK_APMIXED_SGMPLL>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy5: ethernet-phy@0 {
+ compatible = "ethernet-phy-id67c9.de0a";
+ phy-mode = "2500base-x";
+ reset-gpios = <&pio 6 1>;
+ reset-deassert-us = <20000>;
+ reg = <5>;
+ };
+
+ phy6: ethernet-phy@1 {
+ compatible = "ethernet-phy-id67c9.de0a";
+ phy-mode = "2500base-x";
+ reg = <6>;
+ };
+ };
+
+ mac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ phy-mode = "2500base-x";
+ phy-handle = <&phy5>;
+ reg = <0>;
+ };
+
+ mac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ phy-mode = "2500base-x";
+ phy-handle = <&phy6>;
+ reg = <1>;
+ };
+ };
+ };
--
2.35.3
^ permalink raw reply related
* [PATCH v2 net-next 01/15] arm64: dts: mediatek: mt7986: introduce ethernet nodes
From: Lorenzo Bianconi @ 2022-05-16 16:06 UTC (permalink / raw)
To: netdev
Cc: nbd, john, sean.wang, Mark-MC.Lee, davem, edumazet, kuba, pabeni,
Sam.Shih, linux-mediatek, devicetree, robh, lorenzo.bianconi
In-Reply-To: <cover.1652716741.git.lorenzo@kernel.org>
Introduce ethernet nodes in mt7986 bindings in order to
enable mt7986a/mt7986b ethernet support.
Co-developed-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 74 ++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 39 +++++++++++
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 70 ++++++++++++++++++
3 files changed, 183 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
index 21e420829572..882277a52b69 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -25,6 +25,80 @@ memory@40000000 {
};
};
+ð {
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ mdio: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+&mdio {
+ switch: switch@0 {
+ compatible = "mediatek,mt7531";
+ reg = <31>;
+ reset-gpios = <&pio 5 0>;
+ };
+};
+
+&switch {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan4";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index 694acf8f5b70..d2636a0ed152 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -222,6 +222,45 @@ ethsys: syscon@15000000 {
#reset-cells = <1>;
};
+ eth: ethernet@15100000 {
+ compatible = "mediatek,mt7986-eth";
+ reg = <0 0x15100000 0 0x80000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <ðsys CLK_ETH_FE_EN>,
+ <ðsys CLK_ETH_GP2_EN>,
+ <ðsys CLK_ETH_GP1_EN>,
+ <ðsys CLK_ETH_WOCPU1_EN>,
+ <ðsys CLK_ETH_WOCPU0_EN>,
+ <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
+ <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
+ <&sgmiisys0 CLK_SGMII0_CDR_REF>,
+ <&sgmiisys0 CLK_SGMII0_CDR_FB>,
+ <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
+ <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
+ <&sgmiisys1 CLK_SGMII1_CDR_REF>,
+ <&sgmiisys1 CLK_SGMII1_CDR_FB>,
+ <&topckgen CLK_TOP_NETSYS_SEL>,
+ <&topckgen CLK_TOP_NETSYS_500M_SEL>;
+ clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
+ "sgmii_tx250m", "sgmii_rx250m",
+ "sgmii_cdr_ref", "sgmii_cdr_fb",
+ "sgmii2_tx250m", "sgmii2_rx250m",
+ "sgmii2_cdr_ref", "sgmii2_cdr_fb",
+ "netsys0", "netsys1";
+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+ <&topckgen CLK_TOP_SGM_325M_SEL>;
+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
+ <&apmixedsys CLK_APMIXED_SGMPLL>;
+ mediatek,ethsys = <ðsys>;
+ mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
+ #reset-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
index d73467ea3641..0f49d5764ff3 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
@@ -28,3 +28,73 @@ memory@40000000 {
&uart0 {
status = "okay";
};
+
+ð {
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ mdio: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@0 {
+ compatible = "mediatek,mt7531";
+ reg = <31>;
+ reset-gpios = <&pio 5 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan4";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };
+};
--
2.35.3
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox