* [PATCH v1 12/22] clk: starfive: Introduce inverter and divider
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Introduce inverter and divider for starfive clocks.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/clk-starfive-common.c | 12 ++++++++++++
drivers/clk/starfive/clk-starfive-common.h | 8 ++++++++
2 files changed, 20 insertions(+)
diff --git a/drivers/clk/starfive/clk-starfive-common.c b/drivers/clk/starfive/clk-starfive-common.c
index 9c0eb7a50d1e..d84b326c9aed 100644
--- a/drivers/clk/starfive/clk-starfive-common.c
+++ b/drivers/clk/starfive/clk-starfive-common.c
@@ -298,6 +298,15 @@ static const struct clk_ops starfive_clk_inv_ops = {
.debug_init = starfive_clk_debug_init,
};
+static const struct clk_ops starfive_clk_idiv_ops = {
+ .get_phase = starfive_clk_get_phase,
+ .set_phase = starfive_clk_set_phase,
+ .recalc_rate = starfive_clk_recalc_rate,
+ .determine_rate = starfive_clk_determine_rate,
+ .set_rate = starfive_clk_set_rate,
+ .debug_init = starfive_clk_debug_init,
+};
+
const struct clk_ops *starfive_clk_ops(u32 max)
{
if (max & STARFIVE_CLK_DIV_MASK) {
@@ -308,6 +317,9 @@ const struct clk_ops *starfive_clk_ops(u32 max)
}
if (max & STARFIVE_CLK_ENABLE)
return &starfive_clk_gdiv_ops;
+ else if (max & STARFIVE_CLK_INVERT)
+ return &starfive_clk_idiv_ops;
+
if (max == STARFIVE_CLK_FRAC_MAX)
return &starfive_clk_fdiv_ops;
return &starfive_clk_div_ops;
diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
index a03824e9e75f..fd9bf6f20152 100644
--- a/drivers/clk/starfive/clk-starfive-common.h
+++ b/drivers/clk/starfive/clk-starfive-common.h
@@ -103,6 +103,14 @@ struct starfive_clk_data {
.parents = { [0] = _parent }, \
}
+#define STARFIVE_IDIV(_idx, _name, _flags, _max, _parent) \
+[_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = STARFIVE_CLK_INVERT | (_max), \
+ .parents = { [0] = _parent }, \
+}
+
struct starfive_clk {
struct clk_hw hw;
unsigned int idx;
--
2.25.1
^ permalink raw reply related
* [PATCH v1 10/22] clk: starfive: Add JHB100 System-2 clock generator driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add support for JHB100 System-2 clock generator (SYS2CRG).
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-sys2.c | 178 ++++++++++++++++++
3 files changed, 187 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys2.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index b6042bcb5992..729bdfce7b8a 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -91,3 +91,11 @@ config CLK_STARFIVE_JHB100_SYS1
help
Say yes here to support the system-1 clock controller on the
StarFive JHB100 SoC.
+
+config CLK_STARFIVE_JHB100_SYS2
+ bool "StarFive JHB100 system-2 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS0
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the system-2 clock controller on the
+ StarFive JHB100 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index b3571e2f0555..90b6390296bd 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys2.c b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c
new file mode 100644
index 000000000000..5111f139a1c3
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 System-2 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_SYS2CLK_NUM_CLKS (JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 + 1)
+
+/* external clocks */
+#define JHB100_SYS2CLK_OSC (JHB100_SYS2CLK_NUM_CLKS + 0)
+#define JHB100_SYS2CLK_PLL1 (JHB100_SYS2CLK_NUM_CLKS + 1)
+#define JHB100_SYS2CLK_GPU0_600 (JHB100_SYS2CLK_NUM_CLKS + 2)
+#define JHB100_SYS2CLK_GPU1_600 (JHB100_SYS2CLK_NUM_CLKS + 3)
+
+static const struct starfive_clk_data jhb100_sys2crg_clk_data[] __initconst = {
+ /* jtag mst*/
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_200, "jtagm0_200", 6,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_200, "jtagm1_200", 6,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_100, "jtagm0_100", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_100, "jtagm1_100", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_ATPG_TCLOCK, "jtagm0_atpg_tclock", 2,
+ JHB100_SYS2CLK_JTAGM0_100),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_ATPG_TCLOCK, "jtagm1_atpg_tclock", 2,
+ JHB100_SYS2CLK_JTAGM1_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_HCLK, "jtag0_mst_wrap_hclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_200),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_CLK_JTAG, "jtag0_mst_wrap_clk_jtag",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_200),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_APB_PCLK, "jtag0_mst_wrap_apb_pclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_ATPG_TCLOCK, "jtag0_mst_wrap_atpg_tclock",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_HCLK, "jtag1_mst_wrap_hclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_200),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_CLK_JTAG, "jtag1_mst_wrap_clk_jtag",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_200),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_APB_PCLK, "jtag1_mst_wrap_apb_pclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_ATPG_TCLOCK, "jtag1_mst_wrap_atpg_tclock",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_100),
+ /* hostusbcmn */
+ STARFIVE__DIV(JHB100_SYS2CLK_HOSTUSB_100, "hostusb_100", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_HOSTUSBCMN_500, "hostusbcmn_500", 4,
+ JHB100_SYS2CLK_PLL1),
+ /* bmcperiph1 */
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_200, "bmcper1_200", 6,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_250, "bmcper1_250", 5,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_143_DFT, "bmcper1_143_dft", 8,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE_GATE(JHB100_SYS2CLK_BMCPER1_143, "bmcper1_143", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_BMCPER1_143_DFT),
+ /* bmcperiph0 */
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER0_200, "bmcper0_200", 6,
+ JHB100_SYS2CLK_PLL1),
+ /* gpu0 */
+ STARFIVE__DIV(JHB100_SYS2CLK_GPU0_100, "gpu0_100", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU0_BUS_CLK, "gpu0_bus_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU0_600),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU0_APB_CLK, "gpu0_apb_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU0_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU0_OSC_CLK, "gpu0_osc_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_OSC),
+ /* gpu1 */
+ STARFIVE__DIV(JHB100_SYS2CLK_GPU1_100, "gpu1_100", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU1_BUS_CLK, "gpu1_bus_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU1_600),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU1_APB_CLK, "gpu1_apb_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU1_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU1_OSC_CLK, "gpu1_osc_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_OSC),
+ /* main icg */
+ STARFIVE_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0, "main_icg_en_jtag0", 0,
+ JHB100_SYS2CLK_JTAGM0_200),
+ STARFIVE_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1, "main_icg_en_jtag1", 0,
+ JHB100_SYS2CLK_JTAGM1_200),
+};
+
+static int __init jhb100_sys2crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_SYS2CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_SYS2CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_SYS2CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_sys2crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_sys2crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_sys2crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_sys2crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_SYS2CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_SYS2CLK_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JHB100_SYS2CLK_PLL1)
+ parents[i].fw_name = "pll1";
+ else if (pidx == JHB100_SYS2CLK_GPU0_600)
+ parents[i].fw_name = "sys2_gpu0_600";
+ else
+ parents[i].fw_name = "sys2_gpu1_600";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-sys2", 0);
+}
+
+static const struct of_device_id jhb100_sys2crg_match[] = {
+ { .compatible = "starfive,jhb100-sys2crg" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jhb100_sys2crg_driver = {
+ .driver = {
+ .name = "clk-starfive-jhb100-sys2",
+ .of_match_table = jhb100_sys2crg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jhb100_sys2crg_driver, jhb100_sys2crg_probe);
--
2.25.1
^ permalink raw reply related
* [PATCH v1 13/22] clk: starfive: Expand the storage of clock parent index
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Expand the storage of clock parent index for per0 domain, which parent
index over 255. So change u8 to u16.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/clk-starfive-common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
index fd9bf6f20152..8edc6c516451 100644
--- a/drivers/clk/starfive/clk-starfive-common.h
+++ b/drivers/clk/starfive/clk-starfive-common.h
@@ -26,7 +26,7 @@ struct starfive_clk_data {
const char *name;
unsigned long flags;
u32 max;
- u8 parents[4];
+ u16 parents[4];
};
#define STARFIVE_GATE(_idx, _name, _flags, _parent) \
--
2.25.1
^ permalink raw reply related
* [PATCH net v7 3/4] selftests: Add MACsec VLAN propagation traffic test
From: Cosmin Ratiu @ 2026-04-02 11:10 UTC (permalink / raw)
To: netdev
Cc: Sabrina Dubroca, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Stanislav Fomichev,
David Wei, Shuah Khan, linux-kselftest, Cosmin Ratiu,
Dragos Tatulea
In-Reply-To: <20260402111034.1494714-1-cratiu@nvidia.com>
Add macsec_traffic.py using NetDrvEpEnv to verify VLAN filter
propagation through offloaded MACsec devices via actual traffic.
The test creates MACsec tunnels with matching SAs on both endpoints,
stacks VLANs on top, and verifies connectivity with ping. Covers:
- Offloaded MACsec with VLAN (filters propagate to HW)
- Software MACsec with VLAN (no HW filter propagation)
- Toggle offload on/off and verify traffic still works
On netdevsim this makes use of the VLAN filter debugfs file to actually
validate that filters are applied/removed correctly.
On real hardware the traffic should validate actual VLAN filter
propagation.
Signed-off-by: Cosmin Ratiu <cratiu@nvidia.com>
---
tools/testing/selftests/drivers/net/config | 1 +
.../selftests/drivers/net/lib/py/env.py | 9 ++
tools/testing/selftests/drivers/net/macsec.py | 141 ++++++++++++++++++
3 files changed, 151 insertions(+)
diff --git a/tools/testing/selftests/drivers/net/config b/tools/testing/selftests/drivers/net/config
index d4b31a317c09..fd16994366f4 100644
--- a/tools/testing/selftests/drivers/net/config
+++ b/tools/testing/selftests/drivers/net/config
@@ -8,4 +8,5 @@ CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
CONFIG_NETCONSOLE_EXTENDED_LOG=y
CONFIG_NETDEVSIM=m
+CONFIG_VLAN_8021Q=m
CONFIG_XDP_SOCKETS=y
diff --git a/tools/testing/selftests/drivers/net/lib/py/env.py b/tools/testing/selftests/drivers/net/lib/py/env.py
index 41cc248ac848..b80666277e36 100644
--- a/tools/testing/selftests/drivers/net/lib/py/env.py
+++ b/tools/testing/selftests/drivers/net/lib/py/env.py
@@ -255,6 +255,15 @@ class NetDrvEpEnv(NetDrvEnvBase):
if nsim_test is False and self._ns is not None:
raise KsftXfailEx("Test does not work on netdevsim")
+ def get_local_nsim_dev(self):
+ """Returns the local netdevsim device or None.
+ Using this method is discouraged, as it makes tests nsim-specific.
+ Standard interfaces available on all HW should ideally be used.
+ This method is intended for the few cases where nsim-specific
+ assertions need to be verified which cannot be verified otherwise.
+ """
+ return self._ns
+
def _require_cmd(self, comm, key, host=None):
cached = self._required_cmd.get(comm, {})
if cached.get(key) is None:
diff --git a/tools/testing/selftests/drivers/net/macsec.py b/tools/testing/selftests/drivers/net/macsec.py
index 7bcfae7800fe..5da80cfc4346 100755
--- a/tools/testing/selftests/drivers/net/macsec.py
+++ b/tools/testing/selftests/drivers/net/macsec.py
@@ -6,10 +6,14 @@
import os
from lib.py import ksft_run, ksft_exit, ksft_eq, ksft_raises
+from lib.py import ksft_variants, KsftNamedVariant
from lib.py import CmdExitFailure, KsftSkipEx
from lib.py import NetDrvEpEnv
from lib.py import cmd, ip, defer, ethtool
+MACSEC_KEY = "12345678901234567890123456789012"
+MACSEC_VLAN_VID = 10
+
# Unique prefix per run to avoid collisions in the shared netns.
# Keep it short: IFNAMSIZ is 16 (incl. NUL), and VLAN names append ".<vid>".
MACSEC_PFX = f"ms{os.getpid()}_"
@@ -59,6 +63,78 @@ def _require_macsec_offload(cfg):
raise KsftSkipEx("macsec-hw-offload not supported")
+def _get_mac(ifname, host=None):
+ """Gets MAC address of an interface."""
+ dev = ip(f"-d link show dev {ifname}", json=True, host=host)
+ return dev[0]["address"]
+
+
+def _setup_macsec_sa(cfg, name):
+ """Adds matching TX/RX SAs on both ends."""
+ local_mac = _get_mac(name)
+ remote_mac = _get_mac(name, host=cfg.remote)
+
+ ip(f"macsec add {name} tx sa 0 pn 1 on key 01 {MACSEC_KEY}")
+ ip(f"macsec add {name} rx port 1 address {remote_mac}")
+ ip(f"macsec add {name} rx port 1 address {remote_mac} "
+ f"sa 0 pn 1 on key 02 {MACSEC_KEY}")
+
+ ip(f"macsec add {name} tx sa 0 pn 1 on key 02 {MACSEC_KEY}",
+ host=cfg.remote)
+ ip(f"macsec add {name} rx port 1 address {local_mac}", host=cfg.remote)
+ ip(f"macsec add {name} rx port 1 address {local_mac} "
+ f"sa 0 pn 1 on key 01 {MACSEC_KEY}", host=cfg.remote)
+
+
+def _setup_macsec_devs(cfg, name, offload):
+ """Creates macsec devices on both ends.
+
+ Only the local device gets HW offload; the remote always uses software
+ MACsec since it may not support offload at all.
+ """
+ offload_arg = "mac" if offload else "off"
+
+ ip(f"link add link {cfg.ifname} {name} "
+ f"type macsec encrypt on offload {offload_arg}")
+ defer(ip, f"link del {name}")
+ ip(f"link add link {cfg.remote_ifname} {name} "
+ f"type macsec encrypt on", host=cfg.remote)
+ defer(ip, f"link del {name}", host=cfg.remote)
+
+
+def _set_offload(name, offload):
+ """Sets offload on the local macsec device only."""
+ offload_arg = "mac" if offload else "off"
+
+ ip(f"link set {name} type macsec encrypt on offload {offload_arg}")
+
+
+def _setup_vlans(cfg, name, vid):
+ """Adds VLANs on top of existing macsec devs."""
+ vlan_name = f"{name}.{vid}"
+
+ ip(f"link add link {name} {vlan_name} type vlan id {vid}")
+ defer(ip, f"link del {vlan_name}")
+ ip(f"link add link {name} {vlan_name} type vlan id {vid}", host=cfg.remote)
+ defer(ip, f"link del {vlan_name}", host=cfg.remote)
+
+
+def _setup_vlan_ips(cfg, name, vid):
+ """Adds VLANs and IPs and brings up the macsec + VLAN devices."""
+ local_ip = "198.51.100.1"
+ remote_ip = "198.51.100.2"
+ vlan_name = f"{name}.{vid}"
+
+ ip(f"addr add {local_ip}/24 dev {vlan_name}")
+ ip(f"addr add {remote_ip}/24 dev {vlan_name}", host=cfg.remote)
+ ip(f"link set {name} up")
+ ip(f"link set {name} up", host=cfg.remote)
+ ip(f"link set {vlan_name} up")
+ ip(f"link set {vlan_name} up", host=cfg.remote)
+
+ return vlan_name, remote_ip
+
+
def test_offload_api(cfg) -> None:
"""MACsec offload API: create SecY, add SA/rx, toggle offload."""
@@ -187,6 +263,69 @@ def test_offload_state(cfg) -> None:
"features should match first offload-on snapshot")
+def _check_nsim_vid(cfg, vid, expected) -> None:
+ """Checks if a VLAN is present. Only works on netdevsim."""
+
+ nsim = cfg.get_local_nsim_dev()
+ if not nsim:
+ return
+
+ vlan_path = nsim.nsims[0].dfs_dir + "vlan"
+ with open(vlan_path, encoding="utf-8") as f:
+ vids = f.read()
+ found = f"ctag {vid}\n" in vids
+ ksft_eq(found, expected,
+ f"VLAN {vid} {'expected' if expected else 'not expected'}"
+ f" in debugfs")
+
+
+@ksft_variants([
+ KsftNamedVariant("offloaded", True),
+ KsftNamedVariant("software", False),
+])
+def test_vlan(cfg, offload) -> None:
+ """Ping through VLAN-over-macsec."""
+
+ _require_ip_macsec(cfg)
+ if offload:
+ _require_macsec_offload(cfg)
+ else:
+ _require_ip_macsec_offload()
+ name = _macsec_name()
+ _setup_macsec_devs(cfg, name, offload=offload)
+ _setup_macsec_sa(cfg, name)
+ _setup_vlans(cfg, name, MACSEC_VLAN_VID)
+ vlan_name, remote_ip = _setup_vlan_ips(cfg, name, MACSEC_VLAN_VID)
+ _check_nsim_vid(cfg, MACSEC_VLAN_VID, offload)
+ # nsim doesn't handle the data path for offloaded macsec, so skip
+ # the ping when offloaded on nsim.
+ if not offload or not cfg.get_local_nsim_dev():
+ cmd(f"ping -I {vlan_name} -c 1 -W 5 {remote_ip}")
+
+
+@ksft_variants([
+ KsftNamedVariant("on_to_off", True),
+ KsftNamedVariant("off_to_on", False),
+])
+def test_vlan_toggle(cfg, offload) -> None:
+ """Toggle offload: VLAN filters propagate/remove correctly."""
+
+ _require_ip_macsec(cfg)
+ _require_macsec_offload(cfg)
+ name = _macsec_name()
+ _setup_macsec_devs(cfg, name, offload=offload)
+ _setup_vlans(cfg, name, MACSEC_VLAN_VID)
+ _check_nsim_vid(cfg, MACSEC_VLAN_VID, offload)
+ _set_offload(name, offload=not offload)
+ _check_nsim_vid(cfg, MACSEC_VLAN_VID, not offload)
+ vlan_name, remote_ip = _setup_vlan_ips(cfg, name, MACSEC_VLAN_VID)
+ _setup_macsec_sa(cfg, name)
+ # nsim doesn't handle the data path for offloaded macsec, so skip
+ # the ping when the final state is offloaded on nsim.
+ if offload or not cfg.get_local_nsim_dev():
+ cmd(f"ping -I {vlan_name} -c 1 -W 5 {remote_ip}")
+
+
def main() -> None:
"""Main program."""
with NetDrvEpEnv(__file__) as cfg:
@@ -194,6 +333,8 @@ def main() -> None:
test_max_secy,
test_max_sc,
test_offload_state,
+ test_vlan,
+ test_vlan_toggle,
], args=(cfg,))
ksft_exit()
--
2.53.0
^ permalink raw reply related
* [PATCH v1 15/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add bindings for the Peripheral-1 clock and reset generator (PER1CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clock/starfive,jhb100-per1crg.yaml | 70 +++++++++++++++++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 60 ++++++++++++++++
.../dt-bindings/reset/starfive,jhb100-crg.h | 20 ++++++
3 files changed, 150 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml
new file mode 100644
index 000000000000..517c6dd2b19f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jhb100-per1crg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-1 Clock and Reset Generator
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jhb100-per1crg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PLL7
+ - description: Peripheral-1 600MHz
+ - description: Peripheral-1 800MHz
+ - description: Peripheral-1 200MHz
+ - description: Peripheral-1 143MHz
+
+ clock-names:
+ items:
+ - const: pll7
+ - const: per1_600
+ - const: per1_800
+ - const: per1_200
+ - const: per1_143
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jhb100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@11b40000 {
+ compatible = "starfive,jhb100-per1crg";
+ reg = <0x11b40000 0x1000>;
+ clocks = <&pll7>,
+ <&sys0crg 68>,
+ <&sys0crg 69>,
+ <&sys2crg 19>,
+ <&sys2crg 22>;
+ clock-names = "pll7", "per1_600",
+ "per1_800", "per1_200",
+ "per1_143";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 104f302b7103..95345d104585 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -387,4 +387,64 @@
#define JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_DMAC 339
#define JHB100_PER0CLK_MAIN_ICG_EN_TRNG 340
+/* PER1CRG clocks */
+#define JHB100_PER1CLK_100 0
+#define JHB100_PER1CLK_1 1
+#define JHB100_PER1CLK_200_DIVN0 2
+#define JHB100_PER1CLK_200_DIVN1 3
+#define JHB100_PER1CLK_200_DIVN2 4
+#define JHB100_PER1CLK_200_DIVN3 5
+#define JHB100_PER1CLK_200_CCLK_DIV 6
+
+#define JHB100_PER1CLK_SGPIO0_PCLK 15
+#define JHB100_PER1CLK_SGPIO0_DCLK 16
+#define JHB100_PER1CLK_SGPIO1_PCLK 17
+#define JHB100_PER1CLK_SGPIO1_DCLK 18
+
+#define JHB100_PER1CLK_EMMC0_BCLK 22
+
+#define JHB100_PER1CLK_EMMC0_CCLK 25
+
+#define JHB100_PER1CLK_DMAC1_1CH_CORE 29
+
+#define JHB100_PER1CLK_DMAC1_1CH_ACLK 31
+
+#define JHB100_PER1CLK_DMAC2_1CH_CORE 33
+
+#define JHB100_PER1CLK_DMAC2_1CH_ACLK 35
+
+#define JHB100_PER1CLK_DMAC3_1CH_CORE 37
+
+#define JHB100_PER1CLK_DMAC3_1CH_ACLK 39
+
+#define JHB100_PER1CLK_DMAC0_2CH_CORE 41
+
+#define JHB100_PER1CLK_DMAC0_2CH_ACLK 43
+
+#define JHB100_PER1CLK_UFS_REF 45
+#define JHB100_PER1CLK_UFS_300 46
+#define JHB100_PER1CLK_UFS_150 47
+#define JHB100_PER1CLK_UFS_400 48
+#define JHB100_PER1CLK_UFS_75 49
+#define JHB100_PER1CLK_UFS_37_5 50
+#define JHB100_PER1CLK_UFS_7_5 51
+#define JHB100_PER1CLK_UFS_1_875 52
+#define JHB100_PER1CLK_UFS_7_143 53
+#define JHB100_PER1CLK_UFS_3_5715 54
+
+#define JHB100_PER1CLK_MAIN_ICG_EN_SFC0 63
+#define JHB100_PER1CLK_MAIN_ICG_EN_SFC1 64
+#define JHB100_PER1CLK_MAIN_ICG_EN_SFC2 65
+#define JHB100_PER1CLK_MAIN_ICG_EN_SPI0 66
+#define JHB100_PER1CLK_MAIN_ICG_EN_SGPIO0 67
+#define JHB100_PER1CLK_MAIN_ICG_EN_SGPIO1 68
+#define JHB100_PER1CLK_MAIN_ICG_EN_SENSORS_PERIPH1 69
+#define JHB100_PER1CLK_MAIN_ICG_EN_EMMC0 70
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC0 71
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC1 72
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC2 73
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SPI0 74
+#define JHB100_PER1CLK_MAIN_ICG_EN_RAS 75
+#define JHB100_PER1CLK_MAIN_ICG_EN_UFS 76
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index bb5238cb02f6..57977d5b4018 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -143,4 +143,24 @@
#define JHB100_PER0RST_GPIO_IOMUX_PRESETN 74
#define JHB100_PER0RST_UART_MUX_REG_WRAP 75
+/* PER1CRG resets */
+#define JHB100_PER1RST_IOMUX_PRESETN 0
+#define JHB100_PER1RST_SYSCON_PRESETN 1
+#define JHB100_PER1RST_MAIN_RSTN_SFC0 2
+#define JHB100_PER1RST_MAIN_RSTN_SFC1 3
+#define JHB100_PER1RST_MAIN_RSTN_SFC2 4
+#define JHB100_PER1RST_MAIN_RSTN_SPI0 5
+#define JHB100_PER1RST_MAIN_RSTN_PERIPH1_SENSORS 6
+#define JHB100_PER1RST_MAIN_RSTN_SGPIO0 7
+#define JHB100_PER1RST_MAIN_RSTN_SGPIO1 8
+#define JHB100_PER1RST_MAIN_RSTN_EMMC0 9
+
+#define JHB100_PER1RST_MAIN_RSTN_UFS 11
+#define JHB100_PER1RST_MAIN_RSTN_UFS_PHY 12
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC0 13
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC1 14
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC2 15
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SPI0 16
+#define JHB100_PER1RST_MAIN_RSTN_PERIPH1_RAS 17
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v5 net 00/11] xsk: tailroom reservation and MTU validation
From: Maciej Fijalkowski @ 2026-04-02 11:12 UTC (permalink / raw)
To: netdev
Cc: bpf, magnus.karlsson, stfomichev, kuba, pabeni, horms,
larysa.zaremba, aleksander.lobakin, bjorn
In-Reply-To: <20260331150213.550797-1-maciej.fijalkowski@intel.com>
On Tue, Mar 31, 2026 at 05:02:02PM +0200, Maciej Fijalkowski wrote:
FWIW I'll be sending v6 as I messed up refcounting scheme on error path
for shared umem. I'm gonna also put on shelf driver cleanups as I got fed
up with issues reported by Sashiko. I plan to get back to it if I get to
work on forbidding mtu change feature on interfaces loaded with xsk
sockets.
> v4->v5:
> - add further review tags from Bjorn
> - fix ./test_progs -t xsk
> * do so by making the procfs reading common so test_xsk.c can use it
> - get back to idea of relying on pool->umem->zc in
> xsk_pool_get_tailroom(); that is because we now call its caller
> (xsk_pool_get_rx_frame_size()) before getting down to driver via
> ndo_bpf - we do it to rule out invalid setups in terms of MTU vs xsk
> frame size/number of exposed segments by driver
> - bring back explicit rejection of mbuf && segs == 1 combo
>
> v3->v4:
> - allow exact 128 bytes of space when user defined headroom is deducted
> from total frame size
> - provide a routine for reading procfs entries within xskxceiver
> * use it to fetch cache line size and calculate skb_shared_info size
> on our own
> - clean up gve and igc xsk pool enablement routines
> - include mtu vs frame size * max zc segments validation in
> xp_assign_dev()
>
> v2->v3:
> - add tags from Bjorn/Stan
> - provide at least 128 bytes instead ETH_ZLEN when validating frame
> headroom
> * this way we can get rid of i40e/ice changes
> * make sure xsk_pool_get_rx_frame_size() returns value 128b-aligned
> * and remove pre-check from idpf
> - separate XDP_UMEM_SG_FLAG fixes from MTU validation in xsk_bind()
> - make drop_idx a local variable in xsk's xdp drop prog
> - adjust rx_dropped to new 128b related values
> - move ugly placed define (Bjorn)
> - remove READ_ONCE when fetching netdev->mtu (Bjorn)
>
> v1->v2:
> - remove xsk_pool_get_tailroom() definition for !CONFIG_XDP_SOCKETS
> (Stan)
> - do not rely on pool->umem->zc when configuring tailroom (Stan, Bjorn)
> - simplify dbuff setting in ZC drivers (Bjorn)
> - use defines for {head,tail}room in tests (Bjorn)
> - return EINVAL instead of EOPNOTSUPP when mtu setting is wrong (Bjorn)
> - include vlan headers and fcs length when validating mtu (Olek)
> - tighten umem headroom validation when registering umem (Sashiko AI)
> - set XDP_USE_SG in xp_assign_dev_shared() (Sashiko AI)
> - adjust rx dropped xskxceiver test
>
> Hi,
>
> here we fix a long-standing issue regarding multi-buffer scenario in ZC
> mode - we have not been providing space at the end of the buffer where
> multi-buffer XDP works on skb_shared_info. This has been brought to our
> attention via [0].
>
> Unaligned mode does not get any specific treatment, it is user's
> responsibility to properly handle XSK addresses in queues.
>
> With adjustments included here in this set against xskxceiver I have
> been able to pass the full test suite on ice.
>
> Thanks,
> Maciej
>
> [0]: https://community.intel.com/t5/Ethernet-Products/X710-XDP-Packet-Corruption-Issue-DRV-MODE-Zero-Copy-Multi-Buffer/m-p/1724208
>
>
> Maciej Fijalkowski (11):
> xsk: tighten UMEM headroom validation to account for tailroom and min
> frame
> xsk: respect tailroom for ZC setups
> xsk: fix XDP_UMEM_SG_FLAG issues
> xsk: validate MTU against usable frame size on bind
> selftests: bpf: introduce a common routine for reading procfs
> selftests: bpf: fix pkt grow tests
> selftests: bpf: have a separate variable for drop test
> selftests: bpf: adjust rx_dropped xskxceiver's test to respect
> tailroom
> idpf: remove xsk frame size check against alignment
> igc: remove home-grown xsk's frame size validation
> gve: remove home-grown xsk's frame size validation
>
> drivers/net/ethernet/google/gve/gve_main.c | 5 --
> drivers/net/ethernet/intel/idpf/xsk.c | 10 ----
> drivers/net/ethernet/intel/igc/igc_xdp.c | 11 ----
> include/net/xdp_sock.h | 2 +-
> include/net/xdp_sock_drv.h | 17 +++++-
> net/xdp/xdp_umem.c | 3 +-
> net/xdp/xsk_buff_pool.c | 25 ++++++++-
> .../selftests/bpf/prog_tests/test_xsk.c | 55 +++++++++----------
> .../selftests/bpf/prog_tests/test_xsk.h | 23 ++++++++
> tools/testing/selftests/bpf/prog_tests/xsk.c | 19 +++++++
> .../selftests/bpf/progs/xsk_xdp_progs.c | 4 +-
> tools/testing/selftests/bpf/xskxceiver.c | 23 ++++++++
> 12 files changed, 135 insertions(+), 62 deletions(-)
>
> --
> 2.43.0
>
^ permalink raw reply
* [PATCH v1 06/22] clk: starfive: Add JHB100 System-0 clock generator driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add support for JHB100 System-0 clock generator (SYS0CRG).
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 7 +
drivers/clk/starfive/Kconfig | 11 +
drivers/clk/starfive/Makefile | 2 +
.../clk/starfive/clk-starfive-jhb100-sys0.c | 253 ++++++++++++++++++
drivers/clk/starfive/clk-starfive-jhb100.h | 11 +
5 files changed, 284 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100.h
diff --git a/MAINTAINERS b/MAINTAINERS
index b1892a480c31..3af9d79b7daf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25306,6 +25306,13 @@ S: Supported
F: Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
F: drivers/irqchip/irq-starfive-jh8100-intc.c
+STARFIVE JHB100 CLOCK DRIVERS
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: Documentation/devicetree/bindings/clock/starfive,jhb1*.yaml
+F: drivers/clk/starfive/clk-starfive-jhb1*
+F: include/dt-bindings/clock/starfive,jhb1*.h
+
STARFIVE JHB100 DEVICETREES
M: Changhuang Liang <changhuang.liang@starfivetech.com>
L: linux-riscv@lists.infradead.org
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index ff8eace36e64..7926e02ccd7d 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -72,3 +72,14 @@ config CLK_STARFIVE_JH7110_VOUT
help
Say yes here to support the Video-Output clock controller
on the StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JHB100_SYS0
+ bool "StarFive JHB100 system-0 clock support"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select AUXILIARY_BUS
+ select CLK_STARFIVE_COMMON
+ select RESET_STARFIVE_JHB100 if RESET_CONTROLLER
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the system-0 clock controller on the
+ StarFive JHB100 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 012f7ee83f8e..2c5e66d1d44e 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -10,3 +10,5 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
+
+obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys0.c b/drivers/clk/starfive/clk-starfive-jhb100-sys0.c
new file mode 100644
index 000000000000..00299b161e2b
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-sys0.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 System-0 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/auxiliary_bus.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <soc/starfive/reset-starfive-common.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_SYS0CLK_NUM_CLKS (JHB100_SYS0CLK_GPU1_600 + 1)
+
+/* external clocks */
+#define JHB100_SYS0CLK_OSC (JHB100_SYS0CLK_NUM_CLKS + 0)
+#define JHB100_SYS0CLK_PLL0 (JHB100_SYS0CLK_NUM_CLKS + 1)
+#define JHB100_SYS0CLK_PLL1 (JHB100_SYS0CLK_NUM_CLKS + 2)
+#define JHB100_SYS0CLK_PLL2 (JHB100_SYS0CLK_NUM_CLKS + 3)
+
+static const struct starfive_clk_data jhb100_sys0crg_clk_data[] __initconst = {
+ /* bmcpcierp */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPCIERP_600, "bmcpcierp_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPCIERP_100, "bmcpcierp_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_PCIE_REF_CML, "pcie_ref_cml", 24,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_DATA_INIT, "bmcpcierp_ncnoc_data_init",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_600),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG_INIT, "bmcpcierp_ncnoc_cfg_init",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_100),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_TARG, "bmcpcierp_ncnoc_targ",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_600),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_PCU, "bmcpcierp_pcu",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_OSC),
+ /* hostss0 */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS0_100, "hostss0_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS0_600, "hostss0_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS0_PHY_SCAN_400, "hostss0_phy_scan_400", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_GPIO_ESPI0_66, "gpio_espi0_66", 14,
+ JHB100_SYS0CLK_PLL2),
+ /* bmcusb */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCUSB_600, "bmcusb_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCUSB_200, "bmcusb_200", 6,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCUSB_SCANCLK, "bmcusb_scanclk", 5,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCUSB_480M_SCANCLK, "bmcusb_480m_scanclk",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCUSB_SCANCLK),
+ /* vce */
+ STARFIVE__DIV(JHB100_SYS0CLK_VCE_600, "vce_600", 10,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_VCE_100, "vce_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ /* bmcperiph2 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_600, "bmcper2_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_100, "bmcper2_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_400, "bmcper2_400", 8,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_125, "bmcper2_125", 10,
+ JHB100_SYS0CLK_PLL1),
+ /* hostss1 */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS1_600, "hostss1_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400, "hostss1_phy_scan_400", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE_GATE(JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400_ICG_BUF,
+ "hostss1_phy_scan_400_icg_buf", CLK_IS_CRITICAL,
+ JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400),
+ /* npu */
+ STARFIVE__DIV(JHB100_SYS0CLK_NPU_600, "npu_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* vout */
+ STARFIVE__DIV(JHB100_SYS0CLK_VOUT_600, "vout_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_VOUT_AUX, "vout_aux", 150,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph3 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER3_600, "bmcper3_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* hostusb */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTUSB_600, "hostusb_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* hostusbcmn */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTUSBCMN_480, "hostusbcmn_480", 5,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph1 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER1_600, "bmcper1_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER1_800, "bmcper1_800", 4,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph0 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER0_600, "bmcper0_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER0_400, "bmcper0_400", 8,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER0_800, "bmcper0_800", 8,
+ JHB100_SYS0CLK_PLL0),
+ /* gpu0 */
+ STARFIVE__DIV(JHB100_SYS0CLK_GPU0_600, "gpu0_600", 10,
+ JHB100_SYS0CLK_PLL0),
+ /* gpu1 */
+ STARFIVE__DIV(JHB100_SYS0CLK_GPU1_600, "gpu1_600", 10,
+ JHB100_SYS0CLK_PLL0),
+};
+
+static void jhb100_reset_unregister_adev(void *_adev)
+{
+ struct auxiliary_device *adev = _adev;
+
+ auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
+}
+
+static void jhb100_reset_adev_release(struct device *dev)
+{
+ struct auxiliary_device *adev = to_auxiliary_dev(dev);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
+
+ kfree(rdev);
+}
+
+int jhb100_reset_controller_register(struct starfive_clk_priv *priv,
+ const char *adev_name,
+ u32 adev_id)
+{
+ struct starfive_reset_adev *rdev;
+ struct auxiliary_device *adev;
+ int ret;
+
+ rdev = kzalloc_obj(*rdev);
+ if (!rdev)
+ return -ENOMEM;
+
+ rdev->base = priv->base;
+
+ adev = &rdev->adev;
+ adev->name = adev_name;
+ adev->dev.parent = priv->dev;
+ adev->dev.release = jhb100_reset_adev_release;
+ adev->id = adev_id;
+
+ ret = auxiliary_device_init(adev);
+ if (ret)
+ return ret;
+
+ ret = auxiliary_device_add(adev);
+ if (ret) {
+ auxiliary_device_uninit(adev);
+ return ret;
+ }
+
+ return devm_add_action_or_reset(priv->dev,
+ jhb100_reset_unregister_adev, adev);
+}
+EXPORT_SYMBOL_GPL(jhb100_reset_controller_register);
+
+static int __init jhb100_sys0crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_SYS0CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_SYS0CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_SYS0CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_sys0crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_sys0crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_sys0crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_sys0crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_SYS0CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_SYS0CLK_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JHB100_SYS0CLK_PLL0)
+ parents[i].fw_name = "pll0";
+ else if (pidx == JHB100_SYS0CLK_PLL1)
+ parents[i].fw_name = "pll1";
+ else
+ parents[i].fw_name = "pll2";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-sys0", 0);
+}
+
+static const struct of_device_id jhb100_sys0crg_match[] = {
+ { .compatible = "starfive,jhb100-sys0crg" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jhb100_sys0crg_driver = {
+ .driver = {
+ .name = "clk-starfive-jhb100-sys0",
+ .of_match_table = jhb100_sys0crg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jhb100_sys0crg_driver, jhb100_sys0crg_probe);
diff --git a/drivers/clk/starfive/clk-starfive-jhb100.h b/drivers/clk/starfive/clk-starfive-jhb100.h
new file mode 100644
index 000000000000..6c5cb3e9c610
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CLK_STARFIVE_JHB100_H
+#define __CLK_STARFIVE_JHB100_H
+
+#include "clk-starfive-common.h"
+
+int jhb100_reset_controller_register(struct starfive_clk_priv *priv,
+ const char *adev_name,
+ u32 adev_id);
+
+#endif
--
2.25.1
^ permalink raw reply related
* [PATCH v1 21/22] reset: starfive: Add StarFive JHB100 reset driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add auxiliary reset driver to support StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 6 +
drivers/reset/starfive/Kconfig | 9 ++
drivers/reset/starfive/Makefile | 1 +
.../reset/starfive/reset-starfive-jhb100.c | 121 ++++++++++++++++++
4 files changed, 137 insertions(+)
create mode 100644 drivers/reset/starfive/reset-starfive-jhb100.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 3af9d79b7daf..4ddf8ba2e60d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25319,6 +25319,12 @@ L: linux-riscv@lists.infradead.org
S: Maintained
F: arch/riscv/boot/dts/starfive/jhb100*
+STARFIVE JHB100 RESET CONTROLLER DRIVERS
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: drivers/reset/starfive/reset-starfive-jhb1*
+F: include/dt-bindings/reset/starfive,jhb1*.h
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index 29fbcf1a7d83..6f9a0f24f9b9 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -19,3 +19,12 @@ config RESET_STARFIVE_JH7110
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7110 SoC.
+
+config RESET_STARFIVE_JHB100
+ bool "StarFive JHB100 Reset Driver"
+ depends on CLK_STARFIVE_JHB100_SYS0
+ select AUXILIARY_BUS
+ select RESET_STARFIVE_COMMON
+ default ARCH_STARFIVE
+ help
+ This enables the reset controller driver for the StarFive JHB100 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index 582e4c160bd4..217002302a9f 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_RESET_STARFIVE_COMMON) += reset-starfive-common.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
+obj-$(CONFIG_RESET_STARFIVE_JHB100) += reset-starfive-jhb100.o
diff --git a/drivers/reset/starfive/reset-starfive-jhb100.c b/drivers/reset/starfive/reset-starfive-jhb100.c
new file mode 100644
index 000000000000..ab5e0f2a684f
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jhb100.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Reset driver for the StarFive JHB110 SoC
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/reset/starfive,jhb100-crg.h>
+#include <linux/auxiliary_bus.h>
+#include <soc/starfive/reset-starfive-common.h>
+
+#include "reset-starfive-common.h"
+
+#define NUM_RESETS(x) ((x) + 1)
+
+struct jhb100_reset_info {
+ unsigned int nr_resets;
+ unsigned int assert_offset;
+ unsigned int status_offset;
+};
+
+static const struct jhb100_reset_info jhb100_sys0_info = {
+ .nr_resets = NUM_RESETS(JHB100_SYS0RST_BMCUSB_RSTN_CRG),
+ .assert_offset = 0x12c,
+ .status_offset = 0x130,
+};
+
+static const struct jhb100_reset_info jhb100_sys1_info = {
+ .nr_resets = NUM_RESETS(JHB100_SYS1RST_BMCPERIPH3_RSTN_BUS),
+ .assert_offset = 0x54,
+ .status_offset = 0x58,
+};
+
+static const struct jhb100_reset_info jhb100_sys2_info = {
+ .nr_resets = NUM_RESETS(JHB100_SYS2RST_GPU1_HOST_PCIE_RST_N),
+ .assert_offset = 0x88,
+ .status_offset = 0x8c,
+};
+
+static const struct jhb100_reset_info jhb100_periph0_info = {
+ .nr_resets = NUM_RESETS(JHB100_PER0RST_UART_MUX_REG_WRAP),
+ .assert_offset = 0x554,
+ .status_offset = 0x560,
+};
+
+static const struct jhb100_reset_info jhb100_periph1_info = {
+ .nr_resets = NUM_RESETS(JHB100_PER1RST_MAIN_RSTN_PERIPH1_RAS),
+ .assert_offset = 0x134,
+ .status_offset = 0x138,
+};
+
+static const struct jhb100_reset_info jhb100_periph2_info = {
+ .nr_resets = NUM_RESETS(JHB100_PER2RST_MAIN_RSTN_PERIPH2_SENSORS),
+ .assert_offset = 0x11c,
+ .status_offset = 0x120,
+};
+
+static const struct jhb100_reset_info jhb100_periph3_info = {
+ .nr_resets = NUM_RESETS(JHB100_PER3RST_IOMUX_PRESETN),
+ .assert_offset = 0x98,
+ .status_offset = 0x9c,
+};
+
+static int jhb100_reset_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct jhb100_reset_info *info = (struct jhb100_reset_info *)(id->driver_data);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
+ void __iomem *base = rdev->base;
+
+ if (!info || !base)
+ return -ENODEV;
+
+ return reset_starfive_register(&adev->dev, adev->dev.parent->of_node,
+ base + info->assert_offset,
+ base + info->status_offset,
+ NULL, info->nr_resets, NULL);
+}
+
+static const struct auxiliary_device_id jhb100_reset_ids[] = {
+ {
+ .name = "clk_starfive_jhb100_sys0.r-sys0",
+ .driver_data = (kernel_ulong_t)&jhb100_sys0_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-sys1",
+ .driver_data = (kernel_ulong_t)&jhb100_sys1_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-sys2",
+ .driver_data = (kernel_ulong_t)&jhb100_sys2_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-per0",
+ .driver_data = (kernel_ulong_t)&jhb100_periph0_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-per1",
+ .driver_data = (kernel_ulong_t)&jhb100_periph1_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-per2",
+ .driver_data = (kernel_ulong_t)&jhb100_periph2_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-per3",
+ .driver_data = (kernel_ulong_t)&jhb100_periph3_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(auxiliary, jhb100_reset_ids);
+
+static struct auxiliary_driver jhb100_reset_driver = {
+ .probe = jhb100_reset_probe,
+ .id_table = jhb100_reset_ids,
+};
+module_auxiliary_driver(jhb100_reset_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 reset driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related
* [PATCH v1 20/22] clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add driver for the StarFive JHB100 Peripheral-3 clock controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-per3.c | 189 ++++++++++++++++++
3 files changed, 198 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per3.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 01d6d325dcd0..c612f1ede7d7 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -97,6 +97,14 @@ config CLK_STARFIVE_JHB100_PER2
Say yes here to support the peripheral-2 clock controller
on the StarFive JHB100 SoC.
+config CLK_STARFIVE_JHB100_PER3
+ bool "StarFive JHB100 peripheral-3 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS1
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the peripheral-3 clock controller
+ on the StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 044e1942ccfa..f00690f0cdad 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PER3) += clk-starfive-jhb100-per3.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per3.c b/drivers/clk/starfive/clk-starfive-jhb100-per3.c
new file mode 100644
index 000000000000..5533bb481f6d
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-per3.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 Peripheral-3 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_PER3CLK_NUM_CLKS (JHB100_PER3CLK_MAIN_ICG_EN_GMAC1 + 1)
+
+/* external clocks */
+#define JHB100_PER3CLK_100 (JHB100_PER3CLK_NUM_CLKS + 0)
+#define JHB100_PER3CLK_125 (JHB100_PER3CLK_NUM_CLKS + 1)
+#define JHB100_PER3CLK_600 (JHB100_PER3CLK_NUM_CLKS + 2)
+#define JHB100_PER3CLK_OSC (JHB100_PER3CLK_NUM_CLKS + 3)
+#define JHB100_PER3CLK_GMAC0_RMII_RCLKI (JHB100_PER3CLK_NUM_CLKS + 4)
+#define JHB100_PER3CLK_GMAC1_SGMII_TX (JHB100_PER3CLK_NUM_CLKS + 5)
+#define JHB100_PER3CLK_GMAC1_SGMII_RX (JHB100_PER3CLK_NUM_CLKS + 6)
+
+static const struct starfive_clk_data jhb100_per3crg_clk_data[] = {
+ STARFIVE__DIV(JHB100_PER3CLK_300, "per3_300", 256,
+ JHB100_PER3CLK_600),
+ STARFIVE__DIV(JHB100_PER3CLK_200, "per3_200", 256,
+ JHB100_PER3CLK_600),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC1_PTP_REF, "gmac1_ptp_ref", 2,
+ JHB100_PER3CLK_100),
+ STARFIVE__MUX(JHB100_PER3CLK_GMAC1_TX_125_MUX, "gmac1_tx_125_mux", 0, 2,
+ JHB100_PER3CLK_GMAC1_SGMII_TX,
+ JHB100_PER3CLK_125),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC1_TX, "gmac1_tx", 50,
+ JHB100_PER3CLK_GMAC1_TX_125_MUX),
+ STARFIVE__MUX(JHB100_PER3CLK_GMAC1_RX_125_MUX, "gmac1_rx_125_mux", 0, 2,
+ JHB100_PER3CLK_GMAC1_SGMII_RX,
+ JHB100_PER3CLK_125),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC1_RX, "gmac1_rx", 50,
+ JHB100_PER3CLK_GMAC1_RX_125_MUX),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC0_PTP_REF, "gmac0_ptp_ref", 2,
+ JHB100_PER3CLK_100),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC0_RMII_PLL, "gmac0_rmii_pll", 2,
+ JHB100_PER3CLK_100),
+ STARFIVE__MUX(JHB100_PER3CLK_GMAC0_RMII_MUX, "gmac0_rmii_mux", 0, 2,
+ JHB100_PER3CLK_GMAC0_RMII_PLL,
+ JHB100_PER3CLK_GMAC0_RMII_RCLKI),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2, "gmac0_rmii_mux_div2", 20,
+ JHB100_PER3CLK_GMAC0_RMII_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_TX_I, "ether0_rmii_clk_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RX_I, "ether0_rmii_clk_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_PTP_REF_I, "ether0_rmii_clk_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_PTP_REF),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RMII_I, "ether0_rmii_clk_rmii_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_CSR_I, "ether0_rmii_clk_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_ACLK_I, "ether0_rmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_300),
+ STARFIVE_GATE(JHB100_PER3CLK_GMAC0_RMII_RCLKO, "gmac0_rmii_rclko",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_PLL),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_I, "ether0_sgmii_clk_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_I, "ether0_sgmii_clk_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_125_I, "ether0_sgmii_clk_tx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX_125_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_125_I, "ether0_sgmii_clk_rx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX_125_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_PTP_REF_I, "ether0_sgmii_clk_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_PTP_REF),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_REF_25_I, "ether0_sgmii_clk_ref_25_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_OSC),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_CSR_I, "ether0_sgmii_clk_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_ACLK_I, "ether0_sgmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_300),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_PHY_PCLK_I, "ether0_sgmii_phy_pclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_SENSORS_PERIPH3, "main_icg_en_sensors_periph3", 0,
+ JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI0, "main_icg_en_peci0", 0,
+ JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI1, "main_icg_en_peci1", 0,
+ JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC0, "main_icg_en_gmac0",
+ CLK_IS_CRITICAL, JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC1, "main_icg_en_gmac1",
+ CLK_IS_CRITICAL, JHB100_PER3CLK_100),
+};
+
+static int jhb100_per3crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_PER3CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_PER3CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_PER3CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_per3crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_per3crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_per3crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_per3crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_PER3CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_PER3CLK_100)
+ parents[i].fw_name = "per3_100";
+ else if (pidx == JHB100_PER3CLK_125)
+ parents[i].fw_name = "per3_125";
+ else if (pidx == JHB100_PER3CLK_600)
+ parents[i].fw_name = "per3_600";
+ else if (pidx == JHB100_PER3CLK_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JHB100_PER3CLK_GMAC0_RMII_RCLKI)
+ parents[i].fw_name = "per3_gmac0_rmii_rclki";
+ else if (pidx == JHB100_PER3CLK_GMAC1_SGMII_TX)
+ parents[i].fw_name = "per3_gmac1_sgmii_tx";
+ else if (pidx == JHB100_PER3CLK_GMAC1_SGMII_RX)
+ parents[i].fw_name = "per3_gmac1_sgmii_rx";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-per3", 0);
+}
+
+static const struct of_device_id jhb100_per3crg_match[] = {
+ { .compatible = "starfive,jhb100-per3crg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per3crg_match);
+
+static struct platform_driver jhb100_per3crg_driver = {
+ .probe = jhb100_per3crg_probe,
+ .driver = {
+ .name = "clk-starfive-jhb100-per3",
+ .of_match_table = jhb100_per3crg_match,
+ },
+};
+module_platform_driver(jhb100_per3crg_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 Peripheral-3 Clock Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related
* [PATCH v1 16/22] clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add driver for the StarFive JHB100 Peripheral-1 clock controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-per1.c | 204 ++++++++++++++++++
3 files changed, 213 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per1.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index adf97444f460..72cf314c6cfc 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -81,6 +81,14 @@ config CLK_STARFIVE_JHB100_PER0
Say yes here to support the peripheral-0 clock controller
on the StarFive JHB100 SoC.
+config CLK_STARFIVE_JHB100_PER1
+ bool "StarFive JHB100 peripheral-1 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS2
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the peripheral-1 clock controller
+ on the StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 2f605d0fd6da..51511086a727 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per1.c b/drivers/clk/starfive/clk-starfive-jhb100-per1.c
new file mode 100644
index 000000000000..c5c1cff5d9a8
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-per1.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 Peripheral-1 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_PER1CLK_NUM_CLKS (JHB100_PER1CLK_MAIN_ICG_EN_UFS + 1)
+
+/* external clocks */
+#define JHB100_PER1CLK_143 (JHB100_PER1CLK_NUM_CLKS + 0)
+#define JHB100_PER1CLK_200 (JHB100_PER1CLK_NUM_CLKS + 1)
+#define JHB100_PER1CLK_600 (JHB100_PER1CLK_NUM_CLKS + 2)
+#define JHB100_PER1CLK_800 (JHB100_PER1CLK_NUM_CLKS + 3)
+#define JHB100_PER1CLK_PLL7 (JHB100_PER1CLK_NUM_CLKS + 4)
+
+static const struct starfive_clk_data jhb100_per1crg_clk_data[] = {
+ STARFIVE__DIV(JHB100_PER1CLK_100, "per1_100", 8, JHB100_PER1CLK_600),
+ STARFIVE__DIV(JHB100_PER1CLK_1, "per1_1", 100, JHB100_PER1CLK_100),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN0, "200_divn0", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN1, "200_divn1", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN2, "200_divn2", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN3, "200_divn3", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_CCLK_DIV, "200_cclk_div", 2046,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO0_PCLK, "sgpio0_pclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO0_DCLK, "sgpio0_dclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO1_PCLK, "sgpio1_pclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO1_DCLK, "sgpio1_dclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_EMMC0_BCLK, "emmc0_bclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_EMMC0_CCLK, "emmc0_cclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC1_1CH_CORE, "dmac1_1ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC1_1CH_ACLK, "dmac1_1ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC2_1CH_CORE, "dmac2_1ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC2_1CH_ACLK, "dmac2_1ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC3_1CH_CORE, "dmac3_1ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC3_1CH_ACLK, "dmac3_1ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC0_2CH_CORE, "dmac0_2ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC0_2CH_ACLK, "dmac0_2ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_REF, "ufs_ref", 75,
+ JHB100_PER1CLK_PLL7),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_300, "ufs_300", 2,
+ JHB100_PER1CLK_600),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_150, "ufs_150", 12,
+ JHB100_PER1CLK_600),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_400, "ufs_400", 2,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_75, "ufs_75", 2,
+ JHB100_PER1CLK_UFS_150),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_37_5, "ufs_37_5", 2,
+ JHB100_PER1CLK_UFS_75),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_7_5, "ufs_7_5", 10,
+ JHB100_PER1CLK_UFS_75),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_1_875, "ufs_1_875", 4,
+ JHB100_PER1CLK_UFS_7_5),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_7_143, "ufs_7_143", 20,
+ JHB100_PER1CLK_143),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_3_5715, "ufs_3_5715", 2,
+ JHB100_PER1CLK_UFS_7_143),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC0, "main_icg_en_sfc0", CLK_IS_CRITICAL,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC1, "main_icg_en_sfc1", CLK_IS_CRITICAL,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC2, "main_icg_en_sfc2", CLK_IS_CRITICAL,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SPI0, "main_icg_en_spi0", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_EMMC0, "main_icg_en_emmc0", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SGPIO0, "main_icg_en_sgpio0", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SGPIO1, "main_icg_en_sgpio1", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SENSORS_PERIPH1, "main_icg_en_sensors_periph1", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC0, "main_icg_en_dmac_sfc0",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC1, "main_icg_en_dmac_sfc1",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC2, "main_icg_en_dmac_sfc2",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SPI0, "main_icg_en_dmac_spi0",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_RAS, "main_icg_en_ras", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_UFS, "main_icg_en_ufs", 0,
+ JHB100_PER1CLK_100),
+};
+
+static int jhb100_per1crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_PER1CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_PER1CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_PER1CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_per1crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_per1crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_per1crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_per1crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_PER1CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_PER1CLK_600)
+ parents[i].fw_name = "per1_600";
+ else if (pidx == JHB100_PER1CLK_200)
+ parents[i].fw_name = "per1_200";
+ else if (pidx == JHB100_PER1CLK_800)
+ parents[i].fw_name = "per1_800";
+ else if (pidx == JHB100_PER1CLK_143)
+ parents[i].fw_name = "per1_143";
+ else if (pidx == JHB100_PER1CLK_PLL7)
+ parents[i].fw_name = "pll7";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-per1", 0);
+}
+
+static const struct of_device_id jhb100_per1crg_match[] = {
+ { .compatible = "starfive,jhb100-per1crg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per1crg_match);
+
+static struct platform_driver jhb100_per1crg_driver = {
+ .probe = jhb100_per1crg_probe,
+ .driver = {
+ .name = "clk-starfive-jhb100-per1",
+ .of_match_table = jhb100_per1crg_match,
+ },
+};
+module_platform_driver(jhb100_per1crg_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 Peripheral-1 Clock Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related
* [PATCH v1 18/22] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add driver for the StarFive JHB100 Peripheral-2 clock controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-per2.c | 232 ++++++++++++++++++
3 files changed, 241 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per2.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 72cf314c6cfc..01d6d325dcd0 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -89,6 +89,14 @@ config CLK_STARFIVE_JHB100_PER1
Say yes here to support the peripheral-1 clock controller
on the StarFive JHB100 SoC.
+config CLK_STARFIVE_JHB100_PER2
+ bool "StarFive JHB100 peripheral-2 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS0
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the peripheral-2 clock controller
+ on the StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 51511086a727..044e1942ccfa 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per2.c b/drivers/clk/starfive/clk-starfive-jhb100-per2.c
new file mode 100644
index 000000000000..42b9dbd11618
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-per2.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 Peripheral-2 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_PER2CLK_NUM_CLKS (JHB100_PER2CLK_MAIN_ICG_EN_GMAC3 + 1)
+
+/* external clocks */
+#define JHB100_PER2CLK_600 (JHB100_PER2CLK_NUM_CLKS + 0)
+#define JHB100_PER2CLK_400 (JHB100_PER2CLK_NUM_CLKS + 1)
+#define JHB100_PER2CLK_125 (JHB100_PER2CLK_NUM_CLKS + 2)
+#define JHB100_PER2CLK_GMAC2_RGMII_RX (JHB100_PER2CLK_NUM_CLKS + 3)
+#define JHB100_PER2CLK_GMAC2_RMII_REF (JHB100_PER2CLK_NUM_CLKS + 4)
+#define JHB100_PER2CLK_OSC (JHB100_PER2CLK_NUM_CLKS + 5)
+#define JHB100_PER2CLK_GMAC3_SGMII_TX (JHB100_PER2CLK_NUM_CLKS + 6)
+#define JHB100_PER2CLK_GMAC3_SGMII_RX (JHB100_PER2CLK_NUM_CLKS + 7)
+
+static const struct starfive_clk_data jhb100_per2crg_clk_data[] = {
+ STARFIVE__DIV(JHB100_PER2CLK_300, "per2_300", 2,
+ JHB100_PER2CLK_600),
+ STARFIVE__DIV(JHB100_PER2CLK_100, "per2_100", 4,
+ JHB100_PER2CLK_400),
+ STARFIVE__DIV(JHB100_PER2CLK_50, "per2_50", 2,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC2_RMII_50, "gmac2_rmii_50", 2,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN0_CORE_DIV, "can0_core_div", 20,
+ JHB100_PER2CLK_400),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN1_CORE_DIV, "can1_core_div", 20,
+ JHB100_PER2CLK_400),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN0_TIMER, "can0_timer", 100,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN1_TIMER, "can1_timer", 100,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_RTC_CORE_DIV, "rtc_core_div", 763,
+ JHB100_PER2CLK_OSC),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_RMII_MUX_DLY, "gmac2_rmii_mux_dly", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_REF,
+ JHB100_PER2CLK_GMAC2_RMII_50),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC2_RMII_DIV, "gmac2_rmii_div", 20,
+ JHB100_PER2CLK_GMAC2_RMII_MUX_DLY),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_RGMII_125_MUX, "gmac2_rgmii_125_mux", 0, 2,
+ JHB100_PER2CLK_GMAC2_RGMII_RX,
+ JHB100_PER2CLK_125),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC2_RGMII_DIV, "gmac2_rgmii_div", 50,
+ JHB100_PER2CLK_125),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_TX_MUX, "gmac2_tx_mux", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_DIV,
+ JHB100_PER2CLK_GMAC2_RGMII_DIV),
+ STARFIVE__INV(JHB100_PER2CLK_GMAC2_TX_180_BUF, "gmac2_tx_180_buf",
+ JHB100_PER2CLK_GMAC2_TX_MUX),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_RX_MUX_DLY, "gmac2_rx_mux_dly", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_DIV,
+ JHB100_PER2CLK_GMAC2_RGMII_125_MUX),
+ STARFIVE__INV(JHB100_PER2CLK_GMAC2_RX_180_BUF, "gmac2_rx_180_buf",
+ JHB100_PER2CLK_GMAC2_RX_MUX_DLY),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY, "gmac2_txck_mux_dly", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_50,
+ JHB100_PER2CLK_GMAC2_TX_MUX),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC3_TX_125_MUX, "gmac3_tx_125_mux", 0, 2,
+ JHB100_PER2CLK_GMAC3_SGMII_TX,
+ JHB100_PER2CLK_125),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC3_RX_125_MUX, "gmac3_rx_125_mux", 0, 2,
+ JHB100_PER2CLK_GMAC3_SGMII_RX,
+ JHB100_PER2CLK_125),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC3_TX_DIV, "gmac3_tx_div", 50,
+ JHB100_PER2CLK_GMAC3_TX_125_MUX),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC3_RX_DIV, "gmac3_rx_div", 50,
+ JHB100_PER2CLK_GMAC3_RX_125_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_SENSORS_PERIPH2, "sensors_periph2", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_FAN_TACH_PCLK, "fan_tach_pclk", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_I, "ether0_rmiiandrgmii_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_TX_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_I, "ether0_rmiiandrgmii_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RX_MUX_DLY),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_180_I, "ether0_rmiiandrgmii_tx_180_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_TX_180_BUF),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_180_I, "ether0_rmiiandrgmii_rx_180_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RX_180_BUF),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_PTP_REF_I, "ether0_rmiiandrgmii_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_50),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RMII_I, "ether0_rmiiandrgmii_rmii_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RMII_MUX_DLY),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_CSR_I, "ether0_rmiiandrgmii_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_ACLK_I, "ether0_rmiiandrgmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_300),
+ STARFIVE_GATE(JHB100_PER2CLK_RMIIANDRGMII_IOMUX_GMAC2_TXCK, "rmiiandrgmii_iomux_gmac2_txck",
+ CLK_IS_CRITICAL, JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_TX_I, "ether1_sgmii_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_TX_DIV),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_RX_I, "ether1_sgmii_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_RX_DIV),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_TX_125_I, "ether1_sgmii_tx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_TX_125_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_RX_125_I, "ether1_sgmii_rx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_RX_125_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_PTP_REF_I, "ether1_sgmii_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_50),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_CSR_I, "ether1_sgmii_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_ACLK_I, "ether1_sgmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_300),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_PHY_PCLK_I, "ether1_sgmii_phy_pclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_REF_25_I, "ether1_sgmii_ref_25_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_OSC),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_CAN0, "main_icg_en_can0", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_CAN1, "main_icg_en_can1", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_DMAC_8CH, "main_icg_en_dmac_8ch", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_RTC_SCAN, "main_icg_en_rtc_scan", CLK_IS_CRITICAL,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_ADC0, "main_icg_en_adc0", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_ADC1, "main_icg_en_adc1", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_GMAC2, "main_icg_en_gmac2", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_GMAC3, "main_icg_en_gmac3", 0,
+ JHB100_PER2CLK_100),
+};
+
+static int jhb100_per2crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_PER2CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_PER2CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_PER2CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_per2crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_per2crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_per2crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_per2crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_PER2CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_PER2CLK_600)
+ parents[i].fw_name = "per2_600";
+ else if (pidx == JHB100_PER2CLK_400)
+ parents[i].fw_name = "per2_400";
+ else if (pidx == JHB100_PER2CLK_125)
+ parents[i].fw_name = "per2_125";
+ else if (pidx == JHB100_PER2CLK_GMAC2_RGMII_RX)
+ parents[i].fw_name = "per2_gmac2_rgmii_rx";
+ else if (pidx == JHB100_PER2CLK_GMAC2_RMII_REF)
+ parents[i].fw_name = "per2_gmac2_rmii_ref";
+ else if (pidx == JHB100_PER2CLK_GMAC3_SGMII_TX)
+ parents[i].fw_name = "per2_gmac3_sgmii_tx";
+ else if (pidx == JHB100_PER2CLK_GMAC3_SGMII_RX)
+ parents[i].fw_name = "per2_gmac3_sgmii_rx";
+ else if (pidx == JHB100_PER2CLK_OSC)
+ parents[i].fw_name = "osc";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-per2", 0);
+}
+
+static const struct of_device_id jhb100_per2crg_match[] = {
+ { .compatible = "starfive,jhb100-per2crg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per2crg_match);
+
+static struct platform_driver jhb100_per2crg_driver = {
+ .probe = jhb100_per2crg_probe,
+ .driver = {
+ .name = "clk-starfive-jhb100-per2",
+ .of_match_table = jhb100_per2crg_match,
+ },
+};
+module_platform_driver(jhb100_per2crg_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 Peripheral-2 Clock Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related
* Re: [PATCH net-next 05/11] net: macb: allocate tieoff descriptor once across device lifetime
From: Nicolai Buchwitz @ 2026-04-02 11:14 UTC (permalink / raw)
To: Théo Lebrun
Cc: Nicolas Ferre, Claudiu Beznea, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Richard Cochran,
Russell King, Paolo Valerio, Conor Dooley, Vladimir Kondratiev,
Gregory CLEMENT, Benoît Monin, Tawfik Bayouk,
Thomas Petazzoni, Maxime Chevallier, netdev, linux-kernel
In-Reply-To: <20260401-macb-context-v1-5-9590c5ab7272@bootlin.com>
On 1.4.2026 18:39, Théo Lebrun wrote:
> The tieoff descriptor is a RX DMA descriptor ring of size one. It gets
> configured onto queues for Wake-on-LAN during system-wide suspend when
> hardware does not support disabling individual queues
> (MACB_CAPS_QUEUE_DISABLE).
>
> MACB/GEM driver allocates it alongside the main RX ring
> inside macb_alloc_consistent() at open. Free is done by
> macb_free_consistent() at close.
>
> Change to allocate once at probe and free on probe failure or device
> removal. This makes the tieoff descriptor lifetime much longer,
> avoiding repeating coherent buffer allocation on each open/close cycle.
>
> Main benefit: we dissociate its lifetime from the main ring's lifetime.
> That way there is less work to be doing on resources (re)alloc. This
> currently happens on close/open, but will soon also happen on context
> swap operations (set_ringparam, change_mtu, set_channels, etc).
>
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
> drivers/net/ethernet/cadence/macb_main.c | 70
> ++++++++++++++++----------------
> [...]
>
> +static int macb_alloc_tieoff(struct macb *bp)
> +{
> + /* Tieoff is a workaround in case HW cannot disable queues, for PM.
> */
> + if (bp->caps & MACB_CAPS_QUEUE_DISABLE)
> + return 0;
> +
> + bp->rx_ring_tieoff = dma_alloc_coherent(&bp->pdev->dev,
> + macb_dma_desc_get_size(bp),
> + &bp->rx_ring_tieoff_dma,
> + GFP_KERNEL);
> + if (!bp->rx_ring_tieoff)
> + return -ENOMEM;
> +
> + return 0;
> +}
The old macb_init_tieoff() that wrote WRAP+USED into the
descriptor is deleted but its work is not replicated here.
dma_alloc_coherent zeroes the memory, so RX_USED=0 and the
hardware will treat it as a valid receive buffer pointing to
DMA address 0 during suspend.
Shouldn't this have a macb_set_addr() + ctrl=0 after the
allocation?
> [...]
Thanks
Nicolai
^ permalink raw reply
* Re: [PATCH net-next v7] selftests: net: add tests for PPP
From: Paolo Abeni @ 2026-04-02 11:17 UTC (permalink / raw)
To: Qingfang Deng
Cc: Jakub Kicinski, Dianne Skoll, Shuah Khan, David S. Miller,
Eric Dumazet, Simon Horman, Felix Maurer,
Sebastian Andrzej Siewior, Matthieu Baerts (NGI0), linux-kernel,
linux-kselftest, linux-ppp, netdev, Paul Mackerras, Jaco Kroon
In-Reply-To: <CALW65ja1FV-OcqSazgKZhQhKf3oqr=kcGxyGkOGbhurGLOJ0-w@mail.gmail.com>
On 4/2/26 12:13 PM, Qingfang Deng wrote:
> On Thu, Apr 2, 2026 at 5:48 PM Paolo Abeni <pabeni@redhat.com> wrote:
>> Note that similar failures in the past in other test-cases were usually
>> due to timing issues. i.e. the pppoe-server starts in background too
>> late for the client.
>
> I don't think it is a timing issue, otherwise the PADI negotiation
> won't succeed. The "updetach" option on the client side also make it
> wait for the negotiation.
> It's likely that the pppd instance spawned by pppoe-server fails to
> find the "rp-pppoe.so" plugin, so the connection fails when handing
> off the session from pppoe-server to pppd. Note the naming difference:
> the client loads "pppoe.so", while the server loads "rp-pppoe.so" by
> default.
>
> What distro do you run CI tests on? On Ubuntu 24.04, "rp-pppoe.so" is
> a symlink to "pppoe.so" in apt package "ppp". Maybe an additional
> package is required for the distro you use, or I may work around that
> by manually creating the symlink.
It's fedora 43 with ppp and pppoe installed.
ppp provides pppoe.so, and AFAICS nothink provides rp-pppoe.so, and the
pppoe-server is looking for a non existing /etc/ppp/plugins/rp-pppoe.so
plugin.
Before I mess with the nipa testbed, could you please double check that
ln -n /usr/lib64/pppd/2.5.1/pppoe.so /etc/ppp/plugins/rp-pppoe.so
should solve?
Thanks,
Paolo
^ permalink raw reply
* Re: [net-next,v4,4/4] octeontx2-pf: cn20k: Use unified Halo context
From: Paolo Abeni @ 2026-04-02 11:20 UTC (permalink / raw)
To: sbhatta
Cc: pabeni, linux-kernel, lcherian, andrew+netdev, davem, kuba,
gakula, edumazet, sgoutham, bbhushan2, netdev
In-Reply-To: <1774940919-1599-5-git-send-email-sbhatta@marvell.com>
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
octeontx2-pf: cn20k: Use unified Halo context
This commit replaces the separate aura and pool contexts with the unified
Halo context available in CN20K hardware for managing network device pools
and buffer allocation.
> diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c b/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
> --- a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
[ ... ]
> @@ -516,85 +507,8 @@ int cn20k_tc_alloc_entry(struct otx2_nic *nic,
>
> return 0;
> }
> -
> -static int cn20k_aura_aq_init(struct otx2_nic *pfvf, int aura_id,
> - int pool_id, int numptrs)
> -{
> - struct npa_cn20k_aq_enq_req *aq;
> - struct otx2_pool *pool;
> - u8 bpid_idx;
> - int err;
> -
> - pool = &pfvf->qset.pool[pool_id];
> -
> - /* Allocate memory for HW to update Aura count.
> - * Alloc one cache line, so that it fits all FC_STYPE modes.
> - */
> - if (!pool->fc_addr) {
> - err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN);
> - if (err)
> - return err;
> - }
> -
> - /* Initialize this aura's context via AF */
> - aq = otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox);
> - if (!aq) {
> - /* Shared mbox memory buffer is full, flush it and retry */
> - err = otx2_sync_mbox_msg(&pfvf->mbox);
> - if (err)
> - return err;
> - aq = otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox);
> - if (!aq)
> - return -ENOMEM;
> - }
> -
> - aq->aura_id = aura_id;
> -
> - /* Will be filled by AF with correct pool context address */
> - aq->aura.pool_addr = pool_id;
> - aq->aura.pool_caching = 1;
> - aq->aura.shift = ilog2(numptrs) - 8;
> - aq->aura.count = numptrs;
> - aq->aura.limit = numptrs;
> - aq->aura.avg_level = 255;
> - aq->aura.ena = 1;
> - aq->aura.fc_ena = 1;
> - aq->aura.fc_addr = pool->fc_addr->iova;
> - aq->aura.fc_hyst_bits = 0; /* Store count on all updates */
>
> - /* Enable backpressure for RQ aura */
> - if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) {
> - aq->aura.bp_ena = 0;
> - /* If NIX1 LF is attached then specify NIX1_RX.
> - *
> - * Below NPA_AURA_S[BP_ENA] is set according to the
> - * NPA_BPINTF_E enumeration given as:
> - * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so
> - * NIX0_RX is 0x0 + 0*0x1 = 0
> - * NIX1_RX is 0x0 + 1*0x1 = 1
> - * But in HRM it is given that
> - * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to
> - * NIX-RX based on [BP] level. One bit per NIX-RX; index
> - * enumerated by NPA_BPINTF_E."
> - */
> - if (pfvf->nix_blkaddr == BLKADDR_NIX1)
> - aq->aura.bp_ena = 1;
> -
> - bpid_idx = cn20k_aura_bpid_idx(pfvf, aura_id);
> - aq->aura.bpid = pfvf->bpid[bpid_idx];
> -
> - /* Set backpressure level for RQ's Aura */
> - aq->aura.bp = RQ_BP_LVL_AURA;
> - }
> -
> - /* Fill AQ info */
> - aq->ctype = NPA_AQ_CTYPE_AURA;
> - aq->op = NPA_AQ_INSTOP_INIT;
> -
> - return 0;
> -}
> -
> -static int cn20k_pool_aq_init(struct otx2_nic *pfvf, u16 pool_id,
> +static int cn20k_halo_aq_init(struct otx2_nic *pfvf, u16 pool_id,
> int stack_pages, int numptrs, int buf_size,
> int type)
> {
> @@ -610,36 +524,57 @@ struct page_pool_params pp_params = { 0 };
> if (err)
> return err;
>
> + /* Allocate memory for HW to update Aura count.
> + * Alloc one cache line, so that it fits all FC_STYPE modes.
> + */
> + if (!pool->fc_addr) {
> + err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN);
> + if (err) {
> + qmem_free(pfvf->dev, pool->stack);
> + return err;
> + }
> + }
> +
> pool->rbsize = buf_size;
>
> - /* Initialize this pool's context via AF */
> + /* Initialize this aura's context via AF */
> aq = otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox);
> if (!aq) {
> /* Shared mbox memory buffer is full, flush it and retry */
> err = otx2_sync_mbox_msg(&pfvf->mbox);
> - if (err) {
> - qmem_free(pfvf->dev, pool->stack);
> - return err;
> - }
> + if (err)
> + goto free_mem;
> aq = otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox);
> if (!aq) {
> - qmem_free(pfvf->dev, pool->stack);
> - return -ENOMEM;
> + err = -ENOMEM;
> + goto free_mem;
> }
> }
>
> aq->aura_id = pool_id;
> - aq->pool.stack_base = pool->stack->iova;
> - aq->pool.stack_caching = 1;
> - aq->pool.ena = 1;
> - aq->pool.buf_size = buf_size / 128;
> - aq->pool.stack_max_pages = stack_pages;
> - aq->pool.shift = ilog2(numptrs) - 8;
> - aq->pool.ptr_start = 0;
> - aq->pool.ptr_end = ~0ULL;
>
> + aq->halo.stack_base = pool->stack->iova;
> + aq->halo.stack_caching = 1;
> + aq->halo.ena = 1;
> + aq->halo.buf_size = buf_size / 128;
> + aq->halo.stack_max_pages = stack_pages;
> + aq->halo.shift = ilog2(numptrs) - 8;
> + aq->halo.ptr_start = 0;
> + aq->halo.ptr_end = ~0ULL;
> +
> + aq->halo.avg_level = 255;
> + aq->halo.fc_ena = 1;
> + aq->halo.fc_addr = pool->fc_addr->iova;
> + aq->halo.fc_hyst_bits = 0; /* Store count on all updates */
> +
> + if (pfvf->npa_dpc_valid) {
> + aq->halo.op_dpc_ena = 1;
> + aq->halo.op_dpc_set = pfvf->npa_dpc;
> + }
> + aq->halo.unified_ctx = 1;
^^^^
Does this code properly configure backpressure for receive queues? The old
cn20k_aura_aq_init configured NPA-level backpressure by setting bp_ena,
bpid, and bp fields in the aura context. This caused the hardware to signal
backpressure to NIX-RX when receive buffers filled to 85% (RQ_BP_LVL_AURA):
/* Enable backpressure for RQ aura */
if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) {
aq->aura.bp_ena = 0;
if (pfvf->nix_blkaddr == BLKADDR_NIX1)
aq->aura.bp_ena = 1;
bpid_idx = cn20k_aura_bpid_idx(pfvf, aura_id);
aq->aura.bpid = pfvf->bpid[bpid_idx];
/* Set backpressure level for RQ's Aura */
aq->aura.bp = RQ_BP_LVL_AURA;
}
The new cn20k_halo_aq_init does not set the equivalent Halo context fields
(bp_ena_0, bpid_0, bp_0). Looking at struct npa_cn20k_halo_s in the AF
headers, these fields exist in the Halo context.
The AF side rvu_npa_aq_enq_inst() does not auto-configure backpressure
during INIT operations. The AF teardown code rvu_npa_halo_hwctx_disable()
explicitly clears bp_ena_0 through bp_ena_7, confirming these fields are
expected to be set during initialization.
Without NPA-level backpressure configuration, wouldn't CN20K devices fail
to trigger backpressure when aura buffers fill up, leading to packet drops
under heavy traffic load?
>
> /* Fill AQ info */
> - aq->ctype = NPA_AQ_CTYPE_POOL;
> + aq->ctype = NPA_AQ_CTYPE_HALO;
> aq->op = NPA_AQ_INSTOP_INIT;
[ ... ]
> diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
> --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
> @@ -1651,6 +1651,9 @@ int otx2_init_hw_resources(struct otx2_nic *pf)
> if (!is_otx2_lbkvf(pf->pdev))
> otx2_nix_config_bp(pf, true);
>
> + if (is_cn20k(pf->pdev))
> + cn20k_npa_alloc_dpc(pf);
> +
> /* Init Auras and pools used by NIX RQ, for free buffer ptrs */
> err = otx2_rq_aura_pool_init(pf);
> if (err) {
> @@ -1726,6 +1729,8 @@
> otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
> otx2_aura_pool_free(pf);
> err_free_nix_lf:
> + if (pf->npa_dpc_valid)
> + cn20k_npa_free_dpc(pf);
Is there a potential double-free of the NPA DPC counter via the
rvu_rep_rsrc_init error path?
cn20k_npa_free_dpc() does not clear nic->npa_dpc_valid after successfully
freeing the DPC counter. If otx2_init_hw_resources() fails after
cn20k_npa_alloc_dpc() succeeds (e.g., otx2_rq_aura_pool_init() returns an
error), the error cleanup at err_free_nix_lf calls cn20k_npa_free_dpc(pf)
which frees the counter but leaves npa_dpc_valid=true.
The caller rvu_rep_rsrc_init() then calls otx2_free_hw_resources(priv) at
its err_free_rsrc label:
rvu_rep_rsrc_init()
otx2_init_hw_resources(priv)
cn20k_npa_alloc_dpc(pf) [succeeds]
otx2_rq_aura_pool_init(pf) [fails]
goto err_free_nix_lf
cn20k_npa_free_dpc(pf) [frees counter, npa_dpc_valid still true]
goto err_free_rsrc
otx2_free_hw_resources(priv)
cn20k_npa_free_dpc(pf) [frees same counter again]
Looking at cn20k_npa_free_dpc() in cn20k.c:
int cn20k_npa_free_dpc(struct otx2_nic *nic)
{
struct npa_cn20k_dpc_free_req *req;
int err;
if (!nic->npa_dpc_valid)
return 0;
mutex_lock(&nic->mbox.lock);
req = otx2_mbox_alloc_msg_npa_cn20k_dpc_free(&nic->mbox);
if (!req) {
mutex_unlock(&nic->mbox.lock);
return -ENOMEM;
}
req->cntr_id = nic->npa_dpc;
err = otx2_sync_mbox_msg(&nic->mbox);
mutex_unlock(&nic->mbox.lock);
return err;
}
Since npa_dpc_valid is still true, the second call passes the guard check
and sends another mbox message to free the same counter ID. Shouldn't
cn20k_npa_free_dpc() clear nic->npa_dpc_valid after the successful
otx2_sync_mbox_msg() call to prevent this double-free?
> mutex_lock(&mbox->lock);
> free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
> if (free_req) {
[ ... ]
^ permalink raw reply
* Re: [PATCH net-next 06/11] net: macb: introduce macb_context struct for buffer management
From: Nicolai Buchwitz @ 2026-04-02 11:22 UTC (permalink / raw)
To: Théo Lebrun
Cc: Nicolas Ferre, Claudiu Beznea, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Richard Cochran,
Russell King, Paolo Valerio, Conor Dooley, Vladimir Kondratiev,
Gregory CLEMENT, Benoît Monin, Tawfik Bayouk,
Thomas Petazzoni, Maxime Chevallier, netdev, linux-kernel
In-Reply-To: <20260401-macb-context-v1-6-9590c5ab7272@bootlin.com>
On 1.4.2026 18:39, Théo Lebrun wrote:
> Whenever an operation requires buffer realloc, we close the interface,
> update parameters and reopen. To improve reliability under memory
> pressure, we should rather alloc new buffers, reconfigure HW and free
> old buffers. This requires MACB to support having multiple "contexts"
> in parallel.
>
> Introduce this concept by adding the macb_context struct, which owns
> all
> queue buffers and the parameters associated. We do not yet support
> multiple contexts in parallel, because all functions access bp->ctx
> (the currently active context) directly.
>
> Steps:
>
> - Introduce `struct macb_context` and its children `struct macb_rxq`
> and `struct macb_txq`. Context fields are stolen from `struct macb`
> and rxq/txq fields are from `struct macb_queue`.
>
> Making it two separate structs per queue simplifies accesses: we
> grab
> a txq/rxq local variable and access fields like txq->head instead of
> queue->tx_head. It also anecdotally improves data locality.
>
> - macb_init_dflt() does not set bp->ctx->{rx,tx}_ring_size to default
> values as ctx is not allocated yet. Instead, introduce
> bp->configured_{rx,tx}_ring_size which get updated on user requests.
>
> - macb_open() starts by allocating bp->ctx. It gets freed in the
> open error codepath or by macb_close().
>
> - Guided by compile errors, update all codepaths. Most diff is
> changing
> `queue->tx_*` to `txq->*` and `queue->rx_*` to `rxq->*`, with a new
> local variable. Also rx_buffer_size / rx_ring_size / tx_ring_size
> move from bp to bp->ctx.
>
> Introduce two helpers macb_tx|rx() functions to convert macb_queue
> pointers.
>
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
> drivers/net/ethernet/cadence/macb.h | 49 ++--
> drivers/net/ethernet/cadence/macb_main.c | 442
> ++++++++++++++++++-------------
> 2 files changed, 296 insertions(+), 195 deletions(-)
>
> [...]
> diff --git a/drivers/net/ethernet/cadence/macb_main.c
> b/drivers/net/ethernet/cadence/macb_main.c
> index d5023fdc0756..0f63d9b89c11 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> [...]
> @@ -3596,14 +3677,15 @@ static void macb_get_regs(struct net_device
> *netdev, struct ethtool_regs *regs,
> void *p)
> {
> struct macb *bp = netdev_priv(netdev);
> + struct macb_txq *txq = &bp->ctx->txq[0];
bp->ctx is NULL when the interface is down. This will crash if
ethtool -d is called while the interface is not running. Same
issue below in macb_get_ringparam().
> unsigned int tail, head;
> u32 *regs_buff = p;
>
> regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
> | MACB_GREGS_VERSION;
>
> - tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
> - head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
> + tail = macb_tx_ring_wrap(bp, txq->tail);
> + head = macb_tx_ring_wrap(bp, txq->head);
>
> regs_buff[0] = macb_readl(bp, NCR);
> regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
> @@ -3682,8 +3764,8 @@ static void macb_get_ringparam(struct net_device
> *netdev,
> ring->rx_max_pending = MAX_RX_RING_SIZE;
> ring->tx_max_pending = MAX_TX_RING_SIZE;
>
> - ring->rx_pending = bp->rx_ring_size;
> - ring->tx_pending = bp->tx_ring_size;
> + ring->rx_pending = bp->ctx->rx_ring_size;
> + ring->tx_pending = bp->ctx->tx_ring_size;
Same NULL ctx issue as above. This one could just read from
bp->configured_{rx,tx}_ring_size instead.
> [...]
Thanks
Nicolai
^ permalink raw reply
* Re: [PATCH v2] xfrm: delay dev_put in xfrm_input to after transport reinject
From: Qi Tang @ 2026-04-02 11:26 UTC (permalink / raw)
To: Florian Westphal, Steffen Klassert
Cc: Herbert Xu, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Simon Horman, David Ahern, netdev, stable, Qi Tang
In-Reply-To: <ac5K7S3dBsINFafg@strlen.de>
On Thu, Apr 3, 2026, Florian Westphal wrote:
> I'd suggest do drop the refcount after NF_HOOK, i.e. something like:
>
> dev = skb->dev;
>
> NF_HOOK(NFPROTO_IPV4, NF_INET_PRE_ROUTING,
> ...
> if (async)
> dev_put(dev);
Much cleaner. The reinject callback only uses cb->net (saved at
queue time) and dst_input, neither needs skb->dev, so the ref
only has to survive through the NF_HOOK call.
Will send v3 with this approach.
Qi Tang
^ permalink raw reply
* [PATCH v1 00/22] Add basic clocks and resets for JHB100 SoC
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
The JHB100 SoC includes CRG (Clock and Reset Generator) for multiple
subsystems:
The JHB100 SoC is divided into multiple subsystems, and basically
each subsystem includes a CRG(Clock and Reset Generator):
- sys0crg/sys1crg/sys2crg/
- per0crg/per1crg/per2crg/per3crg/
- voutcrg
- vcecrg
- gpu0crg/gpu1crg
- cpucrg
- usbcrg
- host0crg/host1crg
- pcierpcrg
- husb0crg/husb1crg
- husbcmncrg
- husbd0crg/husbd1crg
- npucrg
In the current series, we will only add the following CRG:
- sys0crg/sys1crg/sys2crg/
- per0crg/per1crg/per2crg/per3crg/
The remaining CRG will be implemented in future series.
This series depends on the series:
https://lore.kernel.org/all/20260402084019.440708-1-changhuang.liang@starfivetech.com/
and it has been tested on the StarFive JHB100 EVB-1.
Changhuang Liang (18):
dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset
generator
clk: starfive: Add JHB100 System-0 clock generator driver
dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset
generator
clk: starfive: Add JHB100 System-1 clock generator driver
dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset
generator
clk: starfive: Add JHB100 System-2 clock generator driver
dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset
generator
clk: starfive: Introduce inverter and divider
clk: starfive: Expand the storage of clock parent index
clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver
dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset
generator
clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver
dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset
generator
clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver
dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset
generator
clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver
reset: starfive: Add StarFive JHB100 reset driver
riscv: dts: starfive: jhb100: Add clocks and resets nodes
Sia Jee Heng (4):
reset: starfive: Rename file name "jh71x0" to "common"
reset: starfive: Convert the word "jh71x0" to "starfive"
clk: starfive: Rename file name "jh71x0" to "common"
clk: starfive: Convert the word "jh71x0" to "starfive"
.../clock/starfive,jhb100-per0crg.yaml | 70 ++
.../clock/starfive,jhb100-per1crg.yaml | 70 ++
.../clock/starfive,jhb100-per2crg.yaml | 79 +++
.../clock/starfive,jhb100-per3crg.yaml | 78 +++
.../clock/starfive,jhb100-sys0crg.yaml | 63 ++
.../clock/starfive,jhb100-sys1crg.yaml | 71 ++
.../clock/starfive,jhb100-sys2crg.yaml | 64 ++
MAINTAINERS | 13 +
arch/riscv/boot/dts/starfive/jhb100.dtsi | 198 +++++-
drivers/clk/starfive/Kconfig | 67 +-
drivers/clk/starfive/Makefile | 10 +-
drivers/clk/starfive/clk-starfive-common.c | 351 ++++++++++
drivers/clk/starfive/clk-starfive-common.h | 135 ++++
.../clk/starfive/clk-starfive-jh7100-audio.c | 127 ++--
drivers/clk/starfive/clk-starfive-jh7100.c | 503 +++++++-------
.../clk/starfive/clk-starfive-jh7110-aon.c | 62 +-
.../clk/starfive/clk-starfive-jh7110-isp.c | 72 +-
.../clk/starfive/clk-starfive-jh7110-stg.c | 94 +--
.../clk/starfive/clk-starfive-jh7110-sys.c | 525 +++++++-------
.../clk/starfive/clk-starfive-jh7110-vout.c | 74 +-
drivers/clk/starfive/clk-starfive-jh7110.h | 4 +-
drivers/clk/starfive/clk-starfive-jh71x0.c | 339 ---------
drivers/clk/starfive/clk-starfive-jh71x0.h | 127 ----
.../clk/starfive/clk-starfive-jhb100-per0.c | 655 ++++++++++++++++++
.../clk/starfive/clk-starfive-jhb100-per1.c | 204 ++++++
.../clk/starfive/clk-starfive-jhb100-per2.c | 232 +++++++
.../clk/starfive/clk-starfive-jhb100-per3.c | 189 +++++
.../clk/starfive/clk-starfive-jhb100-sys0.c | 253 +++++++
.../clk/starfive/clk-starfive-jhb100-sys1.c | 157 +++++
.../clk/starfive/clk-starfive-jhb100-sys2.c | 178 +++++
drivers/clk/starfive/clk-starfive-jhb100.h | 11 +
drivers/reset/starfive/Kconfig | 15 +-
drivers/reset/starfive/Makefile | 3 +-
...rfive-jh71x0.c => reset-starfive-common.c} | 68 +-
.../reset/starfive/reset-starfive-common.h | 14 +
.../reset/starfive/reset-starfive-jh7100.c | 4 +-
.../reset/starfive/reset-starfive-jh7110.c | 8 +-
.../reset/starfive/reset-starfive-jh71x0.h | 14 -
.../reset/starfive/reset-starfive-jhb100.c | 121 ++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 542 +++++++++++++++
.../dt-bindings/reset/starfive,jhb100-crg.h | 193 ++++++
...rfive-jh71x0.h => reset-starfive-common.h} | 10 +-
42 files changed, 4805 insertions(+), 1262 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per2crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml
create mode 100644 drivers/clk/starfive/clk-starfive-common.c
create mode 100644 drivers/clk/starfive/clk-starfive-common.h
delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per0.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per1.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per2.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per3.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys1.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys2.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100.h
rename drivers/reset/starfive/{reset-starfive-jh71x0.c => reset-starfive-common.c} (55%)
create mode 100644 drivers/reset/starfive/reset-starfive-common.h
delete mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
create mode 100644 drivers/reset/starfive/reset-starfive-jhb100.c
create mode 100644 include/dt-bindings/clock/starfive,jhb100-crg.h
create mode 100644 include/dt-bindings/reset/starfive,jhb100-crg.h
rename include/soc/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (50%)
--
2.25.1
^ permalink raw reply
* Re: [PATCH net-next 10/11] net: macb: use context swapping in .set_ringparam()
From: Nicolai Buchwitz @ 2026-04-02 11:29 UTC (permalink / raw)
To: Théo Lebrun
Cc: Nicolas Ferre, Claudiu Beznea, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Richard Cochran,
Russell King, Paolo Valerio, Conor Dooley, Vladimir Kondratiev,
Gregory CLEMENT, Benoît Monin, Tawfik Bayouk,
Thomas Petazzoni, Maxime Chevallier, netdev, linux-kernel
In-Reply-To: <20260401-macb-context-v1-10-9590c5ab7272@bootlin.com>
On 1.4.2026 18:39, Théo Lebrun wrote:
> ethtool_ops.set_ringparam() is implemented using the primitive close /
> update ring size / reopen sequence. Under memory pressure this does not
> fly: we free our buffers at close and cannot reallocate new ones at
> open. Also, it triggers a slow PHY reinit.
>
> Instead, exploit the new context mechanism and improve our sequence to:
> - allocate a new context (including buffers) first
> - if it fails, early return without any impact to the interface
> - stop interface
> - update global state (bp, netdev, etc)
> - pass buffer pointers to the hardware
> - start interface
> - free old context.
>
> The HW disable sequence is inspired by macb_reset_hw() but avoids
> (1) setting NCR bit CLRSTAT and (2) clearing register PBUFRXCUT.
>
> The HW re-enable sequence is inspired by macb_mac_link_up(), skipping
> over register writes which would be redundant (because values have not
> changed).
>
> The generic context swapping parts are isolated into helper functions
> macb_context_swap_start|end(), reusable by other operations
> (change_mtu,
> set_channels, etc).
>
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
> drivers/net/ethernet/cadence/macb_main.c | 89
> +++++++++++++++++++++++++++++---
> 1 file changed, 82 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb_main.c
> b/drivers/net/ethernet/cadence/macb_main.c
> index 42b19b969f3e..543356554c11 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -2905,6 +2905,76 @@ static struct macb_context
> *macb_context_alloc(struct macb *bp,
> return ctx;
> }
>
> +static void macb_context_swap_start(struct macb *bp)
> +{
> + struct macb_queue *queue;
> + unsigned int q;
> + u32 ctrl;
> +
> + /* Disable software Tx, disable HW Tx/Rx and disable NAPI. */
> +
> + netif_tx_disable(bp->netdev);
> +
> + ctrl = macb_readl(bp, NCR);
> + macb_writel(bp, NCR, ctrl & ~(MACB_BIT(RE) | MACB_BIT(TE)));
> +
> + macb_writel(bp, TSR, -1);
> + macb_writel(bp, RSR, -1);
> +
> + for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
> + queue_writel(queue, IDR, -1);
> + queue_readl(queue, ISR);
> + if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> + queue_writel(queue, ISR, -1);
> + }
> +
> + for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
> + napi_disable(&queue->napi_rx);
> + napi_disable(&queue->napi_tx);
> + }
tx_error_task, hresp_err_bh_work, and tx_lpi_work all dereference
bp->ctx and could race with the pointer swap in swap_end.
macb_close() cancels at least tx_lpi_work here. Should these be
flushed too?
> +}
> +
> +static void macb_context_swap_end(struct macb *bp,
> + struct macb_context *new_ctx)
> +{
> + struct macb_context *old_ctx;
> + struct macb_queue *queue;
> + unsigned int q;
> + u32 ctrl;
> +
> + /* Swap contexts & give buffer pointers to HW. */
> +
> + old_ctx = bp->ctx;
> + bp->ctx = new_ctx;
> + macb_init_buffers(bp);
> +
> + /* Start NAPI, HW Tx/Rx and software Tx. */
> +
> + for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
> + napi_enable(&queue->napi_rx);
> + napi_enable(&queue->napi_tx);
> + }
> +
> + if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
> + for (q = 0, queue = bp->queues; q < bp->num_queues;
> + ++q, ++queue) {
> + queue_writel(queue, IER,
> + bp->rx_intr_mask |
> + MACB_TX_INT_FLAGS |
> + MACB_BIT(HRESP));
> + }
> + }
> +
> + ctrl = macb_readl(bp, NCR);
> + macb_writel(bp, NCR, ctrl | MACB_BIT(RE) | MACB_BIT(TE));
> +
> + netif_tx_start_all_queues(bp->netdev);
> +
> + /* Free old context. */
> +
> + macb_free_consistent(old_ctx);
1. kfree(old_ctx) is missing. The context struct itself leaks on
every swap.
2. macb_close() calls netdev_tx_reset_queue() for each queue.
Shouldn't the swap do the same? BQL accounting will be stale
after switching to a fresh context.
3. macb_configure_dma() is not called after the swap. For
set_ringparam this is probably fine since rx_buffer_size
does not change, but this becomes a problem in patch 11.
> [...]
^ permalink raw reply
* [PATCH v1 03/22] clk: starfive: Rename file name "jh71x0" to "common"
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
StarFive JHB100 shares a similar clock and reset design with JH7110.
To facilitate the reuse of the file and its functionalities, files
containing the "jh71x0" naming convention are renamed to use the
"common" wording.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 ++++----
drivers/clk/starfive/Makefile | 2 +-
.../{clk-starfive-jh71x0.c => clk-starfive-common.c} | 4 ++--
.../{clk-starfive-jh71x0.h => clk-starfive-common.h} | 4 ++--
drivers/clk/starfive/clk-starfive-jh7100-audio.c | 2 +-
drivers/clk/starfive/clk-starfive-jh7100.c | 2 +-
drivers/clk/starfive/clk-starfive-jh7110.h | 2 +-
7 files changed, 12 insertions(+), 12 deletions(-)
rename drivers/clk/starfive/{clk-starfive-jh71x0.c => clk-starfive-common.c} (99%)
rename drivers/clk/starfive/{clk-starfive-jh71x0.h => clk-starfive-common.h} (98%)
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index bd29358ffeec..ff8eace36e64 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -1,12 +1,12 @@
# SPDX-License-Identifier: GPL-2.0
-config CLK_STARFIVE_JH71X0
+config CLK_STARFIVE_COMMON
bool
config CLK_STARFIVE_JH7100
bool "StarFive JH7100 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
- select CLK_STARFIVE_JH71X0
+ select CLK_STARFIVE_COMMON
default ARCH_STARFIVE
help
Say yes here to support the clock controller on the StarFive JH7100
@@ -15,7 +15,7 @@ config CLK_STARFIVE_JH7100
config CLK_STARFIVE_JH7100_AUDIO
tristate "StarFive JH7100 audio clock support"
depends on CLK_STARFIVE_JH7100
- select CLK_STARFIVE_JH71X0
+ select CLK_STARFIVE_COMMON
default m if ARCH_STARFIVE
help
Say Y or M here to support the audio clocks on the StarFive JH7100
@@ -33,7 +33,7 @@ config CLK_STARFIVE_JH7110_SYS
bool "StarFive JH7110 system clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
select AUXILIARY_BUS
- select CLK_STARFIVE_JH71X0
+ select CLK_STARFIVE_COMMON
select RESET_STARFIVE_JH7110 if RESET_CONTROLLER
select CLK_STARFIVE_JH7110_PLL
default ARCH_STARFIVE
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 199ac0f37a2f..012f7ee83f8e 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
+obj-$(CONFIG_CLK_STARFIVE_COMMON) += clk-starfive-common.o
obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-common.c
similarity index 99%
rename from drivers/clk/starfive/clk-starfive-jh71x0.c
rename to drivers/clk/starfive/clk-starfive-common.c
index 80e9157347eb..4aecb65e9fd7 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.c
+++ b/drivers/clk/starfive/clk-starfive-common.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * StarFive JH71X0 Clock Generator Driver
+ * StarFive Clock Generator Driver
*
* Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
*/
@@ -10,7 +10,7 @@
#include <linux/device.h>
#include <linux/io.h>
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
{
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-common.h
similarity index 98%
rename from drivers/clk/starfive/clk-starfive-jh71x0.h
rename to drivers/clk/starfive/clk-starfive-common.h
index 9d5dec1d5cd1..f634c62c196a 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.h
+++ b/drivers/clk/starfive/clk-starfive-common.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CLK_STARFIVE_JH71X0_H
-#define __CLK_STARFIVE_JH71X0_H
+#ifndef __CLK_STARFIVE_COMMON_H
+#define __CLK_STARFIVE_COMMON_H
#include <linux/bits.h>
#include <linux/clk-provider.h>
diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
index 7de23f6749aa..4505d309f664 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -15,7 +15,7 @@
#include <dt-bindings/clock/starfive-jh7100-audio.h>
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
/* external clocks */
#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 03f6f26a15d8..bf82190b9c57 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -15,7 +15,7 @@
#include <dt-bindings/clock/starfive-jh7100.h>
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
/* external clocks */
#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h
index 0659adae4d76..6b1bdf860f00 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110.h
+++ b/drivers/clk/starfive/clk-starfive-jh7110.h
@@ -2,7 +2,7 @@
#ifndef __CLK_STARFIVE_JH7110_H
#define __CLK_STARFIVE_JH7110_H
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
/* top clocks of ISP/VOUT domain from JH7110 SYSCRG */
struct jh7110_top_sysclk {
--
2.25.1
^ permalink raw reply related
* Re: [PATCH net-next 11/11] net: macb: use context swapping in .ndo_change_mtu()
From: Nicolai Buchwitz @ 2026-04-02 11:30 UTC (permalink / raw)
To: Théo Lebrun
Cc: Nicolas Ferre, Claudiu Beznea, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Richard Cochran,
Russell King, Paolo Valerio, Conor Dooley, Vladimir Kondratiev,
Gregory CLEMENT, Benoît Monin, Tawfik Bayouk,
Thomas Petazzoni, Maxime Chevallier, netdev, linux-kernel
In-Reply-To: <20260401-macb-context-v1-11-9590c5ab7272@bootlin.com>
On 1.4.2026 18:39, Théo Lebrun wrote:
> Use newly introduced context buffer management to implement
> .ndo_change_mtu() as a context swap: allocate new context ->
> reconfigure HW -> free old context.
>
> This resists memory pressure well by failing without closing the
> interface and it is much faster by avoiding PHY reinit.
>
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
> drivers/net/ethernet/cadence/macb_main.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb_main.c
> b/drivers/net/ethernet/cadence/macb_main.c
> index 543356554c11..e10791bf1f4d 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -3438,11 +3438,25 @@ static int macb_close(struct net_device
> *netdev)
>
> static int macb_change_mtu(struct net_device *netdev, int new_mtu)
> {
> - if (netif_running(netdev))
> - return -EBUSY;
> + struct macb *bp = netdev_priv(netdev);
> + bool running = netif_running(netdev);
> + struct macb_context *new_ctx;
> +
> + if (running) {
> + new_ctx = macb_context_alloc(bp, new_mtu,
> + bp->configured_rx_ring_size,
> + bp->configured_tx_ring_size);
> + if (IS_ERR(new_ctx))
> + return PTR_ERR(new_ctx);
> +
> + macb_context_swap_start(bp);
> + }
>
> WRITE_ONCE(netdev->mtu, new_mtu);
>
> + if (running)
> + macb_context_swap_end(bp, new_ctx);
Same issues from patch 10 apply here, plus:
macb_context_swap_end() never calls macb_configure_dma(). The
new context has a different rx_buffer_size (derived from new_mtu),
but the DMACFG register's RXBS field still reflects the old
value. If new MTU > old MTU, the hardware will DMA past the end
of the new buffers using the old (smaller) RXBS. Shouldn't
macb_configure_dma() be called after the swap?
> +
> return 0;
> }
^ permalink raw reply
* Re: [PATCH net-next 1/3] net: mctp: perform source address lookups when we populate our dst
From: Paolo Abeni @ 2026-04-02 11:30 UTC (permalink / raw)
To: Jeremy Kerr, Matt Johnston, David S. Miller, Eric Dumazet,
Jakub Kicinski, Simon Horman
Cc: netdev
In-Reply-To: <20260331-dev-mctp-null-eids-v1-1-b4d047372eaf@codeconstruct.com.au>
On 3/31/26 9:41 AM, Jeremy Kerr wrote:
> Rather than querying the output device for its address in
> mctp_local_output, set up the source address when we're populating the
> dst structure. If no address is assigned, use MCTP_ADDR_NULL.
>
> This will allow us more flexibility when routing for NULL-source-eid
> cases. For now though, we still reject a NULL source address in the
> output path.
>
> We need to update the tests a little, so that addresses are assigned
> before we do the dst lookups.
>
> Signed-off-by: Jeremy Kerr <jk@codeconstruct.com.au>
Sashiko pointed to a possible pre-existent issue:
https://sashiko.dev/#/patchset/20260331-dev-mctp-null-eids-v1-0-b4d047372eaf%40codeconstruct.com.au
please have a look and follow-up if needed.
Thanks,
Paolo
^ permalink raw reply
* [PATCH ipsec 1/2] xfrm: Wait for RCU readers during policy netns exit
From: Steffen Klassert @ 2026-04-02 11:31 UTC (permalink / raw)
To: netdev; +Cc: Florian Westphal
xfrm_policy_fini() frees the policy_bydst hash tables after flushing the
policy work items and deleting all policies, but it does not wait for
concurrent RCU readers to leave their read-side critical sections first.
The policy_bydst tables are published via rcu_assign_pointer() and are
looked up through rcu_dereference_check(), so netns teardown must also
wait for an RCU grace period before freeing the table memory.
Fix this by adding synchronize_rcu() before freeing the policy hash tables.
Fixes: e1e551bc5630 ("xfrm: policy: prepare policy_bydst hash for rcu lookups")
Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
---
net/xfrm/xfrm_policy.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c
index 362939aa56cf..8f0188e763c7 100644
--- a/net/xfrm/xfrm_policy.c
+++ b/net/xfrm/xfrm_policy.c
@@ -4290,6 +4290,8 @@ static void xfrm_policy_fini(struct net *net)
#endif
xfrm_policy_flush(net, XFRM_POLICY_TYPE_MAIN, false);
+ synchronize_rcu();
+
WARN_ON(!list_empty(&net->xfrm.policy_all));
for (dir = 0; dir < XFRM_POLICY_MAX; dir++) {
--
2.43.0
^ permalink raw reply related
* [PATCH ipsec 2/2] xfrm: Wait for RCU readers during state netns exit
From: Steffen Klassert @ 2026-04-02 11:31 UTC (permalink / raw)
To: netdev; +Cc: Florian Westphal
In-Reply-To: <ac5TePdKtegtWiRG@secunet.com>
xfrm_state_fini() flushes the resize and GC work, destroys all states, and
then frees the state hash tables and the inbound percpu state cache.
Those objects can still be observed by concurrent RCU readers. We need
to wait for a RCU grace period before freeing the hash tables and the
percpu cache to avoid netns teardown racing with lockless lookups.
Fix this by adding synchronize_rcu() before freeing the state hash
tables and the inbound percpu state cache.
Fixes: c8406998b801 ("xfrm: state: use rcu_deref and assign_pointer helpers")
Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
---
net/xfrm/xfrm_state.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/net/xfrm/xfrm_state.c b/net/xfrm/xfrm_state.c
index 1748d374abca..84fbf1591138 100644
--- a/net/xfrm/xfrm_state.c
+++ b/net/xfrm/xfrm_state.c
@@ -3327,6 +3327,8 @@ void xfrm_state_fini(struct net *net)
xfrm_state_flush(net, 0, false);
flush_work(&xfrm_state_gc_work);
+ synchronize_rcu();
+
WARN_ON(!list_empty(&net->xfrm.state_all));
for (i = 0; i <= net->xfrm.state_hmask; i++) {
--
2.43.0
^ permalink raw reply related
* [PATCH v1 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add clocks and resets nodes for JHB100 RISC-V BMC SoC. They contain
sys0crg/sys1crg/sys2crg/per0crg/per1crg/per2crg/per3crg.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jhb100.dtsi | 198 ++++++++++++++++++++++-
1 file changed, 195 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
index 4d03470f78ab..700d00f800bc 100644
--- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -4,6 +4,8 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <dt-bindings/reset/starfive,jhb100-crg.h>
/ {
compatible = "starfive,jhb100";
@@ -268,12 +270,96 @@ pmu {
<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */
};
- clk_uart: clk-uart {
- compatible = "fixed-clock"; /* Initial clock handler for UART */
+ osc: osc {
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
+ pll0: pll0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400000000>;
+ };
+
+ pll1: pll1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+
+ pll2: pll2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <903168000>;
+ };
+
+ pll4: pll4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100700000>;
+ };
+
+ pll5: pll5 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100700000>;
+ };
+
+ pll6: pll6 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400000000>;
+ };
+
+ pll7: pll7 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1950000000>;
+ };
+
+ per2_gmac2_rgmii_rx: per2-gmac2-rgmii-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per2_gmac2_rmii_ref: per2-gmac2-rmii-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ per2_gmac3_sgmii_tx: per2-gmac3-sgmii-tx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per2_gmac3_sgmii_rx: per2-gmac3-sgmii-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per3_gmac0_rmii_rclki: per3-gmac0-rmii-rclki {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ per3_gmac1_sgmii_tx: per3-gmac1-sgmii-tx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per3_gmac1_sgmii_rx: per3-gmac1-sgmii-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -315,12 +401,118 @@ bus_nioc: bus_nioc {
uart6: serial@11982000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x11982000 0x0 0x400>;
- clocks = <&clk_uart>, <&clk_uart>;
+ clocks = <&per0crg JHB100_PER0CLK_SCLK_UART6>,
+ <&per0crg JHB100_PER0CLK_APB_UART6>;
clock-names = "baudclk", "apb_pclk";
+ resets = <&per0crg JHB100_PER0RST_MAIN_RSTN_UART6>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
+
+ per0crg: clock-controller@11a08000 {
+ compatible = "starfive,jhb100-per0crg";
+ reg = <0x0 0x11a08000 0x0 0x1000>;
+ clocks = <&osc>, <&pll6>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER0_400>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER0_800>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER0_600>,
+ <&sys2crg JHB100_SYS2CLK_BMCPER0_200>;
+ clock-names = "osc", "pll6", "per0_400",
+ "per0_800", "per0_600",
+ "per0_200_init";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ per1crg: clock-controller@11b40000 {
+ compatible = "starfive,jhb100-per1crg";
+ reg = <0x0 0x11b40000 0x0 0x1000>;
+ clocks = <&pll7>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER1_600>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER1_800>,
+ <&sys2crg JHB100_SYS2CLK_BMCPER1_200>,
+ <&sys2crg JHB100_SYS2CLK_BMCPER1_143>;
+ clock-names = "pll7", "per1_600",
+ "per1_800", "per1_200",
+ "per1_143";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ per2crg: clock-controller@11bc0000 {
+ compatible = "starfive,jhb100-per2crg";
+ reg = <0x0 0x11bc0000 0x0 0x1000>;
+ clocks = <&sys0crg JHB100_SYS0CLK_BMCPER2_600>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER2_400>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER2_125>,
+ <&per2_gmac2_rgmii_rx>,
+ <&per2_gmac2_rmii_ref>,
+ <&per2_gmac3_sgmii_tx>,
+ <&per2_gmac3_sgmii_rx>,
+ <&osc>;
+ clock-names = "per2_600", "per2_400", "per2_125",
+ "per2_gmac2_rgmii_rx",
+ "per2_gmac2_rmii_ref",
+ "per2_gmac3_sgmii_tx",
+ "per2_gmac3_sgmii_rx",
+ "osc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ per3crg: clock-controller@11c40000 {
+ compatible = "starfive,jhb100-per3crg";
+ reg = <0x0 0x11c40000 0x0 0x1000>;
+ clocks = <&sys0crg JHB100_SYS0CLK_BMCPER3_600>,
+ <&sys1crg JHB100_SYS1CLK_BMCPER3_100>,
+ <&sys1crg JHB100_SYS1CLK_BMCPER3_125>,
+ <&per3_gmac0_rmii_rclki>,
+ <&per3_gmac1_sgmii_tx>,
+ <&per3_gmac1_sgmii_rx>,
+ <&osc>;
+ clock-names = "per3_600", "per3_100", "per3_125",
+ "per3_gmac0_rmii_rclki",
+ "per3_gmac1_sgmii_tx",
+ "per3_gmac1_sgmii_rx",
+ "osc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sys0crg: clock-controller@13000000 {
+ compatible = "starfive,jhb100-sys0crg";
+ reg = <0x0 0x13000000 0x0 0x4000>;
+ clocks = <&osc>, <&pll0>, <&pll1>,
+ <&pll2>;
+ clock-names = "osc", "pll0", "pll1", "pll2";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sys1crg: clock-controller@13004000 {
+ compatible = "starfive,jhb100-sys1crg";
+ reg = <0x0 0x13004000 0x0 0x4000>;
+ clocks = <&osc>, <&pll0>, <&pll1>,
+ <&pll2>, <&pll4>, <&pll5>,
+ <&sys0crg JHB100_SYS0CLK_NPU_600>;
+ clock-names = "osc", "pll0", "pll1", "pll2",
+ "pll4", "pll5", "sys1_npu_600";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sys2crg: clock-controller@13008000 {
+ compatible = "starfive,jhb100-sys2crg";
+ reg = <0x0 0x13008000 0x0 0x4000>;
+ clocks = <&osc>, <&pll1>,
+ <&sys0crg JHB100_SYS0CLK_GPU0_600>,
+ <&sys0crg JHB100_SYS0CLK_GPU1_600>;
+ clock-names = "osc", "pll1", "sys2_gpu0_600",
+ "sys2_gpu1_600";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
};
--
2.25.1
^ permalink raw reply related
* Re: [PATCH net-next 00/11] net: macb: implement context swapping
From: Nicolai Buchwitz @ 2026-04-02 11:35 UTC (permalink / raw)
To: Théo Lebrun
Cc: Nicolas Ferre, Claudiu Beznea, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Richard Cochran,
Russell King, Paolo Valerio, Conor Dooley, Vladimir Kondratiev,
Gregory CLEMENT, Benoît Monin, Tawfik Bayouk,
Thomas Petazzoni, Maxime Chevallier, netdev, linux-kernel
In-Reply-To: <20260401-macb-context-v1-0-9590c5ab7272@bootlin.com>
On 1.4.2026 18:39, Théo Lebrun wrote:
> MACB has a pretty primitive approach to buffer management. They are all
> stored in `struct macb *bp`. On operations that require buffer realloc
> (set_ringparam & change_mtu ATM), the only option is to close the
> interface, change our global state and re-open the interface.
>
> Two issues:
> - It doesn't fly on memory pressured systems; we free our precious
> buffers and don't manage to reallocate fully, meaning our machine
> just lost its network access.
> - Anecdotally, it is pretty slow because it implies a full PHY reinit.
>
> Instead, we shall:
> - allocate a new context (including buffers) first
> - if it fails, early return without any impact to the interface
> - stop interface
> - update global state (bp, netdev, etc)
> - pass newly allocated buffer pointers to the hardware
> - start interface
> - free old context
>
> This is what we implement here. Both .set_ringparam() and
> .ndo_change_mtu() are covered by this series. In the future,
> at least .set_channels() [0], XDP [1] and XSK [2] would benefit.
Thanks for your work, the context swapping approach probably
makes a lot of sense and will finally bring proper MTU change
support that I tried to patch earlier.
>
> The change is super intrusive so conflicts will be major. Sorry!
>
> Thanks,
> Have a nice day,
> Théo
>
> [0]:
> https://lore.kernel.org/netdev/20260317-macb-set-channels-v4-0-1bd4f4ffcfca@bootlin.com/
> [1]:
> https://lore.kernel.org/netdev/20260323221047.2749577-1-pvalerio@redhat.com/
> [2]:
> https://lore.kernel.org/netdev/20260304-macb-xsk-v1-0-ba2ebe2bdaa3@bootlin.com/
>
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
> Théo Lebrun (11):
> net: macb: unify device pointer naming convention
> net: macb: unify `struct macb *` naming convention
> net: macb: unify queue index variable naming convention and types
> net: macb: enforce reverse christmas tree (RCT) convention
> net: macb: allocate tieoff descriptor once across device lifetime
> net: macb: introduce macb_context struct for buffer management
> net: macb: avoid macb_init_rx_buffer_size() modifying state
> net: macb: make `struct macb` subset reachable from macb_context
> struct
> net: macb: introduce macb_context_alloc() helper
> net: macb: use context swapping in .set_ringparam()
> net: macb: use context swapping in .ndo_change_mtu()
>
> drivers/net/ethernet/cadence/macb.h | 119 +-
> drivers/net/ethernet/cadence/macb_main.c | 1731
> +++++++++++++++++-------------
> drivers/net/ethernet/cadence/macb_pci.c | 46 +-
> drivers/net/ethernet/cadence/macb_ptp.c | 26 +-
> 4 files changed, 1090 insertions(+), 832 deletions(-)
> ---
> base-commit: 321d1ee521de1362c22adadbc0ce066050a17783
The series didn't apply cleanly on current net-next. The
base commit 321d1ee521de doesn't seem to be upstream yet, is
this based on your set_channels v4 series?
> change-id: 20260401-macb-context-bd0caf20414d
>
> Best regards,
> --
> Théo Lebrun <theo.lebrun@bootlin.com>
Thanks
Nicolai
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox