* [PATCH 7/7] arm64: defconfig: enable clock controller drivers for Qualcomm Nord
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
Enable the clock controller drivers for Nord platform from Qualcomm.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 163b7f0314c90fc45eb6c4aa5e8faa549c60fdf7..f1a3333bb07482ef4f8b4ea9154b0f2c74587a04 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1483,6 +1483,8 @@ CONFIG_CLK_KAANAPALI_GCC=y
CONFIG_CLK_KAANAPALI_GPUCC=m
CONFIG_CLK_KAANAPALI_TCSRCC=m
CONFIG_CLK_KAANAPALI_VIDEOCC=m
+CONFIG_CLK_NORD_GCC=y
+CONFIG_CLK_NORD_TCSRCC=y
CONFIG_CLK_X1E80100_CAMCC=m
CONFIG_CLK_X1E80100_DISPCC=m
CONFIG_CLK_X1E80100_GCC=y
--
2.47.3
^ permalink raw reply related
* [PATCH 5/7] clk: qcom: rpmh: Add support for Nord rpmh clocks
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski, Prasanna Tolety
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
From: Prasanna Tolety <quic_ptolety@quicinc.com>
Add RPMH clock support for the Nord SoC to allow enable/disable of the
clocks.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
drivers/clk/qcom/clk-rpmh.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 6a54481cc6ae175b8238117eefb4f38af0ec40a4..0c423a72662ede52a3ec93679859ae5697a9d7c4 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -349,6 +349,10 @@ DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2);
DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a1, "lnbclka1", 1);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a1, "lnbclka2", 1);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a1, "lnbclka3", 1);
+
DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2);
@@ -965,6 +969,21 @@ static const struct clk_rpmh_desc clk_rpmh_eliza = {
.num_clks = ARRAY_SIZE(eliza_rpmh_clocks),
};
+static struct clk_hw *nord_rpmh_clocks[] = {
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a1.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a1_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a1.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a1_ao.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_nord = {
+ .clks = nord_rpmh_clocks,
+ .num_clks = ARRAY_SIZE(nord_rpmh_clocks),
+};
+
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@@ -1054,6 +1073,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
}
static const struct of_device_id clk_rpmh_match_table[] = {
+ { .compatible = "qcom,nord-rpmh-clk", .data = &clk_rpmh_nord},
{ .compatible = "qcom,eliza-rpmh-clk", .data = &clk_rpmh_eliza},
{ .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
{ .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
--
2.47.3
^ permalink raw reply related
* [PATCH 4/7] clk: qcom: Add TCSR clock driver for Nord SoC
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
From: Taniya Das <taniya.das@oss.qualcomm.com>
Add a clock driver for the TCSR clock controller found on Nord SoC,
which provides refclks for PCIE, USB, SGMII, UFS subsystems.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
[Shawn:
- Use compatible qcom,nord-tcsrcc
- Drop include of <linux/of.h> as the driver doesn't use any OF APIs]
Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/tcsrcc-nord.c | 337 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 345 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8f55f10261ec2dd4add61101c5619cc4516f7d66..10c74db7e072f560f4bc26f81b4378034d1f9bf6 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -674,6 +674,13 @@ config QCS_GCC_404
Say Y if you want to use multimedia devices or peripheral
devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
+config CLK_NORD_TCSRCC
+ tristate "Nord TCSR Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ help
+ Support for the TCSR clock controller on Nord devices.
+ Say Y if you want to use peripheral devices such as PCIe, USB, UFS etc.
+
config SA_CAMCC_8775P
tristate "SA8775P Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 103d6c4b860ccbc6b4ad552e9e6af43298a4474d..1a7ff1986b834f48dbaa2fd8c2559f0046ea7579 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o
+obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o
obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
diff --git a/drivers/clk/qcom/tcsrcc-nord.c b/drivers/clk/qcom/tcsrcc-nord.c
new file mode 100644
index 0000000000000000000000000000000000000000..ed0f4909158f6e7e073e111549a8740f6a7fc94c
--- /dev/null
+++ b/drivers/clk/qcom/tcsrcc-nord.c
@@ -0,0 +1,337 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,nord-tcsrcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "reset.h"
+
+enum {
+ DT_BI_TCXO_PAD,
+};
+
+static struct clk_branch tcsr_dp_rx_0_clkref_en = {
+ .halt_reg = 0xa008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xa008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_rx_0_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_dp_rx_1_clkref_en = {
+ .halt_reg = 0xb008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xb008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_rx_1_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_dp_tx_0_clkref_en = {
+ .halt_reg = 0xc008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xc008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_tx_0_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_dp_tx_1_clkref_en = {
+ .halt_reg = 0xd008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xd008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_tx_1_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_dp_tx_2_clkref_en = {
+ .halt_reg = 0xe008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xe008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_tx_2_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_dp_tx_3_clkref_en = {
+ .halt_reg = 0xf008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xf008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_tx_3_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_pcie_clkref_en = {
+ .halt_reg = 0x8,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_pcie_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_ufs_clkref_en = {
+ .halt_reg = 0x3008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x3008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_ufs_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb2_0_clkref_en = {
+ .halt_reg = 0x4008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x4008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb2_0_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb2_1_clkref_en = {
+ .halt_reg = 0x5008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb2_1_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb2_2_clkref_en = {
+ .halt_reg = 0x6008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x6008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb2_2_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb3_0_clkref_en = {
+ .halt_reg = 0x8008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x8008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb3_0_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb3_1_clkref_en = {
+ .halt_reg = 0x7008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x7008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb3_1_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_ux_sgmii_0_clkref_en = {
+ .halt_reg = 0x1008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_ux_sgmii_0_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_ux_sgmii_1_clkref_en = {
+ .halt_reg = 0x2008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_ux_sgmii_1_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *tcsr_cc_nord_clocks[] = {
+ [TCSR_DP_RX_0_CLKREF_EN] = &tcsr_dp_rx_0_clkref_en.clkr,
+ [TCSR_DP_RX_1_CLKREF_EN] = &tcsr_dp_rx_1_clkref_en.clkr,
+ [TCSR_DP_TX_0_CLKREF_EN] = &tcsr_dp_tx_0_clkref_en.clkr,
+ [TCSR_DP_TX_1_CLKREF_EN] = &tcsr_dp_tx_1_clkref_en.clkr,
+ [TCSR_DP_TX_2_CLKREF_EN] = &tcsr_dp_tx_2_clkref_en.clkr,
+ [TCSR_DP_TX_3_CLKREF_EN] = &tcsr_dp_tx_3_clkref_en.clkr,
+ [TCSR_PCIE_CLKREF_EN] = &tcsr_pcie_clkref_en.clkr,
+ [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
+ [TCSR_USB2_0_CLKREF_EN] = &tcsr_usb2_0_clkref_en.clkr,
+ [TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr,
+ [TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr,
+ [TCSR_USB3_0_CLKREF_EN] = &tcsr_usb3_0_clkref_en.clkr,
+ [TCSR_USB3_1_CLKREF_EN] = &tcsr_usb3_1_clkref_en.clkr,
+ [TCSR_UX_SGMII_0_CLKREF_EN] = &tcsr_ux_sgmii_0_clkref_en.clkr,
+ [TCSR_UX_SGMII_1_CLKREF_EN] = &tcsr_ux_sgmii_1_clkref_en.clkr,
+};
+
+static const struct regmap_config tcsr_cc_nord_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xf008,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc tcsr_cc_nord_desc = {
+ .config = &tcsr_cc_nord_regmap_config,
+ .clks = tcsr_cc_nord_clocks,
+ .num_clks = ARRAY_SIZE(tcsr_cc_nord_clocks),
+};
+
+static const struct of_device_id tcsr_cc_nord_match_table[] = {
+ { .compatible = "qcom,nord-tcsrcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, tcsr_cc_nord_match_table);
+
+static int tcsr_cc_nord_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &tcsr_cc_nord_desc);
+}
+
+static struct platform_driver tcsr_cc_nord_driver = {
+ .probe = tcsr_cc_nord_probe,
+ .driver = {
+ .name = "tcsrcc-nord",
+ .of_match_table = tcsr_cc_nord_match_table,
+ },
+};
+
+module_platform_driver(tcsr_cc_nord_driver);
+
+MODULE_DESCRIPTION("QTI TCSRCC NORD Driver");
+MODULE_LICENSE("GPL");
--
2.47.3
^ permalink raw reply related
* [PATCH 3/7] dt-bindings: clock: qcom: Add Nord Global Clock Controller
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
From: Taniya Das <taniya.das@oss.qualcomm.com>
Add device tree bindings for the global clock controller on Qualcomm
Nord platform. The global clock controller on Nord SoC is divided into
multiple clock controllers (GCC,SE_GCC,NE_GCC and NW_GCC). Add each of
the bindings to define the clock controllers.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
.../devicetree/bindings/clock/qcom,nord-gcc.yaml | 58 ++++++++
.../devicetree/bindings/clock/qcom,nord-negcc.yaml | 60 +++++++++
.../devicetree/bindings/clock/qcom,nord-nwgcc.yaml | 55 ++++++++
include/dt-bindings/clock/qcom,nord-gcc.h | 147 +++++++++++++++++++++
include/dt-bindings/clock/qcom,nord-negcc.h | 124 +++++++++++++++++
include/dt-bindings/clock/qcom,nord-nwgcc.h | 69 ++++++++++
include/dt-bindings/clock/qcom,nord-segcc.h | 98 ++++++++++++++
7 files changed, 611 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..e35136722a931ef76f80d36ad2bc07fe618490d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on Nord SoC.
+
+ See also: include/dt-bindings/clock/qcom,nord-gcc.h
+
+properties:
+ compatible:
+ const: qcom,nord-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: PCIE A Pipe clock source
+ - description: PCIE B Pipe clock source
+ - description: PCIE C Pipe clock source
+ - description: PCIE D Pipe clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,nord-gcc";
+ reg = <0x00100000 0x1f4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&pcie_a_pipe_clk>,
+ <&pcie_b_pipe_clk>,
+ <&pcie_c_pipe_clk>,
+ <&pcie_d_pipe_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml b/Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..749389f65ee14999b3a195256e34f486e9aace1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-negcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global North East Clock & Reset Controller on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control (NE) module provides the clocks, resets
+ and power domains on Nord SoC.
+
+ See also: include/dt-bindings/clock/qcom,nord-negcc.h
+
+properties:
+ compatible:
+ const: qcom,nord-negcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: UFS Phy Rx symbol 0 clock source
+ - description: UFS Phy Rx symbol 1 clock source
+ - description: UFS Phy Tx symbol 0 clock source
+ - description: USB3 Phy sec wrapper pipe clock source
+ - description: USB3 Phy wrapper pipe clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@8900000 {
+ compatible = "qcom,nord-negcc";
+ reg = <0x08900000 0xf4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&ufs_phy_rx_symbol_0_clk>,
+ <&ufs_phy_rx_symbol_1_clk>,
+ <&ufs_phy_tx_symbol_0_clk>,
+ <&usb3_phy_sec_pipe_clk>,
+ <&usb3_phy_pipe_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml b/Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..ce33f966bdfdf0b0ccebc40944e3d961c79c6fe0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global North West and South East Clock & Reset Controller
+ on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control (NW, SE) module provides the clocks, resets
+ and power domains on Nord SoC.
+
+ See also:
+ include/dt-bindings/clock/qcom,nord-nwgcc.h
+ include/dt-bindings/clock/qcom,nord-segcc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,nord-nwgcc
+ - qcom,nord-segcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@8b00000 {
+ compatible = "qcom,nord-nwgcc";
+ reg = <0x08b00000 0xf4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/include/dt-bindings/clock/qcom,nord-gcc.h b/include/dt-bindings/clock/qcom,nord-gcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..8fbde162c8598d75b42136350fb23b33c29c339f
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-gcc.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
+
+/* GCC clocks */
+#define GCC_BOOT_ROM_AHB_CLK 0
+#define GCC_GP1_CLK 1
+#define GCC_GP1_CLK_SRC 2
+#define GCC_GP2_CLK 3
+#define GCC_GP2_CLK_SRC 4
+#define GCC_GPLL0 5
+#define GCC_GPLL0_OUT_EVEN 6
+#define GCC_MMU_0_TCU_VOTE_CLK 7
+#define GCC_PCIE_A_AUX_CLK 8
+#define GCC_PCIE_A_AUX_CLK_SRC 9
+#define GCC_PCIE_A_CFG_AHB_CLK 10
+#define GCC_PCIE_A_DTI_QTC_CLK 11
+#define GCC_PCIE_A_MSTR_AXI_CLK 12
+#define GCC_PCIE_A_PHY_AUX_CLK 13
+#define GCC_PCIE_A_PHY_AUX_CLK_SRC 14
+#define GCC_PCIE_A_PHY_RCHNG_CLK 15
+#define GCC_PCIE_A_PHY_RCHNG_CLK_SRC 16
+#define GCC_PCIE_A_PIPE_CLK 17
+#define GCC_PCIE_A_PIPE_CLK_SRC 18
+#define GCC_PCIE_A_SLV_AXI_CLK 19
+#define GCC_PCIE_A_SLV_Q2A_AXI_CLK 20
+#define GCC_PCIE_B_AUX_CLK 21
+#define GCC_PCIE_B_AUX_CLK_SRC 22
+#define GCC_PCIE_B_CFG_AHB_CLK 23
+#define GCC_PCIE_B_DTI_QTC_CLK 24
+#define GCC_PCIE_B_MSTR_AXI_CLK 25
+#define GCC_PCIE_B_PHY_AUX_CLK 26
+#define GCC_PCIE_B_PHY_AUX_CLK_SRC 27
+#define GCC_PCIE_B_PHY_RCHNG_CLK 28
+#define GCC_PCIE_B_PHY_RCHNG_CLK_SRC 29
+#define GCC_PCIE_B_PIPE_CLK 30
+#define GCC_PCIE_B_PIPE_CLK_SRC 31
+#define GCC_PCIE_B_SLV_AXI_CLK 32
+#define GCC_PCIE_B_SLV_Q2A_AXI_CLK 33
+#define GCC_PCIE_C_AUX_CLK 34
+#define GCC_PCIE_C_AUX_CLK_SRC 35
+#define GCC_PCIE_C_CFG_AHB_CLK 36
+#define GCC_PCIE_C_DTI_QTC_CLK 37
+#define GCC_PCIE_C_MSTR_AXI_CLK 38
+#define GCC_PCIE_C_PHY_AUX_CLK 39
+#define GCC_PCIE_C_PHY_AUX_CLK_SRC 40
+#define GCC_PCIE_C_PHY_RCHNG_CLK 41
+#define GCC_PCIE_C_PHY_RCHNG_CLK_SRC 42
+#define GCC_PCIE_C_PIPE_CLK 43
+#define GCC_PCIE_C_PIPE_CLK_SRC 44
+#define GCC_PCIE_C_SLV_AXI_CLK 45
+#define GCC_PCIE_C_SLV_Q2A_AXI_CLK 46
+#define GCC_PCIE_D_AUX_CLK 47
+#define GCC_PCIE_D_AUX_CLK_SRC 48
+#define GCC_PCIE_D_CFG_AHB_CLK 49
+#define GCC_PCIE_D_DTI_QTC_CLK 50
+#define GCC_PCIE_D_MSTR_AXI_CLK 51
+#define GCC_PCIE_D_PHY_AUX_CLK 52
+#define GCC_PCIE_D_PHY_AUX_CLK_SRC 53
+#define GCC_PCIE_D_PHY_RCHNG_CLK 54
+#define GCC_PCIE_D_PHY_RCHNG_CLK_SRC 55
+#define GCC_PCIE_D_PIPE_CLK 56
+#define GCC_PCIE_D_PIPE_CLK_SRC 57
+#define GCC_PCIE_D_SLV_AXI_CLK 58
+#define GCC_PCIE_D_SLV_Q2A_AXI_CLK 59
+#define GCC_PCIE_LINK_AHB_CLK 60
+#define GCC_PCIE_LINK_XO_CLK 61
+#define GCC_PCIE_NOC_ASYNC_BRIDGE_CLK 62
+#define GCC_PCIE_NOC_CNOC_SF_QX_CLK 63
+#define GCC_PCIE_NOC_M_CFG_CLK 64
+#define GCC_PCIE_NOC_M_PDB_CLK 65
+#define GCC_PCIE_NOC_MSTR_AXI_CLK 66
+#define GCC_PCIE_NOC_PWRCTL_CLK 67
+#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 68
+#define GCC_PCIE_NOC_REFGEN_CLK 69
+#define GCC_PCIE_NOC_REFGEN_CLK_SRC 70
+#define GCC_PCIE_NOC_S_CFG_CLK 71
+#define GCC_PCIE_NOC_S_PDB_CLK 72
+#define GCC_PCIE_NOC_SAFETY_CLK 73
+#define GCC_PCIE_NOC_SAFETY_CLK_SRC 74
+#define GCC_PCIE_NOC_SLAVE_AXI_CLK 75
+#define GCC_PCIE_NOC_TSCTR_CLK 76
+#define GCC_PCIE_NOC_XO_CLK 77
+#define GCC_PDM2_CLK 78
+#define GCC_PDM2_CLK_SRC 79
+#define GCC_PDM_AHB_CLK 80
+#define GCC_PDM_XO4_CLK 81
+#define GCC_QUPV3_WRAP3_CORE_2X_CLK 82
+#define GCC_QUPV3_WRAP3_CORE_CLK 83
+#define GCC_QUPV3_WRAP3_M_CLK 84
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 85
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 86
+#define GCC_QUPV3_WRAP3_S0_CLK 87
+#define GCC_QUPV3_WRAP3_S0_CLK_SRC 88
+#define GCC_QUPV3_WRAP3_S_AHB_CLK 89
+#define GCC_SMMU_PCIE_QTC_VOTE_CLK 90
+
+/* GCC power domains */
+#define GCC_PCIE_A_GDSC 0
+#define GCC_PCIE_A_PHY_GDSC 1
+#define GCC_PCIE_B_GDSC 2
+#define GCC_PCIE_B_PHY_GDSC 3
+#define GCC_PCIE_C_GDSC 4
+#define GCC_PCIE_C_PHY_GDSC 5
+#define GCC_PCIE_D_GDSC 6
+#define GCC_PCIE_D_PHY_GDSC 7
+#define GCC_PCIE_NOC_GDSC 8
+
+/* GCC resets */
+#define GCC_PCIE_A_BCR 0
+#define GCC_PCIE_A_LINK_DOWN_BCR 1
+#define GCC_PCIE_A_NOCSR_COM_PHY_BCR 2
+#define GCC_PCIE_A_PHY_BCR 3
+#define GCC_PCIE_A_PHY_CFG_AHB_BCR 4
+#define GCC_PCIE_A_PHY_COM_BCR 5
+#define GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR 6
+#define GCC_PCIE_B_BCR 7
+#define GCC_PCIE_B_LINK_DOWN_BCR 8
+#define GCC_PCIE_B_NOCSR_COM_PHY_BCR 9
+#define GCC_PCIE_B_PHY_BCR 10
+#define GCC_PCIE_B_PHY_CFG_AHB_BCR 11
+#define GCC_PCIE_B_PHY_COM_BCR 12
+#define GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR 13
+#define GCC_PCIE_C_BCR 14
+#define GCC_PCIE_C_LINK_DOWN_BCR 15
+#define GCC_PCIE_C_NOCSR_COM_PHY_BCR 16
+#define GCC_PCIE_C_PHY_BCR 17
+#define GCC_PCIE_C_PHY_CFG_AHB_BCR 18
+#define GCC_PCIE_C_PHY_COM_BCR 19
+#define GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR 20
+#define GCC_PCIE_D_BCR 21
+#define GCC_PCIE_D_LINK_DOWN_BCR 22
+#define GCC_PCIE_D_NOCSR_COM_PHY_BCR 23
+#define GCC_PCIE_D_PHY_BCR 24
+#define GCC_PCIE_D_PHY_CFG_AHB_BCR 25
+#define GCC_PCIE_D_PHY_COM_BCR 26
+#define GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR 27
+#define GCC_PCIE_NOC_BCR 28
+#define GCC_PDM_BCR 29
+#define GCC_QUPV3_WRAPPER_3_BCR 30
+#define GCC_TCSR_PCIE_BCR 31
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-negcc.h b/include/dt-bindings/clock/qcom,nord-negcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..95f333d8e1aa7cf1e386b6926380b2c853f7cf43
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-negcc.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H
+
+/* NE_GCC clocks */
+#define NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK 0
+#define NE_GCC_AGGRE_NOC_USB2_AXI_CLK 1
+#define NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK 2
+#define NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK 3
+#define NE_GCC_AHB2PHY_CLK 4
+#define NE_GCC_CNOC_USB2_AXI_CLK 5
+#define NE_GCC_CNOC_USB3_PRIM_AXI_CLK 6
+#define NE_GCC_CNOC_USB3_SEC_AXI_CLK 7
+#define NE_GCC_FRQ_MEASURE_REF_CLK 8
+#define NE_GCC_GP1_CLK 9
+#define NE_GCC_GP1_CLK_SRC 10
+#define NE_GCC_GP2_CLK 11
+#define NE_GCC_GP2_CLK_SRC 12
+#define NE_GCC_GPLL0 13
+#define NE_GCC_GPLL0_OUT_EVEN 14
+#define NE_GCC_GPLL2 15
+#define NE_GCC_GPU_2_CFG_CLK 16
+#define NE_GCC_GPU_2_GPLL0_CLK_SRC 17
+#define NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC 18
+#define NE_GCC_GPU_2_HSCNOC_GFX_CLK 19
+#define NE_GCC_GPU_2_SMMU_VOTE_CLK 20
+#define NE_GCC_QUPV3_WRAP2_CORE_2X_CLK 21
+#define NE_GCC_QUPV3_WRAP2_CORE_CLK 22
+#define NE_GCC_QUPV3_WRAP2_M_AHB_CLK 23
+#define NE_GCC_QUPV3_WRAP2_S0_CLK 24
+#define NE_GCC_QUPV3_WRAP2_S0_CLK_SRC 25
+#define NE_GCC_QUPV3_WRAP2_S1_CLK 26
+#define NE_GCC_QUPV3_WRAP2_S1_CLK_SRC 27
+#define NE_GCC_QUPV3_WRAP2_S2_CLK 28
+#define NE_GCC_QUPV3_WRAP2_S2_CLK_SRC 29
+#define NE_GCC_QUPV3_WRAP2_S3_CLK 30
+#define NE_GCC_QUPV3_WRAP2_S3_CLK_SRC 31
+#define NE_GCC_QUPV3_WRAP2_S4_CLK 32
+#define NE_GCC_QUPV3_WRAP2_S4_CLK_SRC 33
+#define NE_GCC_QUPV3_WRAP2_S5_CLK 34
+#define NE_GCC_QUPV3_WRAP2_S5_CLK_SRC 35
+#define NE_GCC_QUPV3_WRAP2_S6_CLK 36
+#define NE_GCC_QUPV3_WRAP2_S6_CLK_SRC 37
+#define NE_GCC_QUPV3_WRAP2_S_AHB_CLK 38
+#define NE_GCC_SDCC4_APPS_CLK 39
+#define NE_GCC_SDCC4_APPS_CLK_SRC 40
+#define NE_GCC_SDCC4_AXI_CLK 41
+#define NE_GCC_UFS_PHY_AHB_CLK 42
+#define NE_GCC_UFS_PHY_AXI_CLK 43
+#define NE_GCC_UFS_PHY_AXI_CLK_SRC 44
+#define NE_GCC_UFS_PHY_ICE_CORE_CLK 45
+#define NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC 46
+#define NE_GCC_UFS_PHY_PHY_AUX_CLK 47
+#define NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC 48
+#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK 49
+#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 50
+#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK 51
+#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 52
+#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK 53
+#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 54
+#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK 55
+#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 56
+#define NE_GCC_USB20_MASTER_CLK 57
+#define NE_GCC_USB20_MASTER_CLK_SRC 58
+#define NE_GCC_USB20_MOCK_UTMI_CLK 59
+#define NE_GCC_USB20_MOCK_UTMI_CLK_SRC 60
+#define NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 61
+#define NE_GCC_USB20_SLEEP_CLK 62
+#define NE_GCC_USB31_PRIM_ATB_CLK 63
+#define NE_GCC_USB31_PRIM_EUD_AHB_CLK 64
+#define NE_GCC_USB31_PRIM_MASTER_CLK 65
+#define NE_GCC_USB31_PRIM_MASTER_CLK_SRC 66
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK 67
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC 68
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 69
+#define NE_GCC_USB31_PRIM_SLEEP_CLK 70
+#define NE_GCC_USB31_SEC_ATB_CLK 71
+#define NE_GCC_USB31_SEC_EUD_AHB_CLK 72
+#define NE_GCC_USB31_SEC_MASTER_CLK 73
+#define NE_GCC_USB31_SEC_MASTER_CLK_SRC 74
+#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK 75
+#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC 76
+#define NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 77
+#define NE_GCC_USB31_SEC_SLEEP_CLK 78
+#define NE_GCC_USB3_PRIM_PHY_AUX_CLK 79
+#define NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC 80
+#define NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK 81
+#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK 82
+#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 83
+#define NE_GCC_USB3_SEC_PHY_AUX_CLK 84
+#define NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC 85
+#define NE_GCC_USB3_SEC_PHY_COM_AUX_CLK 86
+#define NE_GCC_USB3_SEC_PHY_PIPE_CLK 87
+#define NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC 88
+
+/* NE_GCC power domains */
+#define NE_GCC_UFS_MEM_PHY_GDSC 0
+#define NE_GCC_UFS_PHY_GDSC 1
+#define NE_GCC_USB20_PRIM_GDSC 2
+#define NE_GCC_USB31_PRIM_GDSC 3
+#define NE_GCC_USB31_SEC_GDSC 4
+#define NE_GCC_USB3_PHY_GDSC 5
+#define NE_GCC_USB3_SEC_PHY_GDSC 6
+
+/* NE_GCC resets */
+#define NE_GCC_GPU_2_BCR 0
+#define NE_GCC_QUPV3_WRAPPER_2_BCR 1
+#define NE_GCC_SDCC4_BCR 2
+#define NE_GCC_UFS_PHY_BCR 3
+#define NE_GCC_USB20_PRIM_BCR 4
+#define NE_GCC_USB31_PRIM_BCR 5
+#define NE_GCC_USB31_SEC_BCR 6
+#define NE_GCC_USB3_DP_PHY_PRIM_BCR 7
+#define NE_GCC_USB3_DP_PHY_SEC_BCR 8
+#define NE_GCC_USB3_PHY_PRIM_BCR 9
+#define NE_GCC_USB3_PHY_SEC_BCR 10
+#define NE_GCC_USB3PHY_PHY_PRIM_BCR 11
+#define NE_GCC_USB3PHY_PHY_SEC_BCR 12
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-nwgcc.h b/include/dt-bindings/clock/qcom,nord-nwgcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..b6253dd2aa85a3152f99447a60a6f8a3e85d8f3c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-nwgcc.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
+
+/* NW_GCC clocks */
+#define NW_GCC_ACMU_MUX_CLK 0
+#define NW_GCC_CAMERA_AHB_CLK 1
+#define NW_GCC_CAMERA_HF_AXI_CLK 2
+#define NW_GCC_CAMERA_SF_AXI_CLK 3
+#define NW_GCC_CAMERA_TRIG_CLK 4
+#define NW_GCC_CAMERA_XO_CLK 5
+#define NW_GCC_DISP_0_AHB_CLK 6
+#define NW_GCC_DISP_0_HF_AXI_CLK 7
+#define NW_GCC_DISP_0_TRIG_CLK 8
+#define NW_GCC_DISP_1_AHB_CLK 9
+#define NW_GCC_DISP_1_HF_AXI_CLK 10
+#define NW_GCC_DISP_1_TRIG_CLK 11
+#define NW_GCC_DPRX0_AXI_HF_CLK 12
+#define NW_GCC_DPRX0_CFG_AHB_CLK 13
+#define NW_GCC_DPRX1_AXI_HF_CLK 14
+#define NW_GCC_DPRX1_CFG_AHB_CLK 15
+#define NW_GCC_EVA_AHB_CLK 16
+#define NW_GCC_EVA_AXI0_CLK 17
+#define NW_GCC_EVA_AXI0C_CLK 18
+#define NW_GCC_EVA_TRIG_CLK 19
+#define NW_GCC_EVA_XO_CLK 20
+#define NW_GCC_FRQ_MEASURE_REF_CLK 21
+#define NW_GCC_GP1_CLK 22
+#define NW_GCC_GP1_CLK_SRC 23
+#define NW_GCC_GP2_CLK 24
+#define NW_GCC_GP2_CLK_SRC 25
+#define NW_GCC_GPLL0 26
+#define NW_GCC_GPLL0_OUT_EVEN 27
+#define NW_GCC_GPU_2_CFG_AHB_CLK 28
+#define NW_GCC_GPU_2_GPLL0_CLK_SRC 29
+#define NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC 30
+#define NW_GCC_GPU_2_HSCNOC_GFX_CLK 31
+#define NW_GCC_GPU_CFG_AHB_CLK 32
+#define NW_GCC_GPU_GPLL0_CLK_SRC 33
+#define NW_GCC_GPU_GPLL0_DIV_CLK_SRC 34
+#define NW_GCC_GPU_HSCNOC_GFX_CLK 35
+#define NW_GCC_GPU_SMMU_VOTE_CLK 36
+#define NW_GCC_HSCNOC_GPU_2_AXI_CLK 37
+#define NW_GCC_HSCNOC_GPU_AXI_CLK 38
+#define NW_GCC_MMU_1_TCU_VOTE_CLK 39
+#define NW_GCC_VIDEO_AHB_CLK 40
+#define NW_GCC_VIDEO_AXI0_CLK 41
+#define NW_GCC_VIDEO_AXI0C_CLK 42
+#define NW_GCC_VIDEO_AXI1_CLK 43
+#define NW_GCC_VIDEO_XO_CLK 44
+
+/* NW_GCC power domains */
+
+/* NW_GCC resets */
+#define NW_GCC_CAMERA_BCR 0
+#define NW_GCC_DISPLAY_0_BCR 1
+#define NW_GCC_DISPLAY_1_BCR 2
+#define NW_GCC_DPRX0_BCR 3
+#define NW_GCC_DPRX1_BCR 4
+#define NW_GCC_EVA_BCR 5
+#define NW_GCC_GPU_2_BCR 6
+#define NW_GCC_GPU_BCR 7
+#define NW_GCC_VIDEO_BCR 8
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-segcc.h b/include/dt-bindings/clock/qcom,nord-segcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..f0f7422af692d05417d126c1011a22faf3bdc611
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-segcc.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
+
+/* SE_GCC clocks */
+#define SE_GCC_EEE_EMAC0_CLK 0
+#define SE_GCC_EEE_EMAC0_CLK_SRC 1
+#define SE_GCC_EEE_EMAC1_CLK 2
+#define SE_GCC_EEE_EMAC1_CLK_SRC 3
+#define SE_GCC_EMAC0_AXI_CLK 4
+#define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5
+#define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6
+#define SE_GCC_EMAC0_PHY_AUX_CLK 7
+#define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8
+#define SE_GCC_EMAC0_PTP_CLK 9
+#define SE_GCC_EMAC0_PTP_CLK_SRC 10
+#define SE_GCC_EMAC0_RGMII_CLK 11
+#define SE_GCC_EMAC0_RGMII_CLK_SRC 12
+#define SE_GCC_EMAC0_RPCS_RX_CLK 13
+#define SE_GCC_EMAC0_RPCS_TX_CLK 14
+#define SE_GCC_EMAC0_XGXS_RX_CLK 15
+#define SE_GCC_EMAC0_XGXS_TX_CLK 16
+#define SE_GCC_EMAC1_AXI_CLK 17
+#define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18
+#define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19
+#define SE_GCC_EMAC1_PHY_AUX_CLK 20
+#define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21
+#define SE_GCC_EMAC1_PTP_CLK 22
+#define SE_GCC_EMAC1_PTP_CLK_SRC 23
+#define SE_GCC_EMAC1_RGMII_CLK 24
+#define SE_GCC_EMAC1_RGMII_CLK_SRC 25
+#define SE_GCC_EMAC1_RPCS_RX_CLK 26
+#define SE_GCC_EMAC1_RPCS_TX_CLK 27
+#define SE_GCC_EMAC1_XGXS_RX_CLK 28
+#define SE_GCC_EMAC1_XGXS_TX_CLK 29
+#define SE_GCC_FRQ_MEASURE_REF_CLK 30
+#define SE_GCC_GP1_CLK 31
+#define SE_GCC_GP1_CLK_SRC 32
+#define SE_GCC_GP2_CLK 33
+#define SE_GCC_GP2_CLK_SRC 34
+#define SE_GCC_GPLL0 35
+#define SE_GCC_GPLL0_OUT_EVEN 36
+#define SE_GCC_GPLL2 37
+#define SE_GCC_GPLL4 38
+#define SE_GCC_GPLL5 39
+#define SE_GCC_MMU_2_TCU_VOTE_CLK 40
+#define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41
+#define SE_GCC_QUPV3_WRAP0_CORE_CLK 42
+#define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43
+#define SE_GCC_QUPV3_WRAP0_S0_CLK 44
+#define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45
+#define SE_GCC_QUPV3_WRAP0_S1_CLK 46
+#define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47
+#define SE_GCC_QUPV3_WRAP0_S2_CLK 48
+#define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49
+#define SE_GCC_QUPV3_WRAP0_S3_CLK 50
+#define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51
+#define SE_GCC_QUPV3_WRAP0_S4_CLK 52
+#define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53
+#define SE_GCC_QUPV3_WRAP0_S5_CLK 54
+#define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55
+#define SE_GCC_QUPV3_WRAP0_S6_CLK 56
+#define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57
+#define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58
+#define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59
+#define SE_GCC_QUPV3_WRAP1_CORE_CLK 60
+#define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61
+#define SE_GCC_QUPV3_WRAP1_S0_CLK 62
+#define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC 63
+#define SE_GCC_QUPV3_WRAP1_S1_CLK 64
+#define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC 65
+#define SE_GCC_QUPV3_WRAP1_S2_CLK 66
+#define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC 67
+#define SE_GCC_QUPV3_WRAP1_S3_CLK 68
+#define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC 69
+#define SE_GCC_QUPV3_WRAP1_S4_CLK 70
+#define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC 71
+#define SE_GCC_QUPV3_WRAP1_S5_CLK 72
+#define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC 73
+#define SE_GCC_QUPV3_WRAP1_S6_CLK 74
+#define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC 75
+#define SE_GCC_QUPV3_WRAP1_S_AHB_CLK 76
+
+/* SE_GCC power domains */
+#define SE_GCC_EMAC0_GDSC 0
+#define SE_GCC_EMAC1_GDSC 1
+
+/* SE_GCC resets */
+#define SE_GCC_EMAC0_BCR 0
+#define SE_GCC_EMAC1_BCR 1
+#define SE_GCC_QUPV3_WRAPPER_0_BCR 2
+#define SE_GCC_QUPV3_WRAPPER_1_BCR 3
+
+#endif
--
2.47.3
^ permalink raw reply related
* [PATCH 2/7] dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
From: Taniya Das <taniya.das@oss.qualcomm.com>
Add bindings and update documentation compatible for RPMh clock
controller on Nord SoC.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
index 9690169baa4697bbd3ab9197f9661368a0827bf7..a2c404a579812dae073241ea71b63e55e798e80e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
@@ -21,6 +21,7 @@ properties:
- qcom,glymur-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,milos-rpmh-clk
+ - qcom,nord-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
- qcom,sa8775p-rpmh-clk
--
2.47.3
^ permalink raw reply related
* [PATCH 1/7] dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
From: Taniya Das <taniya.das@oss.qualcomm.com>
The Nord SoC TCSR block provides CLKREF clocks for DP, PCIe, UFS, SGMII
and USB.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
[Shawn: Use compatible qcom,nord-tcsrcc rather than qcom,nord-tcsr]
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
.../bindings/clock/qcom,sm8550-tcsr.yaml | 2 ++
include/dt-bindings/clock/qcom,nord-tcsrcc.h | 26 ++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
index ae9aef0e54e8b8b85bc70e6096d524447091f39e..1ccdf4b0f5dd390417821494cdb97d8f4ed26c58 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
@@ -17,6 +17,7 @@ description: |
See also:
- include/dt-bindings/clock/qcom,eliza-tcsr.h
- include/dt-bindings/clock/qcom,glymur-tcsr.h
+ - include/dt-bindings/clock/qcom,nord-tcsrcc.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
@@ -29,6 +30,7 @@ properties:
- qcom,glymur-tcsr
- qcom,kaanapali-tcsr
- qcom,milos-tcsr
+ - qcom,nord-tcsrcc
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
diff --git a/include/dt-bindings/clock/qcom,nord-tcsrcc.h b/include/dt-bindings/clock/qcom,nord-tcsrcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..3f0e2ff7acc72c10d00488c48ec17af8ea6de06e
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-tcsrcc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H
+
+/* TCSR_CC clocks */
+#define TCSR_DP_RX_0_CLKREF_EN 0
+#define TCSR_DP_RX_1_CLKREF_EN 1
+#define TCSR_DP_TX_0_CLKREF_EN 2
+#define TCSR_DP_TX_1_CLKREF_EN 3
+#define TCSR_DP_TX_2_CLKREF_EN 4
+#define TCSR_DP_TX_3_CLKREF_EN 5
+#define TCSR_PCIE_CLKREF_EN 6
+#define TCSR_UFS_CLKREF_EN 7
+#define TCSR_USB2_0_CLKREF_EN 8
+#define TCSR_USB2_1_CLKREF_EN 9
+#define TCSR_USB2_2_CLKREF_EN 10
+#define TCSR_USB3_0_CLKREF_EN 11
+#define TCSR_USB3_1_CLKREF_EN 12
+#define TCSR_UX_SGMII_0_CLKREF_EN 13
+#define TCSR_UX_SGMII_1_CLKREF_EN 14
+
+#endif
--
2.47.3
^ permalink raw reply related
* [PATCH 0/7] clk: qcom: add support for the clock controllers on Nord platforms
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski, Prasanna Tolety
This documents the gcc, tcsr and rpmhcc support in Nord platforms and
adds corresponding drivers as well as enables them in arm64 defconfig.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
Bartosz Golaszewski (1):
arm64: defconfig: enable clock controller drivers for Qualcomm Nord
Prasanna Tolety (1):
clk: qcom: rpmh: Add support for Nord rpmh clocks
Taniya Das (5):
dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
dt-bindings: clock: qcom: Add Nord Global Clock Controller
clk: qcom: Add TCSR clock driver for Nord SoC
clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
.../devicetree/bindings/clock/qcom,nord-gcc.yaml | 58 +
.../devicetree/bindings/clock/qcom,nord-negcc.yaml | 60 +
.../devicetree/bindings/clock/qcom,nord-nwgcc.yaml | 55 +
.../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
.../bindings/clock/qcom,sm8550-tcsr.yaml | 2 +
arch/arm64/configs/defconfig | 2 +
drivers/clk/qcom/Kconfig | 17 +
drivers/clk/qcom/Makefile | 2 +
drivers/clk/qcom/clk-rpmh.c | 20 +
drivers/clk/qcom/gcc-nord.c | 1901 +++++++++++++++++++
drivers/clk/qcom/negcc-nord.c | 1987 ++++++++++++++++++++
drivers/clk/qcom/nwgcc-nord.c | 688 +++++++
drivers/clk/qcom/segcc-nord.c | 1609 ++++++++++++++++
drivers/clk/qcom/tcsrcc-nord.c | 337 ++++
include/dt-bindings/clock/qcom,nord-gcc.h | 147 ++
include/dt-bindings/clock/qcom,nord-negcc.h | 124 ++
include/dt-bindings/clock/qcom,nord-nwgcc.h | 69 +
include/dt-bindings/clock/qcom,nord-segcc.h | 98 +
include/dt-bindings/clock/qcom,nord-tcsrcc.h | 26 +
19 files changed, 7203 insertions(+)
---
base-commit: 3b058d1aeeeff27a7289529c4944291613b364e9
change-id: 20260403-nord-clks-dd6312e1fee2
Best regards,
--
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
^ permalink raw reply
* Re: [net-next PATCH 04/10] bitfield.h: add FIELD_WIDTH()
From: Luiz Angelo Daros de Luca @ 2026-04-03 14:09 UTC (permalink / raw)
To: David Laight
Cc: Yury Norov, Andrew Lunn, Vladimir Oltean, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Simon Horman,
Linus Walleij, Alvin Šipraga, Yury Norov, Rasmus Villemoes,
Russell King, netdev, linux-kernel
In-Reply-To: <20260402232126.2e74631e@pumpkin>
Thanks David and Yuri,
This patch was originally intended to reconstruct a value split across
multiple registers. Originally:
vlan4k->member =
FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK, data[0]) |
(FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, data[2])
<< FIELD_WIDTH(RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK));
However, as Yuri pointed out, I can use FIELD_PREP() to align the bits
into the final struct member without manual bitops. While less common,
this pattern is used elsewhere (e.g., drivers/clk/clk-lmk04832.c). The
updated approach would be:
vlan4k->member =
FIELD_PREP(RTL8365MB_CVLAN_MBR_LO_MASK,
FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK,
data[0])) |
FIELD_PREP(RTL8365MB_CVLAN_MBR_HI_MASK,
FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, data[2]));
If this use of FIELD_PREP is preferred, I will drop this FIELD_WIDTH
patch from the series as it would no longer have any users.
Regards,
Luiz
^ permalink raw reply
* Re: [PATCH iwl-net v1] igc: fix potential skb leak in igc_fpe_xmit_smd_frame()
From: Simon Horman @ 2026-04-03 14:05 UTC (permalink / raw)
To: Kohei Enju
Cc: intel-wired-lan, netdev, Tony Nguyen, Przemek Kitszel,
Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Faizal Rahim
In-Reply-To: <20260329145122.126040-1-kohei@enjuk.jp>
On Sun, Mar 29, 2026 at 02:50:49PM +0000, Kohei Enju wrote:
> When igc_fpe_init_tx_descriptor() fails, no one takes care of an
> allocated skb, leaking it. [1]
>
> Use dev_kfree_skb_any() on failure.
> Also call igc_flush_tx_descriptors() only on success.
>
> [1]
> unreferenced object 0xffff88813aee1b40 (size 224):
> comm "softirq", pid 0, jiffies 4294709256
> [...]
> backtrace (crc dee31384):
> kmem_cache_alloc_node_noprof+0x54f/0x640
> __alloc_skb+0xd9/0x5b0
> igc_fpe_xmit_smd_frame.isra.0+0xad/0x510
> igc_fpe_send_mpacket+0x32/0x80
> [...]
>
> Fixes: 5422570c0010 ("igc: add support for frame preemption verification")
> Signed-off-by: Kohei Enju <kohei@enjuk.jp>
I am wondering if we can achieve this while sticking to the idiom
that the main thread of execution is for the non-error flow,
while conditions handle errors.
Something like this (completely untested!):
diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c b/drivers/net/ethernet/intel/igc/igc_tsn.c
index 8a110145bfee..02dd9f0290a3 100644
--- a/drivers/net/ethernet/intel/igc/igc_tsn.c
+++ b/drivers/net/ethernet/intel/igc/igc_tsn.c
@@ -109,10 +109,16 @@ static int igc_fpe_xmit_smd_frame(struct igc_adapter *adapter,
__netif_tx_lock(nq, cpu);
err = igc_fpe_init_tx_descriptor(ring, skb, type);
- igc_flush_tx_descriptors(ring);
+ if (err)
+ goto err_free_skb_any;
+ igc_flush_tx_descriptors(ring);
__netif_tx_unlock(nq);
+ return 0;
+err_free_skb_any:
+ __netif_tx_unlock(nq);
+ dev_kfree_skb_any(skb);
return err;
}
^ permalink raw reply related
* Re: [PATCH v1 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes
From: Conor Dooley @ 2026-04-03 14:03 UTC (permalink / raw)
To: Changhuang Liang
Cc: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-hardening@vger.kernel.org,
netdev@vger.kernel.org, JeeHeng Sia, Hal Feng, Leyfoon Tan
In-Reply-To: <ZQ4PR01MB12025313E4A491A86580558DF25E2@ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn>
[-- Attachment #1: Type: text/plain, Size: 2537 bytes --]
On Fri, Apr 03, 2026 at 01:07:48AM +0000, Changhuang Liang wrote:
> Hi, Conor
>
> > On Thu, Apr 02, 2026 at 03:55:23AM -0700, Changhuang Liang wrote:
> > > Add clocks and resets nodes for JHB100 RISC-V BMC SoC. They contain
> > > sys0crg/sys1crg/sys2crg/per0crg/per1crg/per2crg/per3crg.
> > >
> > > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> > > ---
> > > arch/riscv/boot/dts/starfive/jhb100.dtsi | 198
> > > ++++++++++++++++++++++-
> > > 1 file changed, 195 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi
> > > b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> > > index 4d03470f78ab..700d00f800bc 100644
> > > --- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
> > > +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> > > @@ -4,6 +4,8 @@
> > > */
> > >
> > > /dts-v1/;
> > > +#include <dt-bindings/clock/starfive,jhb100-crg.h>
> > > +#include <dt-bindings/reset/starfive,jhb100-crg.h>
> > >
> > > / {
> > > compatible = "starfive,jhb100";
> > > @@ -268,12 +270,96 @@ pmu {
> > > <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event
> > ID 34 */
> > > };
> > >
> > > - clk_uart: clk-uart {
> > > - compatible = "fixed-clock"; /* Initial clock handler for UART */
> > > + osc: osc {
> > > + compatible = "fixed-clock";
> > > #clock-cells = <0>;
> > > clock-frequency = <25000000>;
> > > };
> >
> > Is this really on the SoC?
>
> This is not on the SoC.
>
> >
> > >
> > > + pll0: pll0 {
> > > + compatible = "fixed-clock";
> > > + #clock-cells = <0>;
> > > + clock-frequency = <2400000000>;
> > > + };
> >
> > What's providing all of these PLLs? Are they all fixed-frequency on-chip PLLs
> > without an off-chip reference? I find that somewhat unlikely.
> >
> > Since devicetrees are now being imported into U-Boot, it's important to make
> > sure that I'm not merging fixed-clocks that later get replaced by dedicated
> > drivers that U-Boot won't have.
> >
> > To that end, I won't apply the series this depends on without this patch being
> > applied at the same time.
>
> I am preparing a PLL driver series, but PLL0 and PLL1 will still retain fixed frequencies.
> The reference clock for each PLL comes from the osc. Perhaps I can use "fixed-factor-clock"
> to indicate the relationship of the reference clock.
I'll reserve judgement until I see that series so, but it wasn't as if
any of this was going into 7.1 anyway (or maybe even 7.2) so not a
problem.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* [PATCH v3 5/5] arm64: dts: qcom: sdm845-google-common: Enable NFC
From: David Heidelberg via B4 Relay @ 2026-04-03 13:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Martinz, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Casey Connolly,
Alexander Martinz
Cc: Petr Hodina, biemster, netdev, linux-arm-msm, oe-linux-nfc,
devicetree, linux-kernel, phone-devel, Krzysztof Kozlowski,
David Heidelberg
In-Reply-To: <20260403-oneplus-nfc-v3-0-fbdce57d63c1@ixit.cz>
From: David Heidelberg <david@ixit.cz>
Enable NFC controller NXP PN557.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
index 6930066857768..b2dc0327dff85 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
@@ -391,6 +391,23 @@ &gpu_zap_shader {
firmware-name = "qcom/sdm845/Google/blueline/a630_zap.mbn";
};
+&i2c3 {
+ status = "okay";
+
+ nfc@28 {
+ compatible = "nxp,pn557", "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&nfc_int_default &nfc_enable_default>;
+ pinctrl-names = "default";
+ };
+};
+
&i2c12 {
/* Bottom spkr (right) CS35L36 @ 40 */
@@ -459,6 +476,20 @@ &tlmm {
gpio-reserved-ranges = < 0 4>, /* SPI (Intel MNH Pixel Visual Core) */
<81 4>; /* SPI (most likely Fingerprint Cards FPC1075) */
+ nfc_int_default: nfc-int-default-state {
+ pins = "gpio63";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ nfc_enable_default: nfc-enable-default-state {
+ pins = "gpio25", "gpio79";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
touchscreen_reset: ts-reset-state {
pins = "gpio99";
function = "gpio";
--
2.53.0
^ permalink raw reply related
* [PATCH v3 3/5] arm64: dts: qcom: sdm845-shift-axolotl: Correct touchscreen sleep state
From: David Heidelberg via B4 Relay @ 2026-04-03 13:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Martinz, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Casey Connolly,
Alexander Martinz
Cc: Petr Hodina, biemster, netdev, linux-arm-msm, oe-linux-nfc,
devicetree, linux-kernel, phone-devel, Krzysztof Kozlowski,
David Heidelberg
In-Reply-To: <20260403-oneplus-nfc-v3-0-fbdce57d63c1@ixit.cz>
From: David Heidelberg <david@ixit.cz>
There is no suspend state in the mainline kernel, use the sleep state
intended for this purpose.
Fixes: 45882459159d ("arm64: dts: qcom: sdm845: add device tree for SHIFT6mq")
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
index 740eb22550724..783d66cf5b0f8 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
@@ -446,7 +446,7 @@ touchscreen@38 {
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
- pinctrl-names = "default", "suspend";
+ pinctrl-names = "default", "sleep";
touchscreen-size-x = <1080>;
touchscreen-size-y = <2160>;
--
2.53.0
^ permalink raw reply related
* [PATCH v3 4/5] arm64: dts: qcom: sdm845-shift-axolotl: Enable NFC
From: David Heidelberg via B4 Relay @ 2026-04-03 13:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Martinz, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Casey Connolly,
Alexander Martinz
Cc: Petr Hodina, biemster, netdev, linux-arm-msm, oe-linux-nfc,
devicetree, linux-kernel, phone-devel, Krzysztof Kozlowski,
David Heidelberg
In-Reply-To: <20260403-oneplus-nfc-v3-0-fbdce57d63c1@ixit.cz>
From: David Heidelberg <david@ixit.cz>
Enable NFC controller NXP PN553.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 52 +++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
index 783d66cf5b0f8..101597c666332 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
@@ -431,6 +431,26 @@ &gpu_zap_shader {
firmware-name = "qcom/sdm845/SHIFT/axolotl/a630_zap.mbn";
};
+&i2c3 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ nfc@28 {
+ compatible = "nxp,pn553", "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&nfc_default>;
+ pinctrl-1 = <&nfc_sleep>;
+ pinctrl-names = "default", "sleep";
+ };
+};
+
&i2c5 {
status = "okay";
@@ -609,6 +629,38 @@ &slpi_pas {
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
+ nfc_default: nfc-default-state {
+ enable-pins {
+ pins = "gpio12", "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ int-pins {
+ pins = "gpio63";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ nfc_sleep: nfc-sleep-state {
+ enable-pins {
+ pins = "gpio12", "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ int-pins {
+ pins = "gpio63";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
sde_dsi_active: sde-dsi-active-state {
pins = "gpio6", "gpio11";
function = "gpio";
--
2.53.0
^ permalink raw reply related
* [PATCH v3 2/5] arm64: dts: qcom: sdm845-oneplus: Enable NFC
From: David Heidelberg via B4 Relay @ 2026-04-03 13:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Martinz, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Casey Connolly,
Alexander Martinz
Cc: Petr Hodina, biemster, netdev, linux-arm-msm, oe-linux-nfc,
devicetree, linux-kernel, phone-devel, Krzysztof Kozlowski,
David Heidelberg
In-Reply-To: <20260403-oneplus-nfc-v3-0-fbdce57d63c1@ixit.cz>
From: David Heidelberg <david@ixit.cz>
Enable NFC controller NXP PN553, which is part of the package NXP NQ330
(NFC + eSE).
Based on work of biemster <l.j.beemster@gmail.com>.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
.../arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 57 ++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
index 6b7378cf4d493..f5a5f1fbc1fb6 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
@@ -464,6 +464,26 @@ &gpu_zap_shader {
firmware-name = "qcom/sdm845/OnePlus/enchilada/a630_zap.mbn";
};
+&i2c3 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ nfc@28 {
+ compatible = "nxp,pn553", "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&nfc_default>;
+ pinctrl-1 = <&nfc_sleep>;
+ pinctrl-names = "default", "sleep";
+ };
+};
+
&i2c10 {
status = "okay";
clock-frequency = <100000>;
@@ -674,6 +694,11 @@ &qupv3_id_0 {
status = "okay";
};
+&qup_i2c3_default {
+ drive-strength = <2>;
+ bias-disable;
+};
+
&qup_i2c10_default {
drive-strength = <2>;
bias-disable;
@@ -1007,6 +1032,38 @@ speaker_default: speaker-default-state {
bias-pull-up;
output-high;
};
+
+ nfc_default: nfc-default-state {
+ enable-pins {
+ pins = "gpio12", "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ int-pins {
+ pins = "gpio63";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ nfc_sleep: nfc-sleep-state {
+ enable-pins {
+ pins = "gpio12", "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ int-pins {
+ pins = "gpio63";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
&venus {
--
2.53.0
^ permalink raw reply related
* [PATCH v3 0/5] NFC support for five Qualcomm SDM845 phones
From: David Heidelberg via B4 Relay @ 2026-04-03 13:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Martinz, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Casey Connolly,
Alexander Martinz
Cc: Petr Hodina, biemster, netdev, linux-arm-msm, oe-linux-nfc,
devicetree, linux-kernel, phone-devel, Krzysztof Kozlowski,
David Heidelberg
- OnePlus 6 / 6T
- Pixel 3 / 3 XL
- SHIFT 6MQ
Verified with NFC card using neard:
systemctl enable --now neard
nfctool --device nfc0 -1
nfctool -d nfc0 -p
gdbus introspect --system --dest org.neard --object-path /org/neard/nfc0/tag0/record0
or use gNFC:
https://gitlab.gnome.org/dh/gnfc/
successfully detecting and reading a tag.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
Changes in v3:
- Added Pixel 3 / 3 XL support.
- Lower drive-strength from <6>, to <2> which downstream kernel uses.
- Took full ownership of OnePlus 6 NFC patch as original author prefer to keep annonymous. (Krzysztof)
- Enable sleep states (pinctrl).
- Link to v2: https://lore.kernel.org/r/20260324-oneplus-nfc-v2-0-3eef052c9bc6@ixit.cz
Changes in v2:
- Use interrupts-extended. (Konrad)
- Dropped QUESTION prefix, as it's verified this settings work.
- Added compatible for OnePlus 6 based on schematics.
- Corrected axolotl NFC compatible based on information from Alexander (SHIFT).
- Link to v1: https://lore.kernel.org/r/20260322-oneplus-nfc-v1-0-5f22f544f0e2@ixit.cz
---
David Heidelberg (5):
dt-bindings: nfc: nxp,nci: Document PN557 compatible
arm64: dts: qcom: sdm845-oneplus: Enable NFC
arm64: dts: qcom: sdm845-shift-axolotl: Correct touchscreen sleep state
arm64: dts: qcom: sdm845-shift-axolotl: Enable NFC
arm64: dts: qcom: sdm845-google-common: Enable NFC
.../devicetree/bindings/net/nfc/nxp,nci.yaml | 1 +
arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 31 ++++++++++++
.../arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 57 ++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 54 +++++++++++++++++++-
4 files changed, 142 insertions(+), 1 deletion(-)
---
base-commit: cc13002a9f984d37906e9476f3e532a8cdd126f5
change-id: 20251118-oneplus-nfc-c00ef1cdfa9b
Best regards,
--
David Heidelberg <david@ixit.cz>
^ permalink raw reply
* [PATCH v3 1/5] dt-bindings: nfc: nxp,nci: Document PN557 compatible
From: David Heidelberg via B4 Relay @ 2026-04-03 13:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Martinz, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Casey Connolly,
Alexander Martinz
Cc: Petr Hodina, biemster, netdev, linux-arm-msm, oe-linux-nfc,
devicetree, linux-kernel, phone-devel, Krzysztof Kozlowski,
David Heidelberg
In-Reply-To: <20260403-oneplus-nfc-v3-0-fbdce57d63c1@ixit.cz>
From: David Heidelberg <david@ixit.cz>
The PN557 uses the same hardware as the PN553 but ships with
firmware compliant with NCI 2.0.
Document PN557 as a compatible device.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml b/Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml
index 364b361511808..4f3847f64983b 100644
--- a/Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml
+++ b/Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml
@@ -18,6 +18,7 @@ properties:
- nxp,nq310
- nxp,pn547
- nxp,pn553
+ - nxp,pn557
- const: nxp,nxp-nci-i2c
enable-gpios:
--
2.53.0
^ permalink raw reply related
* Re: [PATCH net-next v3 1/3] dt-bindings: net: pse-pd: add poll-interval-ms property
From: Carlo Szelinsky @ 2026-04-03 13:51 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Oleksij Rempel, Kory Maincent, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, netdev, devicetree,
linux-kernel, linux-leds, Carlo Szelinsky
In-Reply-To: <20260330-spiritual-placid-jackal-cd4269@quoll>
Hi Krzysztof,
Thanks for the review.
The idea was to let boards tune the poll rate in case I2C bus load
matters, but you're right - that's a driver decision, not a hardware
property. The controller either has an IRQ or it doesn't, and how
often we poll is up to the driver.
I'll drop this patch and the of_property_read_u32() call in patch 2,
and just hardcode the 500ms default in the driver.
Does that work for you? Happy to send v4 with that change.
Thanks,
Carlo
^ permalink raw reply
* RE: [PATCH net] net: phy: micrel: Fix MMD register access during SPD in ksz9131_resume()
From: Ovidiu Panait @ 2026-04-03 13:50 UTC (permalink / raw)
To: Biju Das, andrew@lunn.ch, hkallweit1@gmail.com,
linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
In-Reply-To: <TYCPR01MB113320392754A3B42F78A9FC5865EA@TYCPR01MB11332.jpnprd01.prod.outlook.com>
> >
> > Hi,
> >
> > >
> > > Hi Ovidiu Panait,
> > >
> > > Thanks for the patch.
> > >
> > > > -----Original Message-----
> > > > From: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > > > Sent: 03 April 2026 12:18
> > > > Subject: [PATCH net] net: phy: micrel: Fix MMD register access
> > > > during
> > > SPD in ksz9131_resume()
> > > >
> > > > During system suspend, phy_suspend() puts the PHY into Software
> > > > Power-
> > > Down
> > > > (SPD) by setting the BMCR_PDOWN bit in MII_BMCR. According to the
> > > KSZ9131 datasheet, MMD register
> > > > access is restricted during SPD:
> > > >
> > > > - Only access to the standard registers (0 through 31) is
> supported.
> > > > - Access to MMD address spaces other than MMD address space 1 is
> > > > possible if the spd_clock_gate_override bit is set.
> > > > - Access to MMD address space 1 is not possible.
> > > >
> > > > However, ksz9131_resume() calls ksz9131_config_rgmii_delay() before
> > > > kszphy_resume() clears BMCR_PDOWN. This means MMD registers are
> > > > accessed
> > > while the PHY is still in SPD,
> > > > contrary to the datasheet.
> > >
> > > SPD mode: This mode is used to power down the device when it is not in
> > > use after power-up.
> > > Previous register settings are maintained during and
> > > following the removal of SPD.
> > >
> > > Suspend to Idle case, it is in SPD mode and the MMD register values
> > > are retained.
> > >
> >
> > On resume from s2idle, ksz9131_resume() calls
> ksz9131_config_rgmii_delay() which does MMD accesses,
> > while the PHY is in SPD. According to the datasheet, it shouldn't
> happen. See commit e398822c4751
> > ("net: phy: micrel: populate .soft_reset for KSZ9131") which fixes the
> same issue.
>
> On my board, while s2idle in SPD mode, it does not hang. The datasheet
> does not explain
> the behaviour when it is SPD mode. But it states that it retains all
> previous register values
> when it is out of SPD mode.
>
According to the KSZ9131 datasheet ([1]):
4.17.3 SOFTWARE POWER-DOWN MODE (SPD)
...
The following remain operational during SPD:
MII Management Interface
- Only access to the standard registers (0 through 31) is supported.
- Access to MMD address spaces other than MMD address space 1 is
possible if the spd_clock_gate_override bit is set.
- Access to MMD address space 1 is not possible.
The spd_clock_gate_override bit is not used in the KSZ9131 driver.
While the datasheet does not specify exactly what happens if registers
from an unsupported address space are accessed while the PHY is in SPD,
I think it is correct for the driver to not do it in the first place.
[1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/00002841D.pdf
Thanks,
Ovidiu
> >
> > > But in Suspend to RAM, PHY loses power and the reset value of Power
> > > Down bit 0 (ie normal mode), there is no restriction for accessing MMD
> > > registers in this mode.
> > >
> >
> > If the PHY loses power, it loses all the configuration that was done by
> ksz9131_config_init(). Right
> > now, only the RGMII delays are restored, which is a subset of the
> configurations done by
> > ksz9131_config_init().
>
> I agree, Only RZ/G3E reported this issue and with configuring only delays,
> it worked.
>
> Calling ksz9131_config_init() restores more MMD registers or call
> phy_init() like this patch.
>
> Cheers,
> Biju
^ permalink raw reply
* Re: [PATCH net-next] eth: remove the driver for acenic / tigon1&2
From: Gary Guo @ 2026-04-03 13:50 UTC (permalink / raw)
To: Jakub Kicinski, davem
Cc: netdev, edumazet, pabeni, andrew+netdev, horms, jes, chenhuacai,
kernel, tsbogend, James.Bottomley, deller, maddy, mpe, npiggin,
chleroy, hca, gor, agordeev, borntraeger, svens, bhelgaas, dakr,
kwilczynski, ojeda, boqun, gary, bjorn3_gh, lossin, a.hindborg,
aliceryhl, tmgross, ebiggers, ardb, tiwai, tytso, enelsonmoore,
martin.petersen, jirislaby, gregkh, geert, herbert, vineethr,
lirongqing, kshk, vadim.fedorenko, dong100, wangruikang,
hkallweit1, kees, loongarch, linux-mips, linux-parisc,
linuxppc-dev, linux-s390, linux-pci, rust-for-linux
In-Reply-To: <20260402183029.1236713-1-kuba@kernel.org>
On Thu Apr 2, 2026 at 7:30 PM BST, Jakub Kicinski wrote:
> The entire git history for this driver looks like tree-wide
> and automated cleanups. There's even more coming now with
> AI, so let's try to delete it instead.
>
> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
> ---
> CC: jes@trained-monkey.org
> CC: chenhuacai@kernel.org
> CC: kernel@xen0n.name
> CC: tsbogend@alpha.franken.de
> CC: James.Bottomley@HansenPartnership.com
> CC: deller@gmx.de
> CC: maddy@linux.ibm.com
> CC: mpe@ellerman.id.au
> CC: npiggin@gmail.com
> CC: chleroy@kernel.org
> CC: hca@linux.ibm.com
> CC: gor@linux.ibm.com
> CC: agordeev@linux.ibm.com
> CC: borntraeger@linux.ibm.com
> CC: svens@linux.ibm.com
> CC: bhelgaas@google.com
> CC: dakr@kernel.org
> CC: kwilczynski@kernel.org
> CC: ojeda@kernel.org
> CC: boqun@kernel.org
> CC: gary@garyguo.net
> CC: bjorn3_gh@protonmail.com
> CC: lossin@kernel.org
> CC: a.hindborg@kernel.org
> CC: aliceryhl@google.com
> CC: tmgross@umich.edu
> CC: ebiggers@google.com
> CC: ardb@kernel.org
> CC: tiwai@suse.de
> CC: tytso@mit.edu
> CC: enelsonmoore@gmail.com
> CC: martin.petersen@oracle.com
> CC: jirislaby@kernel.org
> CC: gregkh@linuxfoundation.org
> CC: geert@linux-m68k.org
> CC: herbert@gondor.apana.org.au
> CC: vineethr@linux.ibm.com
> CC: lirongqing@baidu.com
> CC: kshk@linux.ibm.com
> CC: vadim.fedorenko@linux.dev
> CC: dong100@mucse.com
> CC: wangruikang@iscas.ac.cn
> CC: hkallweit1@gmail.com
> CC: kees@kernel.org
> CC: loongarch@lists.linux.dev
> CC: linux-mips@vger.kernel.org
> CC: linux-parisc@vger.kernel.org
> CC: linuxppc-dev@lists.ozlabs.org
> CC: linux-s390@vger.kernel.org
> CC: linux-pci@vger.kernel.org
> CC: rust-for-linux@vger.kernel.org
> ---
> MAINTAINERS | 6 -
> drivers/net/ethernet/Kconfig | 1 -
> drivers/net/ethernet/alteon/Kconfig | 47 -
> drivers/net/ethernet/Makefile | 1 -
> drivers/net/ethernet/alteon/Makefile | 6 -
> drivers/net/ethernet/alteon/acenic.h | 791 -----
> include/linux/pci_ids.h | 2 -
> drivers/net/ethernet/alteon/acenic.c | 3178 -------------------
> arch/loongarch/configs/loongson32_defconfig | 1 -
> arch/loongarch/configs/loongson64_defconfig | 1 -
> arch/mips/configs/cavium_octeon_defconfig | 1 -
> arch/mips/configs/loongson2k_defconfig | 1 -
> arch/mips/configs/loongson3_defconfig | 1 -
> arch/mips/configs/malta_qemu_32r6_defconfig | 1 -
> arch/mips/configs/maltaaprp_defconfig | 1 -
> arch/mips/configs/maltasmvp_defconfig | 1 -
> arch/mips/configs/maltasmvp_eva_defconfig | 1 -
> arch/mips/configs/maltaup_defconfig | 1 -
> arch/mips/configs/mtx1_defconfig | 1 -
> arch/parisc/configs/generic-32bit_defconfig | 1 -
> arch/parisc/configs/generic-64bit_defconfig | 1 -
> arch/powerpc/configs/44x/akebono_defconfig | 1 -
> arch/powerpc/configs/g5_defconfig | 2 -
> arch/powerpc/configs/powernv_defconfig | 2 -
> arch/powerpc/configs/ppc64_defconfig | 2 -
> arch/powerpc/configs/ppc64e_defconfig | 2 -
> arch/powerpc/configs/ppc6xx_defconfig | 1 -
> arch/powerpc/configs/skiroot_defconfig | 2 -
> arch/s390/configs/debug_defconfig | 1 -
> arch/s390/configs/defconfig | 1 -
> rust/kernel/pci/id.rs | 1 -
> 31 files changed, 4060 deletions(-)
> delete mode 100644 drivers/net/ethernet/alteon/Kconfig
> delete mode 100644 drivers/net/ethernet/alteon/Makefile
> delete mode 100644 drivers/net/ethernet/alteon/acenic.h
> delete mode 100644 drivers/net/ethernet/alteon/acenic.c
>
> [...]
>
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 406abf629be2..8608361fac95 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -1809,8 +1809,6 @@
> /* formerly Platform Tech */
> #define PCI_DEVICE_ID_ESS_ESS0100 0x0100
>
> -#define PCI_VENDOR_ID_ALTEON 0x12ae
> -
> #define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4
> #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001
> #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002
>
> [...]
>
> diff --git a/rust/kernel/pci/id.rs b/rust/kernel/pci/id.rs
> index 50005d176561..dc2035a4c175 100644
> --- a/rust/kernel/pci/id.rs
> +++ b/rust/kernel/pci/id.rs
> @@ -428,7 +428,6 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
> TRANSMETA = bindings::PCI_VENDOR_ID_TRANSMETA, // 0x1279
> ROCKWELL = bindings::PCI_VENDOR_ID_ROCKWELL, // 0x127A
> ITE = bindings::PCI_VENDOR_ID_ITE, // 0x1283
> - ALTEON = bindings::PCI_VENDOR_ID_ALTEON, // 0x12ae
> NVIDIA_SGS = bindings::PCI_VENDOR_ID_NVIDIA_SGS, // 0x12d2
> PERICOM = bindings::PCI_VENDOR_ID_PERICOM, // 0x12D8
> AUREAL = bindings::PCI_VENDOR_ID_AUREAL, // 0x12eb
Does the PCI ID needs to be removed? There was a similar change that I recalled
and the discussion eventually leads to ID not being removed.
https://lore.kernel.org/all/20260123033233.16906-1-enelsonmoore@gmail.com/
That said, if the decision is to remove the IDs, then the Rust change is okay to
me
Acked-by: Gary Guo <gary@garyguo.net> # Rust
Best,
Gary
^ permalink raw reply
* Re: [PATCH net-next v5 7/9] selftests: drivers: hw: move to KTAP output
From: Ioana Ciornei @ 2026-04-03 13:46 UTC (permalink / raw)
To: Paolo Abeni
Cc: netdev, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Simon Horman, linux-kernel, petrm, willemb,
linux-kselftest
In-Reply-To: <5b7faeab-77b5-4a3c-a717-5a80f5e76a31@redhat.com>
On Thu, Apr 02, 2026 at 12:10:09PM +0200, Paolo Abeni wrote:
> On 3/30/26 5:29 PM, Ioana Ciornei wrote:
> > diff --git a/tools/testing/selftests/drivers/net/hw/ethtool_rmon.sh b/tools/testing/selftests/drivers/net/hw/ethtool_rmon.sh
> > index f290ce1832f1..ed81bdc33536 100755
> > --- a/tools/testing/selftests/drivers/net/hw/ethtool_rmon.sh
> > +++ b/tools/testing/selftests/drivers/net/hw/ethtool_rmon.sh
> > @@ -11,10 +11,12 @@ ALL_TESTS="
> > NUM_NETIFS=2
> > lib_dir=$(dirname "$0")
> > source "$lib_dir"/../../../net/forwarding/lib.sh
> > +source "$lib_dir"/../../../kselftest/ktap_helpers.sh
>
> AI review noted:
> ---
> Will this test work correctly after installation? The test sources
> ktap_helpers.sh but the file doesn't appear to be included in the
> Makefile's TEST_INCLUDES variable.
>
> Looking at tools/testing/selftests/drivers/net/hw/Makefile, when
> 'make install' is run, only files listed in TEST_PROGS, TEST_FILES,
> and TEST_INCLUDES are copied to the installation directory. Files
> referenced via 'source' need to be in TEST_INCLUDES to be available
> at runtime.
>
> Without adding '../../../kselftest/ktap_helpers.sh' to TEST_INCLUDES,
> the test will fail with 'No such file or directory' when run from an
> installed location.
Now that I actually looked at this, I don't think that adding
ktap_helpers.sh in TEST_INCLUDES is actually needed.
tools/testing/selftests/Makefile installs ktap_helpers.sh irrespective
of it being included in any TEST_INCLUDES.
install: all
ifdef INSTALL_PATH
@# Ask all targets to install their files
mkdir -p $(INSTALL_PATH)/kselftest
install -m 744 kselftest/module.sh $(INSTALL_PATH)/kselftest/
install -m 744 kselftest/runner.sh $(INSTALL_PATH)/kselftest/
install -m 744 kselftest/prefix.pl $(INSTALL_PATH)/kselftest/
install -m 744 kselftest/ktap_helpers.sh $(INSTALL_PATH)/kselftest/
I tested this and even if I only install drivers/net/hw I still get
ktap_helpers.sh in the install path.
Ioana
^ permalink raw reply
* Re: [PATCH iwl-next] ixgbe: fix cls_u32 nexthdr path returning success when no entry installed
From: Simon Horman @ 2026-04-03 13:46 UTC (permalink / raw)
To: Aleksandr Loktionov
Cc: intel-wired-lan, anthony.l.nguyen, netdev, Marcin Szycik
In-Reply-To: <20260327073046.134085-8-aleksandr.loktionov@intel.com>
On Fri, Mar 27, 2026 at 08:30:42AM +0100, Aleksandr Loktionov wrote:
> ixgbe_configure_clsu32() returns 0 (success) after the nexthdr loop
> even when ixgbe_clsu32_build_input() fails for every candidate entry
> and no jump-table slot is actually programmed. Callers that test the
> return value would then falsely believe the filter was installed.
>
> The variable 'err' already tracks the last ixgbe_clsu32_build_input()
> return value; if the loop completes with a successful break, err is 0.
> If all attempts failed, err holds the last failure code. Change the
> unconditional 'return 0' to 'return err' so errors are propagated
> correctly.
>
> Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
> Reviewed-by: Marcin Szycik <marcin.szycik@linux.intel.com>
This feels like a bug fix that should be routed via iwl-net with
a Fixes tag and some description of the user-visible effect
of this bug.
Else, please clearly state in the commit message that this is not a bug.
...
^ permalink raw reply
* [PATCH net v2] net: airoha: Add dma_rmb() and READ_ONCE() in airoha_qdma_rx_process()
From: Lorenzo Bianconi @ 2026-04-03 13:41 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Lorenzo Bianconi
Cc: Xuegang Lu, linux-arm-kernel, linux-mediatek, netdev
Add missing dma_rmb() in airoha_qdma_rx_process routine to make sure the
DMA read operations are completed when the NIC reports the processing on
the current descriptor is done. Moreover, add missing READ_ONCE() in
airoha_qdma_rx_process() for DMA descriptor control fields in order to
avoid any compiler reordering.
Fixes: 23020f0493270 ("net: airoha: Introduce ethernet support for EN7581 SoC")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
Changes in v2:
- Use msg1 in airoha_qdma_get_gdm_port() signature to avoid missing
READ_ONCE().
- Link to v1: https://lore.kernel.org/r/20260402-airoha_qdma_rx_process-fix-reordering-v1-1-53278474f062@kernel.org
---
drivers/net/ethernet/airoha/airoha_eth.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 95ba99b89428..f1843bc5b991 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -581,10 +581,9 @@ static int airoha_qdma_fill_rx_queue(struct airoha_queue *q)
return nframes;
}
-static int airoha_qdma_get_gdm_port(struct airoha_eth *eth,
- struct airoha_qdma_desc *desc)
+static int airoha_qdma_get_gdm_port(struct airoha_eth *eth, u32 msg1)
{
- u32 port, sport, msg1 = le32_to_cpu(desc->msg1);
+ u32 port, sport;
sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1);
switch (sport) {
@@ -612,15 +611,17 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
while (done < budget) {
struct airoha_queue_entry *e = &q->entry[q->tail];
struct airoha_qdma_desc *desc = &q->desc[q->tail];
- u32 hash, reason, msg1 = le32_to_cpu(desc->msg1);
- struct page *page = virt_to_head_page(e->buf);
- u32 desc_ctrl = le32_to_cpu(desc->ctrl);
+ u32 hash, reason, msg1, desc_ctrl;
struct airoha_gdm_port *port;
int data_len, len, p;
+ struct page *page;
+ desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
if (!(desc_ctrl & QDMA_DESC_DONE_MASK))
break;
+ dma_rmb();
+
q->tail = (q->tail + 1) % q->ndesc;
q->queued--;
@@ -633,10 +634,12 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
if (!len || data_len < len)
goto free_frag;
- p = airoha_qdma_get_gdm_port(eth, desc);
+ msg1 = le32_to_cpu(READ_ONCE(desc->msg1));
+ p = airoha_qdma_get_gdm_port(eth, msg1);
if (p < 0 || !eth->ports[p])
goto free_frag;
+ page = virt_to_head_page(e->buf);
port = eth->ports[p];
if (!q->skb) { /* first buffer */
q->skb = napi_build_skb(e->buf, q->buf_size);
@@ -670,8 +673,8 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
* DMA descriptor. Report DSA tag to the DSA stack
* via skb dst info.
*/
- u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG,
- le32_to_cpu(desc->msg0));
+ u32 msg0 = le32_to_cpu(READ_ONCE(desc->msg0));
+ u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG, msg0);
if (sptag < ARRAY_SIZE(port->dsa_meta) &&
port->dsa_meta[sptag])
---
base-commit: ec7067e661193403a7a00980bda8612db5954142
change-id: 20260402-airoha_qdma_rx_process-fix-reordering-722308255b65
Best regards,
--
Lorenzo Bianconi <lorenzo@kernel.org>
^ permalink raw reply related
* Re: [PATCH iwl-next] ixgbe: use int instead of u32 for error code variables
From: Simon Horman @ 2026-04-03 13:41 UTC (permalink / raw)
To: Aleksandr Loktionov; +Cc: intel-wired-lan, anthony.l.nguyen, netdev
In-Reply-To: <20260327073046.134085-9-aleksandr.loktionov@intel.com>
On Fri, Mar 27, 2026 at 08:30:43AM +0100, Aleksandr Loktionov wrote:
> The variables used to store return values of kernel and driver functions
> throughout the ixgbe driver are declared as u32 in several places. Such
> functions return negative errno values on error (e.g. -EIO, -EFAULT),
> which are sign-extended negative integers. Storing them in an unsigned
> u32 silently wraps the value: -EIO (0xFFFFFFF7) stored in u32 becomes a
> large positive number, so any "if (status)" truthiness check still works
> by accident, but comparisons against specific negative error codes or
> propagation up the call stack would produce wrong results.
>
> In the Linux kernel, u32 is reserved for fixed-width quantities used in
> hardware interfaces or protocol structures. Using it for generic error
> codes misleads reviewers into thinking the value is hardware-constrained.
>
> Change all such local variables from u32 to int driver-wide: one in
> ixgbe_main.c (ixgbe_resume), three in ixgbe_phy.c
> (ixgbe_identify_phy_generic, ixgbe_tn_check_overtemp,
> ixgbe_set_copper_phy_power), and six in ixgbe_x550.c
> (ixgbe_check_link_t_X550em, ixgbe_get_lasi_ext_t_x550em,
> ixgbe_enable_lasi_ext_t_x550em, ixgbe_handle_lasi_ext_t_x550em,
> ixgbe_ext_phy_t_x550em_get_link, ixgbe_setup_internal_phy_t_x550em).
>
> No functional change.
>
> Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Nice cleanup, thanks.
Reviewed-by: Simon Horman <horms@kernel.org>
^ permalink raw reply
* Re: [PATCH net] net: airoha: Add dma_rmb() and READ_ONCE() in airoha_qdma_rx_process()
From: Lorenzo Bianconi @ 2026-04-03 13:41 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni
Cc: Xuegang Lu, linux-arm-kernel, linux-mediatek, netdev
In-Reply-To: <20260402-airoha_qdma_rx_process-fix-reordering-v1-1-53278474f062@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 3122 bytes --]
> Add missing dma_rmb() in airoha_qdma_rx_process routine to make sure the
> DMA read operations are completed when the NIC reports the processing on
> the current descriptor is done. Moreover, add missing READ_ONCE() in
> airoha_qdma_rx_process() for DMA descriptor control fields in order to
> avoid any compiler reordering.
>
> Fixes: 23020f0493270 ("net: airoha: Introduce ethernet support for EN7581 SoC")
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
> drivers/net/ethernet/airoha/airoha_eth.c | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
Please drop this version, I will post v2 to add a missing READ_ONCE() for
airoha_qdma_get_gdm_port().
Regards,
Lorenzo
>
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 95ba99b89428e4cafb91ff7813e43ffeb38e6d9b..29dea8b35f64bfdcf88bc09fd711e0d8b4f7b6fa 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -612,15 +612,17 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
> while (done < budget) {
> struct airoha_queue_entry *e = &q->entry[q->tail];
> struct airoha_qdma_desc *desc = &q->desc[q->tail];
> - u32 hash, reason, msg1 = le32_to_cpu(desc->msg1);
> - struct page *page = virt_to_head_page(e->buf);
> - u32 desc_ctrl = le32_to_cpu(desc->ctrl);
> + u32 hash, reason, msg1, desc_ctrl;
> struct airoha_gdm_port *port;
> int data_len, len, p;
> + struct page *page;
>
> + desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
> if (!(desc_ctrl & QDMA_DESC_DONE_MASK))
> break;
>
> + dma_rmb();
> +
> q->tail = (q->tail + 1) % q->ndesc;
> q->queued--;
>
> @@ -637,6 +639,7 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
> if (p < 0 || !eth->ports[p])
> goto free_frag;
>
> + page = virt_to_head_page(e->buf);
> port = eth->ports[p];
> if (!q->skb) { /* first buffer */
> q->skb = napi_build_skb(e->buf, q->buf_size);
> @@ -670,8 +673,8 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
> * DMA descriptor. Report DSA tag to the DSA stack
> * via skb dst info.
> */
> - u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG,
> - le32_to_cpu(desc->msg0));
> + u32 msg0 = le32_to_cpu(READ_ONCE(desc->msg0));
> + u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG, msg0);
>
> if (sptag < ARRAY_SIZE(port->dsa_meta) &&
> port->dsa_meta[sptag])
> @@ -679,6 +682,7 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
> &port->dsa_meta[sptag]->dst);
> }
>
> + msg1 = le32_to_cpu(READ_ONCE(desc->msg1));
> hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1);
> if (hash != AIROHA_RXD4_FOE_ENTRY)
> skb_set_hash(q->skb, jhash_1word(hash, 0),
>
> ---
> base-commit: ec7067e661193403a7a00980bda8612db5954142
> change-id: 20260402-airoha_qdma_rx_process-fix-reordering-722308255b65
>
> Best regards,
> --
> Lorenzo Bianconi <lorenzo@kernel.org>
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [Intel-wired-lan] [PATCH iwl-next] ixgbe: call ixgbe_setup_fc() before fc_enable() after NVM update
From: Simon Horman @ 2026-04-03 13:39 UTC (permalink / raw)
To: aleksandr.loktionov
Cc: Simon Horman, intel-wired-lan, netdev, anthony.l.nguyen
In-Reply-To: <20260327073046.134085-6-aleksandr.loktionov@intel.com>
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
ixgbe: call ixgbe_setup_fc() before fc_enable() after NVM update
During an NVM update the PHY reset clears the Technology Ability Field
(IEEE 802.3 clause 37 register 7.10) back to hardware defaults. When
the driver subsequently calls only hw->mac.ops.fc_enable() the SRRCTL
register is recalculated from the stale autonegotiated capability bits,
which the MDD (Malicious Driver Detect) logic treats as an invalid
change and halts traffic on the PF.
Fix by calling ixgbe_setup_fc() immediately before fc_enable() in
ixgbe_watchdog_update_link() so that flow-control autoneg and the
PHY registers are re-programmed in the correct order after any reset.
> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
> index 0bc806aaed90..96e912371d9a 100644
> --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
> @@ -8029,6 +8029,12 @@ static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
> pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
>
> if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
> + if (hw->mac.ops.setup_fc) {
> + int err = hw->mac.ops.setup_fc(hw);
> +
> + if (err)
> + e_warn(drv, "setup_fc failed: %d\n", err);
> + }
What happens if setup_fc() fails here? The patch adds this call to fix
MDD issues caused by stale PHY autoneg state after NVM updates.
However, if setup_fc() returns an error, the code only logs a warning
and continues:
if (hw->mac.ops.setup_fc) {
int err = hw->mac.ops.setup_fc(hw);
if (err)
e_warn(drv, "setup_fc failed: %d\n", err);
}
hw->mac.ops.fc_enable(hw);
Since fc_enable() relies on hw->fc.current_mode being properly set by
the autoneg process initiated by setup_fc(), calling it after a
setup_fc failure means it operates on the same stale state the patch
was meant to fix.
Could this leave a residual bug where MDD can still trigger and halt
traffic if setup_fc fails?
> hw->mac.ops.fc_enable(hw);
> ixgbe_set_rx_drop_en(adapter);
> }
^ permalink raw reply
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