* [PATCH 1/1] nfc: llcp: fix use-after-free in llcp_sock_release()
From: Lee Jones @ 2026-04-29 13:22 UTC (permalink / raw)
To: lee, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Simon Horman, Kees Cook, netdev, linux-kernel
llcp_sock_release() unconditionally unlinks the socket from the local
sockets list. However, if the socket is still in connecting state, it
is on the connecting list.
Fix this by checking the socket state and unlinking from the correct list.
Signed-off-by: Lee Jones <lee@kernel.org>
---
net/nfc/llcp_sock.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/net/nfc/llcp_sock.c b/net/nfc/llcp_sock.c
index f1be1e84f6653..feab29fc62f44 100644
--- a/net/nfc/llcp_sock.c
+++ b/net/nfc/llcp_sock.c
@@ -633,6 +633,8 @@ static int llcp_sock_release(struct socket *sock)
if (sock->type == SOCK_RAW)
nfc_llcp_sock_unlink(&local->raw_sockets, sk);
+ else if (sk->sk_state == LLCP_CONNECTING)
+ nfc_llcp_sock_unlink(&local->connecting_sockets, sk);
else
nfc_llcp_sock_unlink(&local->sockets, sk);
--
2.54.0.545.g6539524ca2-goog
^ permalink raw reply related
* Re: [PATCH v4 04/15] firmware: qcom: Add a PAS TEE service
From: Mukesh Ojha @ 2026-04-29 13:20 UTC (permalink / raw)
To: Sumit Garg
Cc: andersson, konradybcio, linux-arm-msm, devicetree, dri-devel,
freedreno, linux-media, netdev, linux-wireless, ath12k,
linux-remoteproc, robh, krzk+dt, conor+dt, robin.clark, sean,
akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, pavan.kondeti, jorge.ramirez,
tonyh, vignesh.viswanathan, srinivas.kandagatla, amirreza.zarrabi,
jens.wiklander, op-tee, apurupa, skare, linux-kernel, Sumit Garg
In-Reply-To: <20260427095603.1157963-5-sumit.garg@kernel.org>
On Mon, Apr 27, 2026 at 03:25:52PM +0530, Sumit Garg wrote:
> From: Sumit Garg <sumit.garg@oss.qualcomm.com>
>
> Add support for Peripheral Authentication Service (PAS) driver based
> on TEE bus with OP-TEE providing the backend PAS service implementation.
>
> The TEE PAS service ABI is designed to be extensible with additional API
> as PTA_QCOM_PAS_CAPABILITIES. This allows to accommodate any future
> extensions of the PAS service needed while still maintaining backwards
> compatibility.
>
> Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
> ---
> drivers/firmware/qcom/Kconfig | 10 +
> drivers/firmware/qcom/Makefile | 1 +
> drivers/firmware/qcom/qcom_pas_tee.c | 479 +++++++++++++++++++++++++++
> 3 files changed, 490 insertions(+)
> create mode 100644 drivers/firmware/qcom/qcom_pas_tee.c
>
> diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig
> index 9a12ae2b639d..300b3a1bd178 100644
> --- a/drivers/firmware/qcom/Kconfig
> +++ b/drivers/firmware/qcom/Kconfig
> @@ -14,6 +14,16 @@ config QCOM_PAS
> backends plugged in whether it's an SCM implementation or a proper
> TEE bus based PAS service implementation.
>
> +config QCOM_PAS_TEE
> + tristate
> + select QCOM_PAS
> + depends on TEE
> + depends on !CPU_BIG_ENDIAN
> + default m if ARCH_QCOM
> + help
> + Enable the generic Peripheral Authentication Service (PAS) provided
> + by the firmware TEE implementation as the backend.
> +
> config QCOM_SCM
> select QCOM_PAS
> select QCOM_TZMEM
> diff --git a/drivers/firmware/qcom/Makefile b/drivers/firmware/qcom/Makefile
> index dc5ab45f906a..48801d18f37b 100644
> --- a/drivers/firmware/qcom/Makefile
> +++ b/drivers/firmware/qcom/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_QCOM_TZMEM) += qcom_tzmem.o
> obj-$(CONFIG_QCOM_QSEECOM) += qcom_qseecom.o
> obj-$(CONFIG_QCOM_QSEECOM_UEFISECAPP) += qcom_qseecom_uefisecapp.o
> obj-$(CONFIG_QCOM_PAS) += qcom_pas.o
> +obj-$(CONFIG_QCOM_PAS_TEE) += qcom_pas_tee.o
> diff --git a/drivers/firmware/qcom/qcom_pas_tee.c b/drivers/firmware/qcom/qcom_pas_tee.c
> new file mode 100644
> index 000000000000..af73d0a68525
> --- /dev/null
> +++ b/drivers/firmware/qcom/qcom_pas_tee.c
> @@ -0,0 +1,479 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/of.h>
> +#include <linux/firmware/qcom/qcom_pas.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/tee_drv.h>
> +#include <linux/uuid.h>
> +
> +#include "qcom_pas.h"
> +
> +/*
> + * Peripheral Authentication Service (PAS) supported.
> + *
> + * [in] params[0].value.a: Unique 32bit remote processor identifier
> + */
> +#define TA_QCOM_PAS_IS_SUPPORTED 1
> +
> +/*
> + * PAS capabilities.
> + *
> + * [in] params[0].value.a: Unique 32bit remote processor identifier
> + * [out] params[1].value.a: PAS capability flags
> + */
> +#define TA_QCOM_PAS_CAPABILITIES 2
> +
> +/*
> + * PAS image initialization.
> + *
> + * [in] params[0].value.a: Unique 32bit remote processor identifier
> + * [in] params[1].memref: Loadable firmware metadata
> + */
> +#define TA_QCOM_PAS_INIT_IMAGE 3
> +
> +/*
> + * PAS memory setup.
> + *
> + * [in] params[0].value.a: Unique 32bit remote processor identifier
> + * [in] params[0].value.b: Relocatable firmware size
> + * [in] params[1].value.a: 32bit LSB relocatable firmware memory address
> + * [in] params[1].value.b: 32bit MSB relocatable firmware memory address
> + */
> +#define TA_QCOM_PAS_MEM_SETUP 4
> +
> +/*
> + * PAS get resource table.
> + *
> + * [in] params[0].value.a: Unique 32bit remote processor identifier
> + * [inout] params[1].memref: Resource table config
> + */
> +#define TA_QCOM_PAS_GET_RESOURCE_TABLE 5
> +
> +/*
> + * PAS image authentication and co-processor reset.
> + *
> + * [in] params[0].value.a: Unique 32bit remote processor identifier
> + * [in] params[0].value.b: Firmware size
> + * [in] params[1].value.a: 32bit LSB firmware memory address
> + * [in] params[1].value.b: 32bit MSB firmware memory address
> + * [in] params[2].memref: Optional fw memory space shared/lent
> + */
> +#define TA_QCOM_PAS_AUTH_AND_RESET 6
> +
> +/*
> + * PAS co-processor set suspend/resume state.
> + *
> + * [in] params[0].value.a: Unique 32bit remote processor identifier
> + * [in] params[0].value.b: Co-processor state identifier
> + */
> +#define TA_QCOM_PAS_SET_REMOTE_STATE 7
> +
> +/*
> + * PAS co-processor shutdown.
> + *
> + * [in] params[0].value.a: Unique 32bit remote processor identifier
> + */
> +#define TA_QCOM_PAS_SHUTDOWN 8
> +
> +#define TEE_NUM_PARAMS 4
> +
> +/**
> + * struct qcom_pas_tee_private - PAS service private data
> + * @dev: PAS service device.
> + * @ctx: TEE context handler.
> + * @session_id: PAS TA session identifier.
> + */
> +struct qcom_pas_tee_private {
> + struct device *dev;
> + struct tee_context *ctx;
> + u32 session_id;
> +};
> +
> +static bool qcom_pas_tee_supported(struct device *dev, u32 pas_id)
> +{
> + struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
> + struct tee_ioctl_invoke_arg inv_arg = {
> + .func = TA_QCOM_PAS_IS_SUPPORTED,
> + .session = data->session_id,
> + .num_params = TEE_NUM_PARAMS
> + };
> + struct tee_param param[4] = {
> + [0] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
> + .u.value.a = pas_id
> + }
> + };
> + int ret;
> +
> + ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
> + if (ret < 0 || inv_arg.ret != 0) {
> + dev_err(dev, "PAS not supported, pas_id: %d, ret: %d, err: 0x%x\n",
> + pas_id, ret, inv_arg.ret);
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static int qcom_pas_tee_init_image(struct device *dev, u32 pas_id,
> + const void *metadata, size_t size,
> + struct qcom_pas_context *ctx)
> +{
> + struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
> + struct tee_ioctl_invoke_arg inv_arg = {
> + .func = TA_QCOM_PAS_INIT_IMAGE,
> + .session = data->session_id,
> + .num_params = TEE_NUM_PARAMS
> + };
> + struct tee_param param[4] = {
> + [0] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
> + .u.value.a = pas_id
> + },
> + [1] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT,
> + }
> + };
> + struct tee_shm *mdata_shm;
> + u8 *mdata_buf = NULL;
> + int ret;
> +
> + mdata_shm = tee_shm_alloc_kernel_buf(data->ctx, size);
> + if (IS_ERR(mdata_shm)) {
> + dev_err(dev, "mdata_shm allocation failed\n");
> + return PTR_ERR(mdata_shm);
> + }
> +
> + mdata_buf = tee_shm_get_va(mdata_shm, 0);
> + if (IS_ERR(mdata_buf)) {
> + dev_err(dev, "mdata_buf get VA failed\n");
> + tee_shm_free(mdata_shm);
> + return PTR_ERR(mdata_buf);
> + }
> + memcpy(mdata_buf, metadata, size);
> +
> + param[1].u.memref.shm = mdata_shm;
> + param[1].u.memref.size = size;
> +
> + ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
> + if (ret < 0 || inv_arg.ret != 0) {
> + dev_err(dev, "PAS init image failed, pas_id: %d, ret: %d, err: 0x%x\n",
> + pas_id, ret, inv_arg.ret);
> + tee_shm_free(mdata_shm);
> + return ret ?: -EINVAL;
> + }
> +
> + if (ctx)
> + ctx->ptr = (void *)mdata_shm;
> + else
> + tee_shm_free(mdata_shm);
> +
> + return ret;
> +}
> +
> +static int qcom_pas_tee_mem_setup(struct device *dev, u32 pas_id,
> + phys_addr_t addr, phys_addr_t size)
> +{
> + struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
> + struct tee_ioctl_invoke_arg inv_arg = {
> + .func = TA_QCOM_PAS_MEM_SETUP,
> + .session = data->session_id,
> + .num_params = TEE_NUM_PARAMS
> + };
> + struct tee_param param[4] = {
> + [0] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
> + .u.value.a = pas_id,
> + .u.value.b = size,
> + },
> + [1] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
> + .u.value.a = lower_32_bits(addr),
> + .u.value.b = upper_32_bits(addr),
> + }
> + };
> + int ret;
> +
> + ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
> + if (ret < 0 || inv_arg.ret != 0) {
> + dev_err(dev, "PAS mem setup failed, pas_id: %d, ret: %d, err: 0x%x\n",
> + pas_id, ret, inv_arg.ret);
> + return ret ?: -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> +DEFINE_FREE(shm_free, struct tee_shm *, tee_shm_free(_T))
> +
> +static void *qcom_pas_tee_get_rsc_table(struct device *dev,
> + struct qcom_pas_context *ctx,
> + void *input_rt, size_t input_rt_size,
> + size_t *output_rt_size)
> +{
> + struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
> + struct tee_ioctl_invoke_arg inv_arg = {
> + .func = TA_QCOM_PAS_GET_RESOURCE_TABLE,
> + .session = data->session_id,
> + .num_params = TEE_NUM_PARAMS
> + };
> + struct tee_param param[4] = {
> + [0] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
> + .u.value.a = ctx->pas_id,
> + },
> + [1] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT,
> + .u.memref.size = input_rt_size,
> + }
> + };
> + void *rt_buf = NULL;
> + int ret;
> +
> + ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
> + if (ret < 0 || inv_arg.ret != 0) {
> + dev_err(dev, "PAS get RT failed, pas_id: %d, ret: %d, err: 0x%x\n",
> + ctx->pas_id, ret, inv_arg.ret);
> + return ret ? ERR_PTR(ret) : ERR_PTR(-EINVAL);
> + }
> +
> + if (param[1].u.memref.size) {
> + struct tee_shm *rt_shm __free(shm_free) =
> + tee_shm_alloc_kernel_buf(data->ctx,
> + param[1].u.memref.size);
> + void *rt_shm_va;
> +
> + if (IS_ERR(rt_shm)) {
> + dev_err(dev, "rt_shm allocation failed\n");
> + return rt_shm;
> + }
> +
> + rt_shm_va = tee_shm_get_va(rt_shm, 0);
> + if (IS_ERR(rt_shm_va)) {
> + dev_err(dev, "rt_shm get VA failed\n");
> + return ERR_CAST(rt_shm_va);
> + }
> + memcpy(rt_shm_va, input_rt, input_rt_size);
It is very obvious that every existing user will pass NULL as input_rt
and 0 as input_rt_size.
Are you not getting NULL pointer on this input_rt ? Ok, you may be not
getting because, input_rt_size == 0.
I hope, your backend implementation checks for this num == 0 and then
ignore input rt.
> +
> + param[1].u.memref.shm = rt_shm;
> + ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
> + if (ret < 0 || inv_arg.ret != 0) {
> + dev_err(dev, "PAS get RT failed, pas_id: %d, ret: %d, err: 0x%x\n",
> + ctx->pas_id, ret, inv_arg.ret);
> + return ret ? ERR_PTR(ret) : ERR_PTR(-EINVAL);
> + }
> +
> + if (param[1].u.memref.size) {
> + *output_rt_size = param[1].u.memref.size;
> + rt_buf = kmemdup(rt_shm_va, *output_rt_size, GFP_KERNEL);
> + if (!rt_buf)
> + return ERR_PTR(-ENOMEM);
> + }
> + }
> +
> + return rt_buf;
> +}
> +
> +static int __qcom_pas_tee_auth_and_reset(struct device *dev, u32 pas_id,
> + phys_addr_t mem_phys, size_t mem_size)
> +{
> + struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
> + struct tee_ioctl_invoke_arg inv_arg = {
> + .func = TA_QCOM_PAS_AUTH_AND_RESET,
> + .session = data->session_id,
> + .num_params = TEE_NUM_PARAMS
> + };
> + struct tee_param param[4] = {
> + [0] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
> + .u.value.a = pas_id,
> + .u.value.b = mem_size,
> + },
> + [1] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
> + .u.value.a = lower_32_bits(mem_phys),
> + .u.value.b = upper_32_bits(mem_phys),
> + },
> + /* Reserved for fw memory space to be shared or lent */
> + [2] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT,
> + }
> + };
> + int ret;
> +
> + ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
> + if (ret < 0 || inv_arg.ret != 0) {
> + dev_err(dev, "PAS auth reset failed, pas_id: %d, ret: %d, err: 0x%x\n",
> + pas_id, ret, inv_arg.ret);
> + return ret ?: -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> +static int qcom_pas_tee_auth_and_reset(struct device *dev, u32 pas_id)
> +{
> + return __qcom_pas_tee_auth_and_reset(dev, pas_id, 0, 0);
> +}
> +
> +static int qcom_pas_tee_prepare_and_auth_reset(struct device *dev,
> + struct qcom_pas_context *ctx)
> +{
> + return __qcom_pas_tee_auth_and_reset(dev, ctx->pas_id, ctx->mem_phys,
> + ctx->mem_size);
> +}
> +
> +static int qcom_pas_tee_set_remote_state(struct device *dev, u32 state,
> + u32 pas_id)
> +{
> + struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
> + struct tee_ioctl_invoke_arg inv_arg = {
> + .func = TA_QCOM_PAS_SET_REMOTE_STATE,
> + .session = data->session_id,
> + .num_params = TEE_NUM_PARAMS
> + };
> + struct tee_param param[4] = {
> + [0] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
> + .u.value.a = pas_id,
> + .u.value.b = state,
> + }
> + };
> + int ret;
> +
> + ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
> + if (ret < 0 || inv_arg.ret != 0) {
> + dev_err(dev, "PAS shutdown failed, pas_id: %d, ret: %d, err: 0x%x\n",
> + pas_id, ret, inv_arg.ret);
should be "PAS set remote state failed .."
> + return ret ?: -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> +static int qcom_pas_tee_shutdown(struct device *dev, u32 pas_id)
> +{
> + struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
> + struct tee_ioctl_invoke_arg inv_arg = {
> + .func = TA_QCOM_PAS_SHUTDOWN,
> + .session = data->session_id,
> + .num_params = TEE_NUM_PARAMS
> + };
> + struct tee_param param[4] = {
> + [0] = {
> + .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
> + .u.value.a = pas_id
> + }
> + };
> + int ret;
> +
> + ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
> + if (ret < 0 || inv_arg.ret != 0) {
> + dev_err(dev, "PAS shutdown failed, pas_id: %d, ret: %d, err: 0x%x\n",
> + pas_id, ret, inv_arg.ret);
> + return ret ?: -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> +static void qcom_pas_tee_metadata_release(struct device *dev,
> + struct qcom_pas_context *ctx)
> +{
> + struct tee_shm *mdata_shm = ctx->ptr;
> +
> + tee_shm_free(mdata_shm);
> +}
> +
> +static struct qcom_pas_ops qcom_pas_ops_tee = {
> + .drv_name = "qcom-pas-tee",
> + .supported = qcom_pas_tee_supported,
> + .init_image = qcom_pas_tee_init_image,
> + .mem_setup = qcom_pas_tee_mem_setup,
> + .get_rsc_table = qcom_pas_tee_get_rsc_table,
> + .auth_and_reset = qcom_pas_tee_auth_and_reset,
> + .prepare_and_auth_reset = qcom_pas_tee_prepare_and_auth_reset,
> + .set_remote_state = qcom_pas_tee_set_remote_state,
> + .shutdown = qcom_pas_tee_shutdown,
> + .metadata_release = qcom_pas_tee_metadata_release,
> +};
> +
> +static int optee_ctx_match(struct tee_ioctl_version_data *ver, const void *data)
> +{
> + return ver->impl_id == TEE_IMPL_ID_OPTEE;
> +}
> +
> +static int qcom_pas_tee_probe(struct tee_client_device *pas_dev)
> +{
> + struct device *dev = &pas_dev->dev;
> + struct qcom_pas_tee_private *data;
> + struct tee_ioctl_open_session_arg sess_arg = {
> + .clnt_login = TEE_IOCTL_LOGIN_REE_KERNEL
> + };
> + int ret, err = -ENODEV;
Most people prefer one line per variable..
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + data->ctx = tee_client_open_context(NULL, optee_ctx_match, NULL, NULL);
> + if (IS_ERR(data->ctx))
> + return -ENODEV;
> +
> + export_uuid(sess_arg.uuid, &pas_dev->id.uuid);
> + ret = tee_client_open_session(data->ctx, &sess_arg, NULL);
> + if (ret < 0 || sess_arg.ret != 0) {
> + dev_err(dev, "tee_client_open_session failed, ret: %d, err: 0x%x\n",
> + ret, sess_arg.ret);
> + err = ret ?: -EINVAL;
Only user of goto, we can close the context and return from here and
'err' not used.
tee_client_close_context(data->ctx);
return ret ?: -EINVAL;
> + goto out_ctx;
> + }
> +
> + data->session_id = sess_arg.session;
> + dev_set_drvdata(dev, data);
> + qcom_pas_ops_tee.dev = dev;
> + qcom_pas_ops_register(&qcom_pas_ops_tee);
> +
> + return ret;
> +out_ctx:
> + tee_client_close_context(data->ctx);
Return after two line does not look nice.
> +
> + return err;
> +}
> +
> +static void qcom_pas_tee_remove(struct tee_client_device *pas_dev)
> +{
> + struct device *dev = &pas_dev->dev;
> + struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
> +
> + qcom_pas_ops_unregister();
> + tee_client_close_session(data->ctx, data->session_id);
> + tee_client_close_context(data->ctx);
> +}
> +
> +static const struct tee_client_device_id qcom_pas_tee_id_table[] = {
> + {UUID_INIT(0xcff7d191, 0x7ca0, 0x4784,
> + 0xaf, 0x13, 0x48, 0x22, 0x3b, 0x9a, 0x4f, 0xbe)},
> + {}
> +};
> +MODULE_DEVICE_TABLE(tee, qcom_pas_tee_id_table);
> +
> +static struct tee_client_driver optee_pas_tee_driver = {
> + .probe = qcom_pas_tee_probe,
> + .remove = qcom_pas_tee_remove,
> + .id_table = qcom_pas_tee_id_table,
> + .driver = {
> + .name = "qcom-pas-tee",
> + },
> +};
> +
> +module_tee_client_driver(optee_pas_tee_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("Qualcomm PAS TEE driver");
> --
> 2.51.0
>
With above change,
Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
--
-Mukesh Ojha
^ permalink raw reply
* Re: [PATCH 7/9] Bluetooth: hci_sync: Add NVMEM-backed BD address retrieval
From: Andrew Lunn @ 2026-04-29 13:15 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Loic Poulain, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Jens Axboe,
Johannes Berg, Jeff Johnson, Marcel Holtmann,
Luiz Augusto von Dentz, Balakrishna Godavarthi, Rocky Liao,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Simon Horman, linux-mmc, devicetree, linux-kernel, linux-arm-msm,
linux-block, linux-wireless, ath10k, linux-bluetooth, netdev,
daniel
In-Reply-To: <CAMRc=Me9G9vd06a39vi_UrXCTkUtJQRogm2MqgnwLS_r3Thyzg@mail.gmail.com>
On Wed, Apr 29, 2026 at 10:53:13AM +0200, Bartosz Golaszewski wrote:
> On Tue, Apr 28, 2026 at 4:23 PM Loic Poulain
> <loic.poulain@oss.qualcomm.com> wrote:
> >
> > Some devices store the Bluetooth BD address in non-volatile
> > memory, which can be accessed through the NVMEM framework.
> > Similar to Ethernet or WiFi MAC addresses, add support for
> > reading the BD address from a 'local-bd-address' NVMEM cell.
> >
> > As with the device-tree provided BD address, add a quirk to
> > indicate whether a device or platform should attempt to read
> > the address from NVMEM when no valid in-chip address is present.
> > Also add a quirk to indicate if the address is stored in
> > big-endian byte order.
> >
> > Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> > ---
>
> Is there any reason why we can't extend the existing
> of_get_mac_address() with another property name and use it here? It
> already has support for mac addresses from nvmem.
Does it even need to be a different property name? Is a bluetooth MAC
address somehow different to an Ethernet MAC address? Isn't it just a
EUI-48, independent of it being Ethernet, Bluetooth, wifi, fddi, token
ring, homing pigeon?
Andrew
^ permalink raw reply
* [PATCH 2/2] pinctrl: qcom: Add Shikra pinctrl driver
From: Komal Bajaj @ 2026-04-29 13:11 UTC (permalink / raw)
To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Richard Cochran
Cc: linux-arm-msm, linux-gpio, devicetree, linux-kernel, netdev,
Komal Bajaj
In-Reply-To: <20260429-shikra-pinctrl-v1-0-1b4bb2b3a8d6@oss.qualcomm.com>
Add pinctrl driver for TLMM block found in Shikra SoC.
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
drivers/pinctrl/qcom/Kconfig.msm | 11 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-shikra.c | 1280 +++++++++++++++++++++++++++++++++
3 files changed, 1292 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm
index 836cdeca1006..c89b0e8790de 100644
--- a/drivers/pinctrl/qcom/Kconfig.msm
+++ b/drivers/pinctrl/qcom/Kconfig.msm
@@ -369,6 +369,17 @@ config PINCTRL_SDX75
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDX75 platform.
+config PINCTRL_SHIKRA
+ tristate "Qualcomm Technologies Inc Shikra pin controller driver"
+ depends on ARM64 || COMPILE_TEST
+ default ARCH_QCOM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
+ found on the Qualcomm Technologies Inc Shikra platform.
+ Say Y here to compile statically, or M here to compile it as a module.
+ If unsure, say N.
+
config PINCTRL_SM4450
tristate "Qualcomm Technologies Inc SM4450 pin controller driver"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 84bda3ada874..07c0d236d82f 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o
+obj-$(CONFIG_PINCTRL_SHIKRA) += pinctrl-shikra.o
obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o
obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
diff --git a/drivers/pinctrl/qcom/pinctrl-shikra.c b/drivers/pinctrl/qcom/pinctrl-shikra.c
new file mode 100644
index 000000000000..25acb74853d2
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-shikra.c
@@ -0,0 +1,1280 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-msm.h"
+
+#define REG_SIZE 0x1000
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
+ { \
+ .grp = PINCTRL_PINGROUP("gpio" #id, \
+ gpio##id##_pins, \
+ ARRAY_SIZE(gpio##id##_pins)), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9, \
+ msm_mux_##f10, \
+ msm_mux_##f11 /* egpio mode */ \
+ }, \
+ .nfuncs = 12, \
+ .ctl_reg = REG_SIZE * id, \
+ .io_reg = 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = 0x8 + REG_SIZE * id, \
+ .intr_status_reg = 0xc + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .egpio_enable = 12, \
+ .egpio_present = 11, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_wakeup_enable_bit = 7, \
+ .intr_wakeup_present_bit = 6, \
+ .intr_target_bit = 8, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .grp = PINCTRL_PINGROUP(#pg_name, \
+ pg_name##_pins, \
+ ARRAY_SIZE(pg_name##_pins)), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+#define UFS_RESET(pg_name, ctl, io) \
+ { \
+ .grp = PINCTRL_PINGROUP(#pg_name, \
+ pg_name##_pins, \
+ ARRAY_SIZE(pg_name##_pins)), \
+ .ctl_reg = ctl, \
+ .io_reg = io, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+static const struct pinctrl_pin_desc shikra_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+ PINCTRL_PIN(117, "GPIO_117"),
+ PINCTRL_PIN(118, "GPIO_118"),
+ PINCTRL_PIN(119, "GPIO_119"),
+ PINCTRL_PIN(120, "GPIO_120"),
+ PINCTRL_PIN(121, "GPIO_121"),
+ PINCTRL_PIN(122, "GPIO_122"),
+ PINCTRL_PIN(123, "GPIO_123"),
+ PINCTRL_PIN(124, "GPIO_124"),
+ PINCTRL_PIN(125, "GPIO_125"),
+ PINCTRL_PIN(126, "GPIO_126"),
+ PINCTRL_PIN(127, "GPIO_127"),
+ PINCTRL_PIN(128, "GPIO_128"),
+ PINCTRL_PIN(129, "GPIO_129"),
+ PINCTRL_PIN(130, "GPIO_130"),
+ PINCTRL_PIN(131, "GPIO_131"),
+ PINCTRL_PIN(132, "GPIO_132"),
+ PINCTRL_PIN(133, "GPIO_133"),
+ PINCTRL_PIN(134, "GPIO_134"),
+ PINCTRL_PIN(135, "GPIO_135"),
+ PINCTRL_PIN(136, "GPIO_136"),
+ PINCTRL_PIN(137, "GPIO_137"),
+ PINCTRL_PIN(138, "GPIO_138"),
+ PINCTRL_PIN(139, "GPIO_139"),
+ PINCTRL_PIN(140, "GPIO_140"),
+ PINCTRL_PIN(141, "GPIO_141"),
+ PINCTRL_PIN(142, "GPIO_142"),
+ PINCTRL_PIN(143, "GPIO_143"),
+ PINCTRL_PIN(144, "GPIO_144"),
+ PINCTRL_PIN(145, "GPIO_145"),
+ PINCTRL_PIN(146, "GPIO_146"),
+ PINCTRL_PIN(147, "GPIO_147"),
+ PINCTRL_PIN(148, "GPIO_148"),
+ PINCTRL_PIN(149, "GPIO_149"),
+ PINCTRL_PIN(150, "GPIO_150"),
+ PINCTRL_PIN(151, "GPIO_151"),
+ PINCTRL_PIN(152, "GPIO_152"),
+ PINCTRL_PIN(153, "GPIO_153"),
+ PINCTRL_PIN(154, "GPIO_154"),
+ PINCTRL_PIN(155, "GPIO_155"),
+ PINCTRL_PIN(156, "GPIO_156"),
+ PINCTRL_PIN(157, "GPIO_157"),
+ PINCTRL_PIN(158, "GPIO_158"),
+ PINCTRL_PIN(159, "GPIO_159"),
+ PINCTRL_PIN(160, "GPIO_160"),
+ PINCTRL_PIN(161, "GPIO_161"),
+ PINCTRL_PIN(162, "GPIO_162"),
+ PINCTRL_PIN(163, "GPIO_163"),
+ PINCTRL_PIN(164, "GPIO_164"),
+ PINCTRL_PIN(165, "GPIO_165"),
+ PINCTRL_PIN(166, "SDC1_RCLK"),
+ PINCTRL_PIN(167, "SDC1_CLK"),
+ PINCTRL_PIN(168, "SDC1_CMD"),
+ PINCTRL_PIN(169, "SDC1_DATA"),
+ PINCTRL_PIN(170, "SDC2_CLK"),
+ PINCTRL_PIN(171, "SDC2_CMD"),
+ PINCTRL_PIN(172, "SDC2_DATA"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+DECLARE_MSM_GPIO_PINS(108);
+DECLARE_MSM_GPIO_PINS(109);
+DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
+DECLARE_MSM_GPIO_PINS(114);
+DECLARE_MSM_GPIO_PINS(115);
+DECLARE_MSM_GPIO_PINS(116);
+DECLARE_MSM_GPIO_PINS(117);
+DECLARE_MSM_GPIO_PINS(118);
+DECLARE_MSM_GPIO_PINS(119);
+DECLARE_MSM_GPIO_PINS(120);
+DECLARE_MSM_GPIO_PINS(121);
+DECLARE_MSM_GPIO_PINS(122);
+DECLARE_MSM_GPIO_PINS(123);
+DECLARE_MSM_GPIO_PINS(124);
+DECLARE_MSM_GPIO_PINS(125);
+DECLARE_MSM_GPIO_PINS(126);
+DECLARE_MSM_GPIO_PINS(127);
+DECLARE_MSM_GPIO_PINS(128);
+DECLARE_MSM_GPIO_PINS(129);
+DECLARE_MSM_GPIO_PINS(130);
+DECLARE_MSM_GPIO_PINS(131);
+DECLARE_MSM_GPIO_PINS(132);
+DECLARE_MSM_GPIO_PINS(133);
+DECLARE_MSM_GPIO_PINS(134);
+DECLARE_MSM_GPIO_PINS(135);
+DECLARE_MSM_GPIO_PINS(136);
+DECLARE_MSM_GPIO_PINS(137);
+DECLARE_MSM_GPIO_PINS(138);
+DECLARE_MSM_GPIO_PINS(139);
+DECLARE_MSM_GPIO_PINS(140);
+DECLARE_MSM_GPIO_PINS(141);
+DECLARE_MSM_GPIO_PINS(142);
+DECLARE_MSM_GPIO_PINS(143);
+DECLARE_MSM_GPIO_PINS(144);
+DECLARE_MSM_GPIO_PINS(145);
+DECLARE_MSM_GPIO_PINS(146);
+DECLARE_MSM_GPIO_PINS(147);
+DECLARE_MSM_GPIO_PINS(148);
+DECLARE_MSM_GPIO_PINS(149);
+DECLARE_MSM_GPIO_PINS(150);
+DECLARE_MSM_GPIO_PINS(151);
+DECLARE_MSM_GPIO_PINS(152);
+DECLARE_MSM_GPIO_PINS(153);
+DECLARE_MSM_GPIO_PINS(154);
+DECLARE_MSM_GPIO_PINS(155);
+DECLARE_MSM_GPIO_PINS(156);
+DECLARE_MSM_GPIO_PINS(157);
+DECLARE_MSM_GPIO_PINS(158);
+DECLARE_MSM_GPIO_PINS(159);
+DECLARE_MSM_GPIO_PINS(160);
+DECLARE_MSM_GPIO_PINS(161);
+DECLARE_MSM_GPIO_PINS(162);
+DECLARE_MSM_GPIO_PINS(163);
+DECLARE_MSM_GPIO_PINS(164);
+DECLARE_MSM_GPIO_PINS(165);
+
+static const unsigned int sdc1_rclk_pins[] = { 166 };
+static const unsigned int sdc1_clk_pins[] = { 167 };
+static const unsigned int sdc1_cmd_pins[] = { 168 };
+static const unsigned int sdc1_data_pins[] = { 169 };
+static const unsigned int sdc2_clk_pins[] = { 170 };
+static const unsigned int sdc2_cmd_pins[] = { 171 };
+static const unsigned int sdc2_data_pins[] = { 172 };
+
+enum shikra_functions {
+ msm_mux_gpio,
+ msm_mux_agera_pll,
+ msm_mux_atest_bbrx,
+ msm_mux_atest_char,
+ msm_mux_atest_gpsadc,
+ msm_mux_atest_tsens,
+ msm_mux_atest_usb,
+ msm_mux_cam_mclk,
+ msm_mux_cci_async,
+ msm_mux_cci_i2c0,
+ msm_mux_cci_i2c1,
+ msm_mux_cci_timer,
+ msm_mux_char_exec,
+ msm_mux_cri_trng,
+ msm_mux_dac_calib,
+ msm_mux_dbg_out_clk,
+ msm_mux_ddr_bist,
+ msm_mux_ddr_pxi,
+ msm_mux_dmic,
+ msm_mux_emac_dll,
+ msm_mux_emac_mcg,
+ msm_mux_emac_phy,
+ msm_mux_emac0_ptp_aux,
+ msm_mux_emac0_ptp_pps,
+ msm_mux_emac1_ptp_aux,
+ msm_mux_emac1_ptp_pps,
+ msm_mux_ext_mclk,
+ msm_mux_gcc_gp,
+ msm_mux_gsm0_tx,
+ msm_mux_i2s0,
+ msm_mux_i2s1,
+ msm_mux_i2s2,
+ msm_mux_i2s3,
+ msm_mux_jitter_bist,
+ msm_mux_m_voc,
+ msm_mux_mdp_vsync_e,
+ msm_mux_mdp_vsync_out0,
+ msm_mux_mdp_vsync_out1,
+ msm_mux_mdp_vsync_p,
+ msm_mux_mdp_vsync_s,
+ msm_mux_mpm_pwr,
+ msm_mux_mss_lte,
+ msm_mux_nav_gpio,
+ msm_mux_pa_indicator_or,
+ msm_mux_pbs_in,
+ msm_mux_pbs_out,
+ msm_mux_pcie0_clk_req_n,
+ msm_mux_phase_flag,
+ msm_mux_pll,
+ msm_mux_prng_rosc,
+ msm_mux_pwm,
+ msm_mux_qdss_cti,
+ msm_mux_qup0_se0,
+ msm_mux_qup0_se1,
+ msm_mux_qup0_se1_01,
+ msm_mux_qup0_se1_23,
+ msm_mux_qup0_se2,
+ msm_mux_qup0_se3_01,
+ msm_mux_qup0_se3_23,
+ msm_mux_qup0_se4_01,
+ msm_mux_qup0_se4_23,
+ msm_mux_qup0_se5,
+ msm_mux_qup0_se6,
+ msm_mux_qup0_se7_01,
+ msm_mux_qup0_se7_23,
+ msm_mux_qup0_se8,
+ msm_mux_qup0_se9,
+ msm_mux_qup0_se9_01,
+ msm_mux_qup0_se9_23,
+ msm_mux_rgmii,
+ msm_mux_sd_write_protect,
+ msm_mux_sdc_cdc,
+ msm_mux_sdc_tb_trig,
+ msm_mux_ssbi_wtr,
+ msm_mux_swr0_rx,
+ msm_mux_swr0_tx,
+ msm_mux_tgu_ch_trigout,
+ msm_mux_tsc_async,
+ msm_mux_tsense_pwm,
+ msm_mux_uim1,
+ msm_mux_uim2,
+ msm_mux_unused_adsp,
+ msm_mux_unused_gsm1,
+ msm_mux_usb0_phy_ps,
+ msm_mux_vfr,
+ msm_mux_vsense_trigger_mirnat,
+ msm_mux_wlan,
+ msm_mux__,
+};
+
+static const char *const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+ "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
+ "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
+ "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
+ "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
+ "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
+ "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
+ "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89",
+ "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
+ "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
+ "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
+ "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
+ "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
+ "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
+ "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131",
+ "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
+ "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
+ "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
+ "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155",
+ "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
+ "gpio162", "gpio163", "gpio164", "gpio165",
+};
+
+static const char *const agera_pll_groups[] = {
+ "gpio22", "gpio23",
+};
+
+static const char *const atest_bbrx_groups[] = {
+ "gpio58", "gpio59",
+};
+
+static const char *const atest_char_groups[] = {
+ "gpio56", "gpio57", "gpio54", "gpio55", "gpio62",
+};
+
+static const char *const atest_gpsadc_groups[] = {
+ "gpio60", "gpio96",
+};
+
+static const char *const atest_tsens_groups[] = {
+ "gpio1", "gpio2",
+};
+
+static const char *const atest_usb_groups[] = {
+ "gpio53", "gpio58", "gpio59", "gpio60", "gpio61", "gpio96",
+ "gpio98", "gpio99", "gpio100", "gpio101",
+};
+
+static const char *const cam_mclk_groups[] = {
+ "gpio34", "gpio35", "gpio96", "gpio98",
+};
+
+static const char *const cci_async_groups[] = {
+ "gpio39",
+};
+
+static const char *const cci_i2c0_groups[] = {
+ "gpio36", "gpio37",
+};
+
+static const char *const cci_i2c1_groups[] = {
+ "gpio41", "gpio42",
+};
+
+static const char *const cci_timer_groups[] = {
+ "gpio38", "gpio40", "gpio43", "gpio47",
+};
+
+static const char *const char_exec_groups[] = {
+ "gpio12", "gpio13",
+};
+
+static const char *const cri_trng_groups[] = {
+ "gpio6", "gpio7", "gpio20",
+};
+
+static const char *const dac_calib_groups[] = {
+ "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
+ "gpio9", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18",
+ "gpio19", "gpio63", "gpio64", "gpio66", "gpio68", "gpio69",
+ "gpio70", "gpio88", "gpio89", "gpio90", "gpio97", "gpio116",
+ "gpio117", "gpio118",
+};
+
+static const char *const dbg_out_clk_groups[] = {
+ "gpio61",
+};
+
+static const char *const ddr_bist_groups[] = {
+ "gpio1", "gpio2", "gpio3", "gpio4",
+};
+
+static const char *const ddr_pxi_groups[] = {
+ "gpio98", "gpio99", "gpio100", "gpio101",
+};
+
+static const char *const dmic_groups[] = {
+ "gpio96", "gpio97", "gpio98", "gpio99",
+};
+
+static const char *const emac_dll_groups[] = {
+ "gpio58", "gpio59", "gpio60", "gpio61",
+};
+
+static const char *const emac_mcg_groups[] = {
+ "gpio28", "gpio29", "gpio40", "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47",
+};
+
+static const char *const emac_phy_groups[] = {
+ "gpio120", "gpio136",
+};
+
+static const char *const emac0_ptp_aux_groups[] = {
+ "gpio60", "gpio63", "gpio69", "gpio85",
+};
+
+static const char *const emac0_ptp_pps_groups[] = {
+ "gpio60", "gpio63", "gpio69", "gpio85",
+};
+
+static const char *const emac1_ptp_aux_groups[] = {
+ "gpio31", "gpio33", "gpio60", "gpio68",
+};
+
+static const char *const emac1_ptp_pps_groups[] = {
+ "gpio31", "gpio33", "gpio60", "gpio68",
+};
+
+static const char *const ext_mclk_groups[] = {
+ "gpio103", "gpio104", "gpio110", "gpio114",
+};
+
+static const char *const gcc_gp_groups[] = {
+ "gpio45", "gpio53", "gpio61", "gpio88", "gpio89", "gpio110",
+};
+
+static const char *const gsm0_tx_groups[] = {
+ "gpio75",
+};
+
+static const char *const i2s0_groups[] = {
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+};
+
+static const char *const i2s1_groups[] = {
+ "gpio96", "gpio97", "gpio98", "gpio99",
+};
+
+static const char *const i2s2_groups[] = {
+ "gpio100", "gpio101", "gpio102", "gpio103",
+};
+
+static const char *const i2s3_groups[] = {
+ "gpio111", "gpio112", "gpio113", "gpio114",
+};
+
+static const char *const jitter_bist_groups[] = {
+ "gpio96", "gpio99",
+};
+
+static const char *const m_voc_groups[] = {
+ "gpio0",
+};
+
+static const char *const mdp_vsync_e_groups[] = {
+ "gpio94",
+};
+
+static const char *const mdp_vsync_out0_groups[] = {
+ "gpio86",
+};
+
+static const char *const mdp_vsync_out1_groups[] = {
+ "gpio86",
+};
+
+static const char *const mdp_vsync_p_groups[] = {
+ "gpio86",
+};
+
+static const char *const mdp_vsync_s_groups[] = {
+ "gpio95",
+};
+
+static const char *const mpm_pwr_groups[] = {
+ "gpio1",
+};
+
+static const char *const mss_lte_groups[] = {
+ "gpio115", "gpio116",
+};
+
+static const char *const nav_gpio_groups[] = {
+ "gpio53", "gpio58", "gpio63", "gpio71", "gpio91", "gpio92",
+ "gpio95", "gpio100", "gpio101", "gpio104",
+};
+
+static const char *const pa_indicator_or_groups[] = {
+ "gpio61",
+};
+
+static const char *const pbs_in_groups[] = {
+ "gpio48", "gpio49", "gpio50", "gpio51", "gpio53", "gpio54",
+ "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60",
+ "gpio61", "gpio62", "gpio63", "gpio74",
+};
+
+static const char *const pbs_out_groups[] = {
+ "gpio22", "gpio23", "gpio24",
+};
+
+static const char *const pcie0_clk_req_n_groups[] = {
+ "gpio117",
+};
+
+static const char *const phase_flag_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio11", "gpio16",
+ "gpio17", "gpio28", "gpio29", "gpio30", "gpio31", "gpio48",
+ "gpio49", "gpio50", "gpio54", "gpio55", "gpio56", "gpio57",
+ "gpio62", "gpio63", "gpio64", "gpio69", "gpio70", "gpio71",
+ "gpio72", "gpio74", "gpio102",
+};
+
+static const char *const pll_groups[] = {
+ "gpio14", "gpio22", "gpio43", "gpio44", "gpio74", "gpio76",
+};
+
+static const char *const prng_rosc_groups[] = {
+ "gpio27", "gpio28",
+};
+
+static const char *const pwm_groups[] = {
+ "gpio32", "gpio40", "gpio45", "gpio53", "gpio54", "gpio55",
+ "gpio56", "gpio57", "gpio58", "gpio61", "gpio62", "gpio68",
+ "gpio77", "gpio79", "gpio80", "gpio87", "gpio102"
+};
+
+static const char *const qdss_cti_groups[] = {
+ "gpio28", "gpio29", "gpio30", "gpio31", "gpio94", "gpio95",
+};
+
+static const char *const qup0_se0_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+
+static const char *const qup0_se1_groups[] = {
+ "gpio28", "gpio29",
+};
+
+static const char *const qup0_se1_01_groups[] = {
+ "gpio4", "gpio5",
+};
+
+static const char *const qup0_se1_23_groups[] = {
+ "gpio4", "gpio5",
+};
+
+static const char *const qup0_se2_groups[] = {
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio30", "gpio31",
+};
+
+static const char *const qup0_se3_01_groups[] = {
+ "gpio10", "gpio11",
+};
+
+static const char *const qup0_se3_23_groups[] = {
+ "gpio10", "gpio11",
+};
+
+static const char *const qup0_se4_01_groups[] = {
+ "gpio12", "gpio13",
+};
+
+static const char *const qup0_se4_23_groups[] = {
+ "gpio12", "gpio13",
+};
+
+static const char *const qup0_se5_groups[] = {
+ "gpio14", "gpio15", "gpio16", "gpio17",
+};
+
+static const char *const qup0_se6_groups[] = {
+ "gpio18", "gpio19", "gpio28", "gpio29", "gpio30", "gpio31",
+};
+
+static const char *const qup0_se7_01_groups[] = {
+ "gpio20", "gpio21",
+};
+
+static const char *const qup0_se7_23_groups[] = {
+ "gpio20", "gpio21",
+};
+
+static const char *const qup0_se8_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25",
+};
+
+static const char *const qup0_se9_groups[] = {
+ "gpio48", "gpio49", "gpio50", "gpio51",
+};
+
+static const char *const qup0_se9_01_groups[] = {
+ "gpio26", "gpio27",
+};
+
+static const char *const qup0_se9_23_groups[] = {
+ "gpio26", "gpio27",
+};
+
+static const char *const rgmii_groups[] = {
+ "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", "gpio126",
+ "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132",
+ "gpio133", "gpio134", "gpio137", "gpio138", "gpio139", "gpio140",
+ "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
+ "gpio147", "gpio148", "gpio149", "gpio150",
+};
+
+static const char *const sd_write_protect_groups[] = {
+ "gpio109",
+};
+
+static const char *const sdc_cdc_groups[] = {
+ "gpio98", "gpio99", "gpio100", "gpio101",
+};
+
+static const char *const sdc_tb_trig_groups[] = {
+ "gpio32", "gpio33",
+};
+
+static const char *const ssbi_wtr_groups[] = {
+ "gpio68", "gpio69", "gpio70", "gpio71",
+};
+
+static const char *const swr0_rx_groups[] = {
+ "gpio107", "gpio108", "gpio109",
+};
+
+static const char *const swr0_tx_groups[] = {
+ "gpio105", "gpio106",
+};
+
+static const char *const tgu_ch_trigout_groups[] = {
+ "gpio14", "gpio15", "gpio16", "gpio17",
+};
+
+static const char *const tsc_async_groups[] = {
+ "gpio45", "gpio46",
+};
+
+static const char *const tsense_pwm_groups[] = {
+ "gpio21",
+};
+
+static const char *const uim1_groups[] = {
+ "gpio81", "gpio82", "gpio83", "gpio84",
+};
+
+static const char *const uim2_groups[] = {
+ "gpio77", "gpio78", "gpio79", "gpio80",
+};
+
+static const char *const unused_adsp_groups[] = {
+ "gpio35",
+};
+
+static const char *const unused_gsm1_groups[] = {
+ "gpio64",
+};
+
+static const char *const usb0_phy_ps_groups[] = {
+ "gpio90",
+};
+
+static const char *const vfr_groups[] = {
+ "gpio59",
+};
+
+static const char *const vsense_trigger_mirnat_groups[] = {
+ "gpio58",
+};
+
+static const char *const wlan_groups[] = {
+ "gpio14", "gpio15",
+};
+
+static const struct pinfunction shikra_functions[] = {
+ MSM_GPIO_PIN_FUNCTION(gpio),
+ MSM_PIN_FUNCTION(agera_pll),
+ MSM_PIN_FUNCTION(atest_bbrx),
+ MSM_PIN_FUNCTION(atest_char),
+ MSM_PIN_FUNCTION(atest_gpsadc),
+ MSM_PIN_FUNCTION(atest_tsens),
+ MSM_PIN_FUNCTION(atest_usb),
+ MSM_PIN_FUNCTION(cam_mclk),
+ MSM_PIN_FUNCTION(cci_async),
+ MSM_PIN_FUNCTION(cci_i2c0),
+ MSM_PIN_FUNCTION(cci_i2c1),
+ MSM_PIN_FUNCTION(cci_timer),
+ MSM_PIN_FUNCTION(char_exec),
+ MSM_PIN_FUNCTION(cri_trng),
+ MSM_PIN_FUNCTION(dac_calib),
+ MSM_PIN_FUNCTION(dbg_out_clk),
+ MSM_PIN_FUNCTION(ddr_bist),
+ MSM_PIN_FUNCTION(ddr_pxi),
+ MSM_PIN_FUNCTION(dmic),
+ MSM_PIN_FUNCTION(emac_dll),
+ MSM_PIN_FUNCTION(emac_mcg),
+ MSM_PIN_FUNCTION(emac_phy),
+ MSM_PIN_FUNCTION(emac0_ptp_aux),
+ MSM_PIN_FUNCTION(emac0_ptp_pps),
+ MSM_PIN_FUNCTION(emac1_ptp_aux),
+ MSM_PIN_FUNCTION(emac1_ptp_pps),
+ MSM_PIN_FUNCTION(ext_mclk),
+ MSM_PIN_FUNCTION(gcc_gp),
+ MSM_PIN_FUNCTION(gsm0_tx),
+ MSM_PIN_FUNCTION(i2s0),
+ MSM_PIN_FUNCTION(i2s1),
+ MSM_PIN_FUNCTION(i2s2),
+ MSM_PIN_FUNCTION(i2s3),
+ MSM_PIN_FUNCTION(jitter_bist),
+ MSM_PIN_FUNCTION(m_voc),
+ MSM_PIN_FUNCTION(mdp_vsync_e),
+ MSM_PIN_FUNCTION(mdp_vsync_out0),
+ MSM_PIN_FUNCTION(mdp_vsync_out1),
+ MSM_PIN_FUNCTION(mdp_vsync_p),
+ MSM_PIN_FUNCTION(mdp_vsync_s),
+ MSM_PIN_FUNCTION(mpm_pwr),
+ MSM_PIN_FUNCTION(mss_lte),
+ MSM_PIN_FUNCTION(nav_gpio),
+ MSM_PIN_FUNCTION(pa_indicator_or),
+ MSM_PIN_FUNCTION(pbs_in),
+ MSM_PIN_FUNCTION(pbs_out),
+ MSM_PIN_FUNCTION(pcie0_clk_req_n),
+ MSM_PIN_FUNCTION(phase_flag),
+ MSM_PIN_FUNCTION(pll),
+ MSM_PIN_FUNCTION(prng_rosc),
+ MSM_PIN_FUNCTION(pwm),
+ MSM_PIN_FUNCTION(qdss_cti),
+ MSM_PIN_FUNCTION(qup0_se0),
+ MSM_PIN_FUNCTION(qup0_se1),
+ MSM_PIN_FUNCTION(qup0_se1_01),
+ MSM_PIN_FUNCTION(qup0_se1_23),
+ MSM_PIN_FUNCTION(qup0_se2),
+ MSM_PIN_FUNCTION(qup0_se3_01),
+ MSM_PIN_FUNCTION(qup0_se3_23),
+ MSM_PIN_FUNCTION(qup0_se4_01),
+ MSM_PIN_FUNCTION(qup0_se4_23),
+ MSM_PIN_FUNCTION(qup0_se5),
+ MSM_PIN_FUNCTION(qup0_se6),
+ MSM_PIN_FUNCTION(qup0_se7_01),
+ MSM_PIN_FUNCTION(qup0_se7_23),
+ MSM_PIN_FUNCTION(qup0_se8),
+ MSM_PIN_FUNCTION(qup0_se9),
+ MSM_PIN_FUNCTION(qup0_se9_01),
+ MSM_PIN_FUNCTION(qup0_se9_23),
+ MSM_PIN_FUNCTION(rgmii),
+ MSM_PIN_FUNCTION(sd_write_protect),
+ MSM_PIN_FUNCTION(sdc_cdc),
+ MSM_PIN_FUNCTION(sdc_tb_trig),
+ MSM_PIN_FUNCTION(ssbi_wtr),
+ MSM_PIN_FUNCTION(swr0_rx),
+ MSM_PIN_FUNCTION(swr0_tx),
+ MSM_PIN_FUNCTION(tgu_ch_trigout),
+ MSM_PIN_FUNCTION(tsc_async),
+ MSM_PIN_FUNCTION(tsense_pwm),
+ MSM_PIN_FUNCTION(uim1),
+ MSM_PIN_FUNCTION(uim2),
+ MSM_PIN_FUNCTION(unused_adsp),
+ MSM_PIN_FUNCTION(unused_gsm1),
+ MSM_PIN_FUNCTION(usb0_phy_ps),
+ MSM_PIN_FUNCTION(vfr),
+ MSM_PIN_FUNCTION(vsense_trigger_mirnat),
+ MSM_PIN_FUNCTION(wlan),
+};
+
+static const struct msm_pingroup shikra_groups[] = {
+ [0] = PINGROUP(0, qup0_se0, m_voc, _, phase_flag, _, _, _, _, _, _, _),
+ [1] = PINGROUP(1, qup0_se0, mpm_pwr, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _),
+ [2] = PINGROUP(2, qup0_se0, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _, _),
+ [3] = PINGROUP(3, qup0_se0, ddr_bist, _, phase_flag, dac_calib, _, _, _, _, _, _),
+ [4] = PINGROUP(4, qup0_se1_23, qup0_se1_01, ddr_bist, _, phase_flag, dac_calib, _, _, _,
+ _, _),
+ [5] = PINGROUP(5, qup0_se1_23, qup0_se1_01, _, phase_flag, dac_calib, _, _, _, _, _, _),
+ [6] = PINGROUP(6, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _),
+ [7] = PINGROUP(7, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _),
+ [8] = PINGROUP(8, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _),
+ [9] = PINGROUP(9, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _),
+ [10] = PINGROUP(10, qup0_se3_01, qup0_se3_23, _, _, _, _, _, _, _, _, _),
+ [11] = PINGROUP(11, qup0_se3_01, qup0_se3_23, _, phase_flag, _, _, _, _, _, _, _),
+ [12] = PINGROUP(12, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _),
+ [13] = PINGROUP(13, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _),
+ [14] = PINGROUP(14, qup0_se5, pll, tgu_ch_trigout, dac_calib, wlan, _, _, _, _, _, _),
+ [15] = PINGROUP(15, qup0_se5, tgu_ch_trigout, _, dac_calib, wlan, _, _, _, _, _, _),
+ [16] = PINGROUP(16, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _),
+ [17] = PINGROUP(17, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _),
+ [18] = PINGROUP(18, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _),
+ [19] = PINGROUP(19, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _),
+ [20] = PINGROUP(20, qup0_se7_01, qup0_se7_23, cri_trng, _, _, _, _, _, _, _, _),
+ [21] = PINGROUP(21, qup0_se7_01, qup0_se7_23, tsense_pwm, _, _, _, _, _, _, _, _),
+ [22] = PINGROUP(22, qup0_se8, pll, agera_pll, pbs_out, _, _, _, _, _, _, _),
+ [23] = PINGROUP(23, qup0_se8, agera_pll, pbs_out, _, _, _, _, _, _, _, _),
+ [24] = PINGROUP(24, qup0_se8, pbs_out, _, _, _, _, _, _, _, _, _),
+ [25] = PINGROUP(25, qup0_se8, _, _, _, _, _, _, _, _, _, _),
+ [26] = PINGROUP(26, qup0_se9_23, qup0_se9_01, _, _, _, _, _, _, _, _, _),
+ [27] = PINGROUP(27, qup0_se9_23, qup0_se9_01, prng_rosc, _, _, _, _, _, _, _, _),
+ [28] = PINGROUP(28, qup0_se1, qup0_se6, emac_mcg, prng_rosc, _, phase_flag, qdss_cti,
+ _, _, _, _),
+ [29] = PINGROUP(29, qup0_se1, qup0_se6, emac_mcg, _, phase_flag, qdss_cti, _, _, _, _, _),
+ [30] = PINGROUP(30, qup0_se2, qup0_se6, _, phase_flag, qdss_cti, _, _, _, _, _, _),
+ [31] = PINGROUP(31, qup0_se2, qup0_se6, emac1_ptp_aux, emac1_ptp_pps, _, phase_flag,
+ qdss_cti, _, _, _, _),
+ [32] = PINGROUP(32, pwm, sdc_tb_trig, _, _, _, _, _, _, _, _, _),
+ [33] = PINGROUP(33, emac1_ptp_aux, emac1_ptp_pps, sdc_tb_trig, _, _, _, _, _, _, _, _),
+ [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _, _, _, _, _),
+ [35] = PINGROUP(35, cam_mclk, unused_adsp, _, _, _, _, _, _, _, _, _),
+ [36] = PINGROUP(36, cci_i2c0, _, _, _, _, _, _, _, _, _, _),
+ [37] = PINGROUP(37, cci_i2c0, _, _, _, _, _, _, _, _, _, _),
+ [38] = PINGROUP(38, cci_timer, _, _, _, _, _, _, _, _, _, _),
+ [39] = PINGROUP(39, cci_async, _, _, _, _, _, _, _, _, _, _),
+ [40] = PINGROUP(40, cci_timer, emac_mcg, pwm, _, _, _, _, _, _, _, _),
+ [41] = PINGROUP(41, cci_i2c1, _, _, _, _, _, _, _, _, _, _),
+ [42] = PINGROUP(42, cci_i2c1, _, _, _, _, _, _, _, _, _, _),
+ [43] = PINGROUP(43, cci_timer, emac_mcg, pll, _, _, _, _, _, _, _, _),
+ [44] = PINGROUP(44, emac_mcg, pll, _, _, _, _, _, _, _, _, _),
+ [45] = PINGROUP(45, tsc_async, emac_mcg, pwm, gcc_gp, _, _, _, _, _, _, _),
+ [46] = PINGROUP(46, tsc_async, emac_mcg, _, _, _, _, _, _, _, _, _),
+ [47] = PINGROUP(47, cci_timer, emac_mcg, _, _, _, _, _, _, _, _, _),
+ [48] = PINGROUP(48, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _),
+ [49] = PINGROUP(49, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _),
+ [50] = PINGROUP(50, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _),
+ [51] = PINGROUP(51, _, qup0_se9, pbs_in, _, _, _, _, _, _, _, _),
+ [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _, _, _),
+ [53] = PINGROUP(53, _, nav_gpio, gcc_gp, pwm, _, pbs_in, atest_usb, _, _, _, _),
+ [54] = PINGROUP(54, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),
+ [55] = PINGROUP(55, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),
+ [56] = PINGROUP(56, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),
+ [57] = PINGROUP(57, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),
+ [58] = PINGROUP(58, _, nav_gpio, pwm, _, pbs_in, atest_bbrx, atest_usb,
+ vsense_trigger_mirnat, emac_dll, _, _),
+ [59] = PINGROUP(59, _, vfr, _, pbs_in, atest_bbrx, atest_usb, emac_dll, _, _, _, _),
+ [60] = PINGROUP(60, _, emac1_ptp_aux, emac1_ptp_pps, emac0_ptp_aux, emac0_ptp_pps, _,
+ pbs_in, atest_gpsadc, atest_usb, emac_dll, _),
+ [61] = PINGROUP(61, _, pwm, gcc_gp, pa_indicator_or, dbg_out_clk, pbs_in, atest_usb,
+ emac_dll, _, _, _),
+ [62] = PINGROUP(62, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),
+ [63] = PINGROUP(63, _, nav_gpio, emac0_ptp_aux, emac0_ptp_pps, _, pbs_in, phase_flag,
+ dac_calib, _, _, _),
+ [64] = PINGROUP(64, _, unused_gsm1, dac_calib, _, _, _, _, _, _, _, _),
+ [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _),
+ [66] = PINGROUP(66, _, dac_calib, _, _, _, _, _, _, _, _, _),
+ [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _, _, _),
+ [68] = PINGROUP(68, _, ssbi_wtr, emac1_ptp_aux, emac1_ptp_pps, pwm, dac_calib, _, _, _,
+ _, _),
+ [69] = PINGROUP(69, _, ssbi_wtr, emac0_ptp_aux, emac0_ptp_pps, _, phase_flag, dac_calib,
+ _, _, _, _),
+ [70] = PINGROUP(70, _, ssbi_wtr, _, phase_flag, dac_calib, _, _, _, _, _, _),
+ [71] = PINGROUP(71, _, ssbi_wtr, nav_gpio, _, phase_flag, _, _, _, _, _, _),
+ [72] = PINGROUP(72, _, _, phase_flag, _, _, _, _, _, _, _, _),
+ [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _, _),
+ [74] = PINGROUP(74, pll, _, pbs_in, phase_flag, _, _, _, _, _, _, _),
+ [75] = PINGROUP(75, gsm0_tx, _, _, _, _, _, _, _, _, _, _),
+ [76] = PINGROUP(76, pll, _, _, _, _, _, _, _, _, _, _),
+ [77] = PINGROUP(77, uim2, pwm, _, _, _, _, _, _, _, _, _),
+ [78] = PINGROUP(78, uim2, _, _, _, _, _, _, _, _, _, _),
+ [79] = PINGROUP(79, uim2, pwm, _, _, _, _, _, _, _, _, _),
+ [80] = PINGROUP(80, uim2, pwm, _, _, _, _, _, _, _, _, _),
+ [81] = PINGROUP(81, uim1, _, _, _, _, _, _, _, _, _, _),
+ [82] = PINGROUP(82, uim1, _, _, _, _, _, _, _, _, _, _),
+ [83] = PINGROUP(83, uim1, _, _, _, _, _, _, _, _, _, _),
+ [84] = PINGROUP(84, uim1, _, _, _, _, _, _, _, _, _, _),
+ [85] = PINGROUP(85, emac0_ptp_aux, emac0_ptp_pps, _, _, _, _, _, _, _, _, _),
+ [86] = PINGROUP(86, mdp_vsync_p, mdp_vsync_out0, mdp_vsync_out1, _, _, _, _, _, _, _, _),
+ [87] = PINGROUP(87, _, pwm, _, _, _, _, _, _, _, _, _),
+ [88] = PINGROUP(88, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _),
+ [89] = PINGROUP(89, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _),
+ [90] = PINGROUP(90, usb0_phy_ps, _, dac_calib, _, _, _, _, _, _, _, _),
+ [91] = PINGROUP(91, nav_gpio, _, _, _, _, _, _, _, _, _, _),
+ [92] = PINGROUP(92, nav_gpio, _, _, _, _, _, _, _, _, _, _),
+ [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _, _, _),
+ [94] = PINGROUP(94, mdp_vsync_e, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _),
+ [95] = PINGROUP(95, nav_gpio, mdp_vsync_s, qdss_cti, qdss_cti, _, _, _, _, _, _, _),
+ [96] = PINGROUP(96, dmic, cam_mclk, i2s1, jitter_bist, atest_gpsadc, atest_usb, _, _, _,
+ _, _),
+ [97] = PINGROUP(97, dmic, i2s1, dac_calib, _, _, _, _, _, _, _, _),
+ [98] = PINGROUP(98, dmic, cam_mclk, i2s1, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _),
+ [99] = PINGROUP(99, dmic, i2s1, jitter_bist, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _),
+ [100] = PINGROUP(100, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _),
+ [101] = PINGROUP(101, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _),
+ [102] = PINGROUP(102, i2s2, pwm, _, phase_flag, _, _, _, _, _, _, _),
+ [103] = PINGROUP(103, ext_mclk, i2s2, _, _, _, _, _, _, _, _, _),
+ [104] = PINGROUP(104, ext_mclk, nav_gpio, _, _, _, _, _, _, _, _, _),
+ [105] = PINGROUP(105, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _),
+ [106] = PINGROUP(106, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _),
+ [107] = PINGROUP(107, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _),
+ [108] = PINGROUP(108, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _),
+ [109] = PINGROUP(109, swr0_rx, i2s0, sd_write_protect, _, _, _, _, _, _, _, _),
+ [110] = PINGROUP(110, ext_mclk, i2s0, _, gcc_gp, _, _, _, _, _, _, _),
+ [111] = PINGROUP(111, i2s3, _, _, _, _, _, _, _, _, _, _),
+ [112] = PINGROUP(112, i2s3, _, _, _, _, _, _, _, _, _, _),
+ [113] = PINGROUP(113, i2s3, _, _, _, _, _, _, _, _, _, _),
+ [114] = PINGROUP(114, ext_mclk, i2s3, _, _, _, _, _, _, _, _, _),
+ [115] = PINGROUP(115, mss_lte, _, _, _, _, _, _, _, _, _, _),
+ [116] = PINGROUP(116, mss_lte, _, dac_calib, _, _, _, _, _, _, _, _),
+ [117] = PINGROUP(117, pcie0_clk_req_n, _, dac_calib, _, _, _, _, _, _, _, _),
+ [118] = PINGROUP(118, _, dac_calib, _, _, _, _, _, _, _, _, _),
+ [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _),
+ [120] = PINGROUP(120, emac_phy, _, _, _, _, _, _, _, _, _, _),
+ [121] = PINGROUP(121, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [122] = PINGROUP(122, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [123] = PINGROUP(123, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [124] = PINGROUP(124, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [125] = PINGROUP(125, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [126] = PINGROUP(126, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [127] = PINGROUP(127, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [128] = PINGROUP(128, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [129] = PINGROUP(129, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [130] = PINGROUP(130, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [131] = PINGROUP(131, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [132] = PINGROUP(132, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [133] = PINGROUP(133, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [134] = PINGROUP(134, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _),
+ [136] = PINGROUP(136, emac_phy, _, _, _, _, _, _, _, _, _, _),
+ [137] = PINGROUP(137, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [138] = PINGROUP(138, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [139] = PINGROUP(139, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [140] = PINGROUP(140, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [141] = PINGROUP(141, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [142] = PINGROUP(142, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [143] = PINGROUP(143, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [144] = PINGROUP(144, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [145] = PINGROUP(145, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [146] = PINGROUP(146, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [147] = PINGROUP(147, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [148] = PINGROUP(148, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [149] = PINGROUP(149, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [150] = PINGROUP(150, rgmii, _, _, _, _, _, _, _, _, _, _),
+ [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, _),
+ [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, _),
+ [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, _),
+ [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _),
+ [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _),
+ [156] = PINGROUP(156, _, _, _, _, _, _, _, _, _, _, _),
+ [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _),
+ [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _),
+ [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _),
+ [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _, _, _),
+ [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _, _),
+ [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _, _, _),
+ [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, _),
+ [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, _),
+ [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, _),
+ [166] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xac004, 0, 0),
+ [167] = SDC_QDSD_PINGROUP(sdc1_clk, 0xac000, 13, 6),
+ [168] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xac000, 11, 3),
+ [169] = SDC_QDSD_PINGROUP(sdc1_data, 0xac000, 9, 0),
+ [170] = SDC_QDSD_PINGROUP(sdc2_clk, 0xaa000, 14, 6),
+ [171] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xaa000, 11, 3),
+ [172] = SDC_QDSD_PINGROUP(sdc2_data, 0xaa000, 9, 0),
+};
+
+static const struct msm_gpio_wakeirq_map shikra_mpm_map[] = {
+ {1, 9}, {2, 31}, {5, 49}, {6, 53}, {9, 72}, {10, 10},
+ {12, 22}, {14, 26}, {17, 29}, {18, 24}, {20, 32}, {22, 33},
+ {25, 34}, {27, 35}, {28, 36}, {29, 37}, {30, 38}, {31, 39},
+ {32, 40}, {33, 41}, {38, 42}, {40, 43}, {43, 44}, {44, 45},
+ {45, 46}, {46, 47}, {47, 48}, {48, 60}, {50, 50}, {51, 51},
+ {52, 61}, {53, 62}, {57, 52}, {58, 63}, {60, 54}, {63, 64},
+ {73, 55}, {74, 56}, {75, 57}, {77, 3}, {80, 4}, {84, 5},
+ {85, 67}, {86, 69}, {88, 70}, {89, 71}, {90, 73}, {91, 74},
+ {92, 75}, {93, 76}, {94, 77}, {95, 78}, {97, 79}, {99, 80},
+ {100, 11}, {101, 13}, {102, 14}, {103, 15}, {106, 16}, {108, 17},
+ {112, 18}, {116, 19}, {117, 20}, {119, 21}, {120, 23}, {136, 25},
+ {159, 27}, {161, 28},
+};
+
+static const struct msm_pinctrl_soc_data shikra_tlmm = {
+ .pins = shikra_pins,
+ .npins = ARRAY_SIZE(shikra_pins),
+ .functions = shikra_functions,
+ .nfunctions = ARRAY_SIZE(shikra_functions),
+ .groups = shikra_groups,
+ .ngroups = ARRAY_SIZE(shikra_groups),
+ .ngpios = 166,
+ .wakeirq_map = shikra_mpm_map,
+ .nwakeirq_map = ARRAY_SIZE(shikra_mpm_map),
+ .egpio_func = 11,
+};
+
+static int shikra_tlmm_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &shikra_tlmm);
+}
+
+static const struct of_device_id shikra_tlmm_of_match[] = {
+ { .compatible = "qcom,shikra-tlmm", .data = &shikra_tlmm },
+ {},
+};
+
+static struct platform_driver shikra_tlmm_driver = {
+ .driver = {
+ .name = "shikra-tlmm",
+ .of_match_table = shikra_tlmm_of_match,
+ },
+ .probe = shikra_tlmm_probe,
+};
+
+static int __init shikra_tlmm_init(void)
+{
+ return platform_driver_register(&shikra_tlmm_driver);
+}
+arch_initcall(shikra_tlmm_init);
+
+static void __exit shikra_tlmm_exit(void)
+{
+ platform_driver_unregister(&shikra_tlmm_driver);
+}
+module_exit(shikra_tlmm_exit);
+
+MODULE_DESCRIPTION("QTI Shikra TLMM driver");
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(of, shikra_tlmm_of_match);
--
2.34.1
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: pinctrl: qcom: Document Shikra Top Level Mode Multiplexer
From: Komal Bajaj @ 2026-04-29 13:11 UTC (permalink / raw)
To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Richard Cochran
Cc: linux-arm-msm, linux-gpio, devicetree, linux-kernel, netdev,
Komal Bajaj
In-Reply-To: <20260429-shikra-pinctrl-v1-0-1b4bb2b3a8d6@oss.qualcomm.com>
Add a DeviceTree binding to describe the TLMM block on Qualcomm's
Shikra SoC.
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
.../bindings/pinctrl/qcom,shikra-tlmm.yaml | 123 +++++++++++++++++++++
1 file changed, 123 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml
new file mode 100644
index 000000000000..896fbe461ef9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,shikra-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Shikra TLMM block
+
+maintainers:
+ - Komal Bajaj <komal.bajaj@oss.qualcomm.com>
+
+description: |
+ Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,shikra-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 83
+
+ gpio-line-names:
+ maxItems: 165
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-shikra-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-shikra-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-shikra-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$"
+ - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
+ sdc2_clk, sdc2_cmd, sdc2_data ]
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_gpsadc,
+ atest_tsens, atest_usb, cam_mclk, cci_async, cci_i2c0,
+ cci_i2c1, cci_timer, char_exec, cri_trng, dac_calib,
+ dbg_out_clk, ddr_bist, ddr_pxi, dmic, emac_dll, emac_mcg,
+ emac_phy, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux,
+ emac1_ptp_pps, ext_mclk, gcc_gp, gsm0_tx, i2s0, i2s1,
+ i2s2, i2s3, jitter_bist, m_voc, mdp_vsync_e, mdp_vsync_out0,
+ mdp_vsync_out1, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte,
+ nav_gpio, pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n,
+ phase_flag, pll, prng_rosc, pwm, qdss_cti, qup0_se0,
+ qup0_se1, qup0_se1_01, qup0_se1_23, qup0_se2, qup0_se3_01,
+ qup0_se3_23, qup0_se4_01, qup0_se4_23, qup0_se5, qup0_se6,
+ qup0_se7_01, qup0_se7_23, qup0_se8, qup0_se9, qup0_se9_01,
+ qup0_se9_23, rgmii, sd_write_protect, sdc_cdc, sdc_tb_trig,
+ ssbi_wtr, swr0_rx, swr0_tx, tgu_ch_trigout, tsc_async,
+ tsense_pwm, uim1, uim2, unused_adsp, unused_gsm1, usb0_phy_ps,
+ vfr, vsense_trigger_mirnat, wlan ]
+
+ required:
+ - pins
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tlmm: pinctrl@500000 {
+ compatible = "qcom,shikra-tlmm";
+ reg = <0x00500000 0x800000>;
+
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-ranges = <&tlmm 0 0 166>;
+
+ qup-uart0-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup0_se1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related
* [PATCH 0/2] pinctrl: qcom: Add support for Qualcomm Shikra SoC
From: Komal Bajaj @ 2026-04-29 13:11 UTC (permalink / raw)
To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Richard Cochran
Cc: linux-arm-msm, linux-gpio, devicetree, linux-kernel, netdev,
Komal Bajaj
Add the pinctrl driver, document the bindings and enable the
driver in defconfig as default.
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
Komal Bajaj (2):
dt-bindings: pinctrl: qcom: Document Shikra Top Level Mode Multiplexer
pinctrl: qcom: Add Shikra pinctrl driver
.../bindings/pinctrl/qcom,shikra-tlmm.yaml | 123 ++
drivers/pinctrl/qcom/Kconfig.msm | 11 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-shikra.c | 1280 ++++++++++++++++++++
4 files changed, 1415 insertions(+)
---
base-commit: 39704f00f747aba3144289870b5fd8ac230a9aaf
change-id: 20260429-shikra-pinctrl-fd71ab6ecd6f
prerequisite-change-id: 20260428-shikra-socid-a27ae38cb7e3:v1
prerequisite-patch-id: 843f28095c0d42d0d60ab7000095c64dcb2e90ca
prerequisite-patch-id: 1069d6880c3ff91c230c20fcd876738001c6d35d
Best regards,
--
Komal Bajaj <komal.bajaj@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH net v5 3/4] iavf: send MAC change request synchronously
From: Przemek Kitszel @ 2026-04-29 13:04 UTC (permalink / raw)
To: Jose Ignacio Tornos Martinez, aleksandr.loktionov
Cc: anthony.l.nguyen, davem, edumazet, horms, intel-wired-lan,
jacob.e.keller, jesse.brandeburg, kuba, netdev, pabeni, stable
In-Reply-To: <20260429120047.218369-1-jtornosm@redhat.com>
On 4/29/26 14:00, Jose Ignacio Tornos Martinez wrote:
> Hello Aleksandr,
>
>> I think continue at the end of the cycle is redundant.
> That continue is intentional; without it, if timeout expires but there
> are still messages in the queue, we give up without processing them. The
Alex is right,
"continue" causes to check the condition clause of while loop, also for
do-while
> message we're waiting for might be in the queue and not a lot of messages
> stored are expected.
> That continue reduces possible false timeouts (because the expected message
> could be stored in the queue) while keeping the delay minimal.
> The timeout is really just an estimate, and I don't think it needs
> to be very precise.
with that said, current code is correct
removing the redundant "if" could be done while applying
(if that will be the only nitpick left)
after more thinking:
in theory, not checking the time but processing next message if there
were any pending on the previous message could cause infinite loop
(to fix that we should stop refreshing "pending" value after the
timeout, but only decrementing it - but I think that this would be
needless complication)
My Reviewed-by still holds
>
> Thanks
>
> Best regards
> Jose Ignacio
>
^ permalink raw reply
* Re: [PATCH net-next 4/4] r8152: Add firmware upload capability for RTL8157/RTL8159
From: Andrew Lunn @ 2026-04-29 13:01 UTC (permalink / raw)
To: Birger Koblitz
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, linux-usb, netdev, linux-kernel, Chih Kai Hsu
In-Reply-To: <877f67bd-6bd8-4d61-8f7b-d206b9125eda@birger-koblitz.de>
On Wed, Apr 29, 2026 at 06:21:58AM +0200, Birger Koblitz wrote:
> On 29/04/2026 3:57 am, Andrew Lunn wrote:
> > On Tue, Apr 28, 2026 at 05:47:24AM +0200, Birger Koblitz wrote:
> > > The RTL8159 requires firmware for its PHY in order to work at
> > > connection speeds > 5GBit. Add support for uploading firmware for
> > > the PHYs using the existing rtl8152_apply_firmware() function
> > > in r8157_hw_phy_cfg() and set up the correct names for the firmware
> > > files.
> No, since the RTL8157 (RTL_VER_16) also works in my experiments as expected
> without this change, i.e. without any updated firmware, or better the
> possibility to update the firmware. It is only for the RTL8159 where the
> firmware is necessary to even get 10GBit performance, at least for the
> link-partners I use for testing. My understanding of the Realtek "firmware"
> is that it mainly provides updated calibration constants, possibly better
> calibration routines for interoperability. Unlike for many other drivers,
> the firmware is not necessary to make the driver work at all.
O.K. Please could you expand the commit message. Explain why you are
adding code for RTL_VER_16 as well as RTL_VER_17.
Andrew
^ permalink raw reply
* [REGRESSION] stmmac: Random DMA reset failure on RK3399 since v6.18
From: Jensen Huang @ 2026-04-29 12:53 UTC (permalink / raw)
To: Russell King, Andrew Lunn, Heiner Kallweit; +Cc: regressions, netdev, LKML
Hi,
I'm reporting a regression on RK3399 (stmmac) observed in v6.18.24.
When a network cable is connected during boot, the DMA reset
occasionally fails with the error message: "Failed to reset the dma".
This appears to be a timing issue related to the EEE RX clock-stop
logic. Based on my investigation with the RTL8211E PHY, I monitored
the PHY register PS1R (MMD device 3, address 0x01) and observed a
value of 0x0f40. This indicates that the PHY is in LPI mode and the RX
clock may have already stopped.
While commit dd557266cf5f ("net: stmmac: block PHY RXC clock-stop")
ensures the clock is running before the DMA reset, my tests suggest
that the phylink_rx_clk_stop_block() call might not provide a
sufficiently stable RX clock in time for the immediate DMA reset that
follows.
Since stmmac already sets mac_requires_rxc = true, I modified
phylink_bringup_phy() to honor this flag. This avoids toggling the
PHY's clk_stop_enable during the initialization sequence, ensuring the
RX clock remains active and stable throughout.
With the change below, I achieved 200/200 successful reboots with the
cable connected (previously ~50% failure rate).
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -2171,7 +2171,7 @@ static int phylink_bringup_phy(struct phylink
*pl, struct phy_device *phy,
/* Allow the MAC to stop its clock if the PHY has the capability */
pl->mac_tx_clk_stop = phy_eee_tx_clock_stop_capable(phy) > 0;
- if (pl->mac_supports_eee_ops) {
+ if (pl->mac_supports_eee_ops && !pl->config->mac_requires_rxc) {
/* Explicitly configure whether the PHY is allowed to stop it's
* receive clock.
*/
Any feedback/testing on this would be appreciated.
Best regards,
Jensen Huang
^ permalink raw reply
* Re: [PATCH net v5 3/4] iavf: send MAC change request synchronously
From: Przemek Kitszel @ 2026-04-29 12:53 UTC (permalink / raw)
To: Jose Ignacio Tornos Martinez, netdev
Cc: intel-wired-lan, aleksandr.loktionov, jacob.e.keller, horms,
jesse.brandeburg, anthony.l.nguyen, davem, edumazet, kuba, pabeni,
stable
In-Reply-To: <20260429102426.210750-4-jtornosm@redhat.com>
On 4/29/26 12:24, Jose Ignacio Tornos Martinez wrote:
> After commit ad7c7b2172c3 ("net: hold netdev instance lock during sysfs
> operations"), iavf_set_mac() is called with the netdev instance lock
> already held.
>
> The function queues a MAC address change request via
> iavf_replace_primary_mac() and then waits for completion. However, in
> the current flow, the actual virtchnl message is sent by the watchdog
> task, which also needs to acquire the netdev lock to run. Additionally,
> the adminq_task which processes virtchnl responses also needs the netdev
> lock.
>
> This creates a deadlock scenario:
> 1. iavf_set_mac() holds netdev lock and waits for MAC change
> 2. Watchdog needs netdev lock to send the request -> blocked
> 3. Even if request is sent, adminq_task needs netdev lock to process
> PF response -> blocked
> 4. MAC change times out after 2.5 seconds
> 5. iavf_set_mac() returns -EAGAIN
>
> This particularly affects VFs during bonding setup when multiple VFs are
> enslaved in quick succession.
>
> Fix by implementing a synchronous MAC change operation similar to the
> approach used in commit fdadbf6e84c4 ("iavf: fix incorrect reset handling
> in callbacks").
>
> The solution:
> 1. Send the virtchnl ADD_ETH_ADDR message directly (not via watchdog)
> 2. Poll the admin queue hardware directly for responses
> 3. Process all received messages (including non-MAC messages)
> 4. Return when MAC change completes or times out
>
> A new generic function iavf_poll_virtchnl_response() is introduced that
> can be reused for any future synchronous virtchnl operations. It takes a
> callback to check completion, allowing flexible condition checking.
>
> This allows the operation to complete synchronously while holding
> netdev_lock, without relying on watchdog or adminq_task. The function
> can sleep for up to 2.5 seconds polling hardware, but this is acceptable
> since netdev_lock is per-device and only serializes operations on the
> same interface.
>
> To support this, change iavf_add_ether_addrs() to return an error code
> instead of void, allowing callers to detect failures. Additionally,
> export iavf_mac_add_reject() to enable proper rollback on local failures
> (timeouts, send errors) - PF rejections are already handled automatically
> by iavf_virtchnl_completion().
>
> Remove vc_waitqueue entirely because iavf_set_mac was the only waiter on
> this waitqueue and after the changes it is not needed.
>
> Fixes: ad7c7b2172c3 ("net: hold netdev instance lock during sysfs operations")
> cc: stable@vger.kernel.org
> Signed-off-by: Jose Ignacio Tornos Martinez <jtornosm@redhat.com>
thank you very much!
Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
^ permalink raw reply
* Re: [PATCH net-next] tcp: add tcp_mstamp_refresh_inline()
From: Neal Cardwell @ 2026-04-29 12:48 UTC (permalink / raw)
To: Eric Dumazet
Cc: David S . Miller, Jakub Kicinski, Paolo Abeni, Simon Horman,
Kuniyuki Iwashima, netdev, eric.dumazet
In-Reply-To: <20260429010809.784315-1-edumazet@google.com>
On Tue, Apr 28, 2026 at 9:08 PM Eric Dumazet <edumazet@google.com> wrote:
>
> We want to inline tcp_mstamp_refresh() in fast path only:
>
> - tcp_rcv_established()
> - tcp_write_xmit()
>
> Add tcp_mstamp_refresh_inline() for this purpose.
>
> Add noinline qualifier on tcp_mstamp_refresh() for the other paths,
> to reduce bloat.
>
> $ scripts/bloat-o-meter -t vmlinux.old vmlinux.new
> add/remove: 0/0 grow/shrink: 1/4 up/down: 26/-123 (-97)
> Function old new delta
> tcp_rcv_established 2238 2264 +26
> tcp_connect 4027 4003 -24
> tcp_tsq_write 152 120 -32
> tcp_send_active_reset 476 444 -32
> tcp_send_window_probe 235 200 -35
> Total: Before=25316710, After=25316613, chg -0.00%
>
> Signed-off-by: Eric Dumazet <edumazet@google.com>
> ---
Reviewed-by: Neal Cardwell <ncardwell@google.com>
Thanks, Eric!
neal
^ permalink raw reply
* [PATCH net-next 3/3] selftests: net: Add protodown tests
From: Ido Schimmel @ 2026-04-29 12:46 UTC (permalink / raw)
To: netdev
Cc: davem, kuba, pabeni, edumazet, andrew+netdev, horms, petrm,
Ido Schimmel
In-Reply-To: <20260429124624.835335-1-idosch@nvidia.com>
Add a selftest for the protodown mechanism using a macvlan device on
top of a dummy device.
Four test cases are included:
1. Basic protodown toggling: Verify that setting protodown results in
DOWN operational state and clearing it restores UP.
2. Protodown reasons: Verify that protodown cannot be cleared while
there are active protodown reasons, but can be cleared once all
reasons are removed.
3. Operational state inheritance: Verify that toggling the lower
device's carrier while protodown is on does not cause the macvlan to
inherit the UP operational state.
4. Lower layer down: Verify that toggling protodown while the lower
device has no carrier does not cause the macvlan to transition to UP
operational state.
Note that the last two test cases fail without "macvlan: Do not transfer
operational state when protodown is enabled" and "net: Add
.ndo_clear_proto_down":
# ./protodown.sh
TEST: Basic protodown on/off [ OK ]
TEST: Protodown reasons [ OK ]
TEST: Inheriting operational state with protodown [FAIL]
Macvlan operational state is not DOWN despite protodown
TEST: Protodown with lower layer down [FAIL]
Macvlan is not LOWERLAYERDOWN after clearing protodown
Assisted-by: Claude:claude-opus-4-6
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
---
tools/testing/selftests/net/Makefile | 1 +
tools/testing/selftests/net/protodown.sh | 160 +++++++++++++++++++++++
2 files changed, 161 insertions(+)
create mode 100755 tools/testing/selftests/net/protodown.sh
diff --git a/tools/testing/selftests/net/Makefile b/tools/testing/selftests/net/Makefile
index a275ed584026..70e0ab43dc5d 100644
--- a/tools/testing/selftests/net/Makefile
+++ b/tools/testing/selftests/net/Makefile
@@ -69,6 +69,7 @@ TEST_PROGS := \
nl_netdev.py \
nl_nlctrl.py \
pmtu.sh \
+ protodown.sh \
psock_snd.sh \
reuseaddr_ports_exhausted.sh \
reuseport_addr_any.sh \
diff --git a/tools/testing/selftests/net/protodown.sh b/tools/testing/selftests/net/protodown.sh
new file mode 100755
index 000000000000..4ad795d3d011
--- /dev/null
+++ b/tools/testing/selftests/net/protodown.sh
@@ -0,0 +1,160 @@
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0
+#
+# Test the "protodown" mechanism. Verify basic protodown toggling, protodown
+# reasons, operational state inheritance when the lower device carrier changes,
+# and correct operational state when the lower device has no carrier.
+
+# shellcheck disable=SC1091,SC2034,SC2154,SC2317
+source lib.sh
+
+require_command jq
+
+ALL_TESTS="
+ protodown_basic
+ protodown_reasons
+ protodown_inherit_operstate
+ protodown_lower_layer_down
+"
+
+operstate_get()
+{
+ local ns=$1; shift
+ local dev=$1; shift
+
+ ip -n "$ns" -j link show dev "$dev" | jq -r '.[].operstate'
+}
+
+operstate_check()
+{
+ local ns=$1; shift
+ local dev=$1; shift
+ local expected=$1; shift
+
+ local current
+ current=$(operstate_get "$ns" "$dev")
+
+ [ "$current" = "$expected" ]
+}
+
+setup_prepare()
+{
+ setup_ns NS
+ defer cleanup_all_ns
+
+ ip -n "$NS" link add name dummy0 type dummy
+ ip -n "$NS" link set dev dummy0 up
+
+ ip -n "$NS" link add name macvlan0 link dummy0 type macvlan mode bridge
+ ip -n "$NS" link set dev macvlan0 up
+}
+
+protodown_basic()
+{
+ RET=0
+
+ ip -n "$NS" link set dev macvlan0 protodown on
+ check_err $? "Failed to set protodown on"
+
+ busywait "$BUSYWAIT_TIMEOUT" operstate_check "$NS" macvlan0 DOWN
+ check_err $? "Operational state is not DOWN after setting protodown"
+
+ ip -n "$NS" link set dev macvlan0 protodown off
+ check_err $? "Failed to set protodown off"
+
+ busywait "$BUSYWAIT_TIMEOUT" operstate_check "$NS" macvlan0 UP
+ check_err $? "Operational state is not UP after clearing protodown"
+
+ log_test "Basic protodown on/off"
+}
+
+protodown_reasons()
+{
+ RET=0
+
+ ip -n "$NS" link set dev macvlan0 protodown on
+
+ ip -n "$NS" link set dev macvlan0 protodown_reason 0 on
+ check_err $? "Failed to set protodown reason bit 0"
+
+ # Cannot clear protodown while reasons are active.
+ ip -n "$NS" link set dev macvlan0 protodown off 2>/dev/null
+ check_fail $? "Clearing protodown succeeded with active reasons"
+
+ ip -n "$NS" link set dev macvlan0 protodown_reason 0 off
+ check_err $? "Failed to clear protodown reason bit 0"
+
+ # Can clear protodown when no reasons are active.
+ ip -n "$NS" link set dev macvlan0 protodown off
+ check_err $? "Failed to clear protodown with no active reasons"
+
+ busywait "$BUSYWAIT_TIMEOUT" operstate_check "$NS" macvlan0 UP
+ check_err $? "Operational state is not UP after clearing protodown"
+
+ log_test "Protodown reasons"
+}
+
+protodown_inherit_operstate()
+{
+ RET=0
+
+ ip -n "$NS" link set dev macvlan0 protodown on
+
+ busywait "$BUSYWAIT_TIMEOUT" operstate_check "$NS" macvlan0 DOWN
+ check_err $? "Operational state is not DOWN after setting protodown"
+
+ # Toggle carrier on the lower device. The macvlan should stay DOWN
+ # because protodown is on.
+ ip -n "$NS" link set dev dummy0 carrier off
+ ip -n "$NS" link set dev dummy0 carrier on
+
+ busywait "$BUSYWAIT_TIMEOUT" operstate_check "$NS" dummy0 UP
+ check_err $? "Lower device is not UP after carrier on"
+
+ busywait "$BUSYWAIT_TIMEOUT" operstate_check "$NS" macvlan0 DOWN
+ check_err $? "Macvlan operational state is not DOWN despite protodown"
+
+ # Clear protodown and verify the macvlan comes back up.
+ ip -n "$NS" link set dev macvlan0 protodown off
+
+ busywait "$BUSYWAIT_TIMEOUT" operstate_check "$NS" macvlan0 UP
+ check_err $? "Operational state is not UP after clearing protodown"
+
+ log_test "Inheriting operational state with protodown"
+}
+
+protodown_lower_layer_down()
+{
+ RET=0
+
+ # Bring the lower device carrier down first.
+ ip -n "$NS" link set dev dummy0 carrier off
+
+ busywait "$BUSYWAIT_TIMEOUT" operstate_check "$NS" macvlan0 LOWERLAYERDOWN
+ check_err $? "Macvlan is not LOWERLAYERDOWN with lower carrier off"
+
+ # Toggle protodown on and off while lower has no carrier. The macvlan
+ # should not transition to UP.
+ ip -n "$NS" link set dev macvlan0 protodown on
+ check_err $? "Failed to set protodown on"
+
+ busywait "$BUSYWAIT_TIMEOUT" operstate_check "$NS" macvlan0 LOWERLAYERDOWN
+ check_err $? "Macvlan is not LOWERLAYERDOWN after setting protodown"
+
+ ip -n "$NS" link set dev macvlan0 protodown off
+ check_err $? "Failed to set protodown off"
+
+ busywait "$BUSYWAIT_TIMEOUT" operstate_check "$NS" macvlan0 LOWERLAYERDOWN
+ check_err $? "Macvlan is not LOWERLAYERDOWN after clearing protodown"
+
+ log_test "Protodown with lower layer down"
+
+ ip -n "$NS" link set dev macvlan0 protodown off
+ ip -n "$NS" link set dev dummy0 carrier on
+}
+
+trap defer_scopes_cleanup EXIT
+setup_prepare
+tests_run
+
+exit "$EXIT_STATUS"
--
2.53.0
^ permalink raw reply related
* [PATCH net-next 2/3] macvlan: Do not transfer operational state when protodown is enabled
From: Ido Schimmel @ 2026-04-29 12:46 UTC (permalink / raw)
To: netdev
Cc: davem, kuba, pabeni, edumazet, andrew+netdev, horms, petrm,
Ido Schimmel
In-Reply-To: <20260429124624.835335-1-idosch@nvidia.com>
The protodown functionality allows user space to keep a macvlan down by
turning off its carrier:
# ip link add name dummy1 up type dummy
# ip link add name macvlan1 up link dummy1 type macvlan mode bridge
# ip link set dev macvlan1 protodown on
$ ip -br link show dev macvlan1
macvlan1@dummy1 DOWN 0a:5c:a3:05:c7:86 <NO-CARRIER,BROADCAST,MULTICAST,UP>
Different applications can set different protodown reasons, which
prevents an application from bringing up a macvlan as long as others
want it down:
# ip link set dev macvlan1 protodown_reason 1 on
# ip link set dev macvlan1 protodown_reason 2 on
# ip link set dev macvlan1 protodown off
Error: Cannot clear protodown, active reasons.
# ip link set dev macvlan1 protodown_reason 2 off
# ip link set dev macvlan1 protodown off
Error: Cannot clear protodown, active reasons.
# ip link set dev macvlan1 protodown_reason 1 off
# ip link set dev macvlan1 protodown off
$ ip -br link show dev macvlan1
macvlan1@dummy1 UP 0a:5c:a3:05:c7:86 <BROADCAST,MULTICAST,UP,LOWER_UP>
Unfortunately, this mechanism is not very useful when the macvlan can be
brought up by toggling the carrier of its lower device:
# ip link set dev macvlan1 protodown on
$ ip -br link show dev macvlan1
macvlan1@dummy1 DOWN 0a:5c:a3:05:c7:86 <NO-CARRIER,BROADCAST,MULTICAST,UP>
# ip link set dev dummy1 carrier off
# ip link set dev dummy1 carrier on
$ ip -br link show dev macvlan1
macvlan1@dummy1 UP 0a:5c:a3:05:c7:86 <BROADCAST,MULTICAST,UP,LOWER_UP>
Obviously, this is not the intended behavior and it is unlikely to be
relied on by anyone. In fact, it is a problem for applications like FRR
that use protodown with macvlan on top of a bridge as part of Virtual
Router Redundancy Protocol (VRRP).
Solve this by not transferring the operational state from the lower
device to the macvlan if protodown is enabled on the macvlan. Note that
READ_ONCE() is not needed as RTNL is held. Also note that vxlan (the
other driver that supports protodown) does not suffer from this problem.
Output with the patch:
# ip link add name dummy1 up type dummy
# ip link add name macvlan1 up link dummy1 type macvlan mode bridge
# ip link set dev macvlan1 protodown on
$ ip -br link show dev macvlan1
macvlan1@dummy1 DOWN 0a:5c:a3:05:c7:86 <NO-CARRIER,BROADCAST,MULTICAST,UP>
# ip link set dev dummy1 carrier off
# ip link set dev dummy1 carrier on
$ ip -br link show dev macvlan1
macvlan1@dummy1 DOWN 0a:5c:a3:05:c7:86 <NO-CARRIER,BROADCAST,MULTICAST,UP>
# ip link set dev macvlan1 protodown off
$ ip -br link show dev macvlan1
macvlan1@dummy1 UP 0a:5c:a3:05:c7:86 <BROADCAST,MULTICAST,UP,LOWER_UP>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
---
drivers/net/macvlan.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
index 61effa295c49..50c0bc8a38db 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -1822,9 +1822,12 @@ static int macvlan_device_event(struct notifier_block *unused,
case NETDEV_UP:
case NETDEV_DOWN:
case NETDEV_CHANGE:
- list_for_each_entry(vlan, &port->vlans, list)
+ list_for_each_entry(vlan, &port->vlans, list) {
+ if (vlan->dev->proto_down)
+ continue;
netif_stacked_transfer_operstate(vlan->lowerdev,
vlan->dev);
+ }
break;
case NETDEV_FEAT_CHANGE:
list_for_each_entry(vlan, &port->vlans, list) {
--
2.53.0
^ permalink raw reply related
* [PATCH net-next 1/3] net: Do not unconditionally turn on carrier when clearing protodown
From: Ido Schimmel @ 2026-04-29 12:46 UTC (permalink / raw)
To: netdev
Cc: davem, kuba, pabeni, edumazet, andrew+netdev, horms, petrm,
Ido Schimmel
In-Reply-To: <20260429124624.835335-1-idosch@nvidia.com>
The protodown functionality is currently supported by vxlan and macvlan
and it allows to keep an interface down by turning off its carrier:
# ip link add name dummy1 up type dummy
# ip link add name macvlan1 up link dummy1 type macvlan mode bridge
# ip link set dev macvlan1 protodown on
$ ip -br link show dev macvlan1
macvlan1@dummy1 DOWN 0a:5c:a3:05:c7:86 <NO-CARRIER,BROADCAST,MULTICAST,UP>
When protodown is cleared, the core unconditionally enables carrier on
the interface:
# ip link set dev macvlan1 protodown off
$ ip -br link show dev macvlan1
macvlan1@dummy1 UP 0a:5c:a3:05:c7:86 <BROADCAST,MULTICAST,UP,LOWER_UP>
This is wrong as it means that a macvlan can end up with a carrier when
its lower device does not have a carrier:
# ip link set dev dummy1 carrier off
$ ip -br link show dev macvlan1
macvlan1@dummy1 LOWERLAYERDOWN 0a:5c:a3:05:c7:86 <NO-CARRIER,BROADCAST,MULTICAST,UP>
# ip link set dev macvlan1 protodown on
# ip link set dev macvlan1 protodown off
$ ip -br link show dev macvlan1
macvlan1@dummy1 UP 0a:5c:a3:05:c7:86 <BROADCAST,MULTICAST,UP,LOWER_UP>
Solve this by adding a new NDO that allows different drivers to react
differently to protodown being cleared. Change the core to invoke the
NDO and implement it for vxlan and macvlan. Maintain the current
behavior for the former, but for macvlan implement the NDO by
transferring the operational state from its lower device.
Output with the patch:
# ip link add name dummy1 up type dummy
# ip link add name macvlan1 up link dummy1 type macvlan mode bridge
# ip link set dev dummy1 carrier off
$ ip -br link show dev macvlan1
macvlan1@dummy1 LOWERLAYERDOWN 0a:5c:a3:05:c7:86 <NO-CARRIER,BROADCAST,MULTICAST,UP>
# ip link set dev macvlan1 protodown on
# ip link set dev macvlan1 protodown off
$ ip -br link show dev macvlan1
macvlan1@dummy1 LOWERLAYERDOWN 0a:5c:a3:05:c7:86 <NO-CARRIER,BROADCAST,MULTICAST,UP>
# ip link set dev dummy1 carrier on
$ ip -br link show dev macvlan1
macvlan1@dummy1 UP 0a:5c:a3:05:c7:86 <BROADCAST,MULTICAST,UP,LOWER_UP>
# ip link set dev macvlan1 protodown on
# ip link set dev macvlan1 protodown off
$ ip -br link show dev macvlan1
macvlan1@dummy1 UP 0a:5c:a3:05:c7:86 <BROADCAST,MULTICAST,UP,LOWER_UP>
Make the NDO only about clearing protodown to avoid suspicion that this
is about re-introducing the NDO that was removed by commit 2106efda785b
("net: remove .ndo_change_proto_down").
Remove net_device::change_proto_down since we can now use the presence
of the new NDO as an indication that changing protodown is supported.
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
---
Documentation/networking/net_cachelines/net_device.rst | 1 -
drivers/net/macvlan.c | 7 ++++++-
drivers/net/vxlan/vxlan_core.c | 8 +++++++-
include/linux/netdevice.h | 6 ++++--
net/core/dev.c | 4 ++--
net/core/rtnetlink.c | 2 +-
6 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/Documentation/networking/net_cachelines/net_device.rst b/Documentation/networking/net_cachelines/net_device.rst
index 1c19bb7705df..267af4957b0d 100644
--- a/Documentation/networking/net_cachelines/net_device.rst
+++ b/Documentation/networking/net_cachelines/net_device.rst
@@ -167,7 +167,6 @@ struct lock_class_key* qdisc_tx_busylock
bool proto_down
unsigned:1 wol_enabled
unsigned_long:1 see_all_hwtstamp_requests
-unsigned_long:1 change_proto_down
unsigned_long:1 netns_immutable
unsigned_long:1 fcoe_mtu
struct list_head net_notifier_list
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
index c40fa331836b..61effa295c49 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -904,6 +904,11 @@ static int macvlan_hwtstamp_set(struct net_device *dev,
return generic_hwtstamp_set_lower(real_dev, cfg, extack);
}
+static void macvlan_clear_proto_down(struct net_device *dev)
+{
+ netif_stacked_transfer_operstate(macvlan_dev_real_dev(dev), dev);
+}
+
/*
* macvlan network devices have devices nesting below it and are a special
* "super class" of normal network devices; split their locks off into a
@@ -1211,6 +1216,7 @@ static const struct net_device_ops macvlan_netdev_ops = {
.ndo_features_check = passthru_features_check,
.ndo_hwtstamp_get = macvlan_hwtstamp_get,
.ndo_hwtstamp_set = macvlan_hwtstamp_set,
+ .ndo_clear_proto_down = macvlan_clear_proto_down,
};
static void macvlan_dev_free(struct net_device *dev)
@@ -1230,7 +1236,6 @@ void macvlan_common_setup(struct net_device *dev)
dev->priv_flags &= ~IFF_TX_SKB_SHARING;
netif_keep_dst(dev);
dev->priv_flags |= IFF_UNICAST_FLT;
- dev->change_proto_down = true;
dev->netdev_ops = &macvlan_netdev_ops;
dev->needs_free_netdev = true;
dev->priv_destructor = macvlan_dev_free;
diff --git a/drivers/net/vxlan/vxlan_core.c b/drivers/net/vxlan/vxlan_core.c
index e88798497503..a3ed9fbd60a6 100644
--- a/drivers/net/vxlan/vxlan_core.c
+++ b/drivers/net/vxlan/vxlan_core.c
@@ -3271,6 +3271,11 @@ static int vxlan_fill_metadata_dst(struct net_device *dev, struct sk_buff *skb)
return 0;
}
+static void vxlan_clear_proto_down(struct net_device *dev)
+{
+ netif_carrier_on(dev);
+}
+
static const struct net_device_ops vxlan_netdev_ether_ops = {
.ndo_init = vxlan_init,
.ndo_uninit = vxlan_uninit,
@@ -3292,6 +3297,7 @@ static const struct net_device_ops vxlan_netdev_ether_ops = {
.ndo_mdb_dump = vxlan_mdb_dump,
.ndo_mdb_get = vxlan_mdb_get,
.ndo_fill_metadata_dst = vxlan_fill_metadata_dst,
+ .ndo_clear_proto_down = vxlan_clear_proto_down,
};
static const struct net_device_ops vxlan_netdev_raw_ops = {
@@ -3302,6 +3308,7 @@ static const struct net_device_ops vxlan_netdev_raw_ops = {
.ndo_start_xmit = vxlan_xmit,
.ndo_change_mtu = vxlan_change_mtu,
.ndo_fill_metadata_dst = vxlan_fill_metadata_dst,
+ .ndo_clear_proto_down = vxlan_clear_proto_down,
};
/* Info for udev, that this is a virtual tunnel endpoint */
@@ -3368,7 +3375,6 @@ static void vxlan_setup(struct net_device *dev)
netif_keep_dst(dev);
dev->priv_flags |= IFF_NO_QUEUE;
- dev->change_proto_down = true;
dev->lltx = true;
/* MTU range: 68 - 65535 */
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 0e1e581efc5a..3757dd6604b8 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -1432,6 +1432,9 @@ struct netdev_net_notifier {
* struct kernel_hwtstamp_config *kernel_config,
* struct netlink_ext_ack *extack);
* Change the hardware timestamping parameters for NIC device.
+ *
+ * void (*ndo_clear_proto_down)(struct net_device *dev);
+ * Enable carrier after dev->proto_down was cleared.
*/
struct net_device_ops {
int (*ndo_init)(struct net_device *dev);
@@ -1683,6 +1686,7 @@ struct net_device_ops {
int (*ndo_hwtstamp_set)(struct net_device *dev,
struct kernel_hwtstamp_config *kernel_config,
struct netlink_ext_ack *extack);
+ void (*ndo_clear_proto_down)(struct net_device *dev);
#if IS_ENABLED(CONFIG_NET_SHAPER)
/**
@@ -2062,7 +2066,6 @@ enum netdev_reg_state {
* ndo_hwtstamp_set() for all timestamp requests
* regardless of source, even if those aren't
* HWTSTAMP_SOURCE_NETDEV
- * @change_proto_down: device supports setting carrier via IFLA_PROTO_DOWN
* @netns_immutable: interface can't change network namespaces
* @fcoe_mtu: device supports maximum FCoE MTU, 2158 bytes
*
@@ -2476,7 +2479,6 @@ struct net_device {
/* priv_flags_slow, ungrouped to save space */
unsigned long see_all_hwtstamp_requests:1;
- unsigned long change_proto_down:1;
unsigned long netns_immutable:1;
unsigned long fcoe_mtu:1;
diff --git a/net/core/dev.c b/net/core/dev.c
index 06c195906231..ff66762592e4 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -10143,14 +10143,14 @@ EXPORT_SYMBOL(netdev_port_same_parent_id);
int netif_change_proto_down(struct net_device *dev, bool proto_down)
{
- if (!dev->change_proto_down)
+ if (!dev->netdev_ops->ndo_clear_proto_down)
return -EOPNOTSUPP;
if (!netif_device_present(dev))
return -ENODEV;
if (proto_down)
netif_carrier_off(dev);
else
- netif_carrier_on(dev);
+ dev->netdev_ops->ndo_clear_proto_down(dev);
WRITE_ONCE(dev->proto_down, proto_down);
return 0;
}
diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c
index b613bb6e07df..30951e5a9555 100644
--- a/net/core/rtnetlink.c
+++ b/net/core/rtnetlink.c
@@ -3009,7 +3009,7 @@ static int do_set_proto_down(struct net_device *dev,
bool proto_down;
int err;
- if (!dev->change_proto_down) {
+ if (!dev->netdev_ops->ndo_clear_proto_down) {
NL_SET_ERR_MSG(extack, "Protodown not supported by device");
return -EOPNOTSUPP;
}
--
2.53.0
^ permalink raw reply related
* [PATCH net-next 0/3] net: Fix protodown with macvlan
From: Ido Schimmel @ 2026-04-29 12:46 UTC (permalink / raw)
To: netdev
Cc: davem, kuba, pabeni, edumazet, andrew+netdev, horms, petrm,
Ido Schimmel
When protodown is enabled on a macvlan, two bugs cause the macvlan to
incorrectly report an UP operational state:
1. Toggling protodown on and then off on the macvlan while the lower
device has no carrier causes the macvlan to report UP instead of
LOWERLAYERDOWN, since netif_change_proto_down() unconditionally turns
the carrier on.
2. Toggling the lower device's carrier while protodown is enabled on the
macvlan causes the macvlan to inherit the UP operational state,
effectively bypassing the protodown mechanism.
Patch #1 solves the first problem by introducing a new NDO that allows
different drivers to react differently to protodown being cleared. For
macvlan it is implemented by transferring the operational state from the
lower device. For vxlan (the other driver that supports protodown) it
continues to be implemented by turning on the carrier.
Patch #2 prevents a macvlan with protodown enabled from inheriting the
operational state of its lower device.
Patch #3 adds a selftest covering both bugs and the basic protodown
functionality.
Targeting at net-next since these are not regressions (i.e., never
worked).
Ido Schimmel (3):
net: Do not unconditionally turn on carrier when clearing protodown
macvlan: Do not transfer operational state when protodown is enabled
selftests: net: Add protodown tests
.../networking/net_cachelines/net_device.rst | 1 -
drivers/net/macvlan.c | 12 +-
drivers/net/vxlan/vxlan_core.c | 8 +-
include/linux/netdevice.h | 6 +-
net/core/dev.c | 4 +-
net/core/rtnetlink.c | 2 +-
tools/testing/selftests/net/Makefile | 1 +
tools/testing/selftests/net/protodown.sh | 160 ++++++++++++++++++
8 files changed, 185 insertions(+), 9 deletions(-)
create mode 100755 tools/testing/selftests/net/protodown.sh
--
2.53.0
^ permalink raw reply
* Re: [bug report] Potential refcounting
From: Jason Gunthorpe @ 2026-04-29 12:44 UTC (permalink / raw)
To: Ginger; +Cc: Tariq Toukan, netdev, linux-rdma, ttoukan.linux
In-Reply-To: <CAGp+u1baSuC9z9rGkJR0v1+eBW==9ppxh7tSn19jJOA9bX1Ycg@mail.gmail.com>
On Wed, Apr 29, 2026 at 06:13:40PM +0800, Ginger wrote:
> Side note: to see if T1 (i.e., IRQ) can fire, I checked the calling
> path to 'mlx4_cq_free' and only 'synchronize_irq()' is seen, but not
> 'disable_irq()'. It means that T1 may still happen after T0 calls
> 'mlx4_cq_free()'.
synchronize_irq() is supposed to wait for any concurrently running IRQ
threads to finish. New IRQ threads will then be guarenteed to see the
radix_tree_delete() and can't see the CQ being removed here.
Since the refcount is != 0 until after synchronize_irq(), and the irq
can't see the cq after synchronize_irq() there should be no issue.
Jason
^ permalink raw reply
* Re: [RFC PATCH net-next 1/2] net: napi: Fix interrupts permanently disabled during busy poll
From: Dragos Tatulea @ 2026-04-29 12:43 UTC (permalink / raw)
To: Björn Töpel, Jakub Kicinski
Cc: David S. Miller, Eric Dumazet, Paolo Abeni, Simon Horman,
Daniel Borkmann, Martin Karsten, Gal Pressman, Tariq Toukan,
Joe Damato, Frederik Deweerdt, netdev, linux-kernel
In-Reply-To: <87o6j2hslk.fsf@all.your.base.are.belong.to.us>
On Wed, Apr 29, 2026 at 02:13:43PM +0200, Björn Töpel wrote:
> Dragos Tatulea <dtatulea@nvidia.com> writes:
>
> > On Tue, Apr 28, 2026 at 05:38:44PM -0700, Jakub Kicinski wrote:
> >> On Tue, 28 Apr 2026 17:51:30 +0000 Dragos Tatulea wrote:
> >> > + local_irq_save(flags);
> >> > + hrtimer_start(&napi->timer, ns_to_ktime(timeout),
> >> > + HRTIMER_MODE_REL_PINNED);
> >> > clear_bit(NAPI_STATE_SCHED, &napi->state);
> >> > + local_irq_restore(flags);
> >>
> >> I don't think disabling IRQ is necessary?
> >> Isn't it legal to clear the bit first then schedule the timer?
> >> The timer does not own the napi instance.
> >
> > Isn't the following scenario possible (but extremely unlikely)?
> >
> > 1. busy_poll_stop(): napi timer is schedueled.
> > 2. Hard irq pre-empts busy_poll_stop() and takes an unusually long time.
> > 4. napi timer triggers (also hard irq), napi_watchdog() skips schedule
> > because NAPI_STATE_SCHED is set.
> > 5. busy_poll_stop(): NAPI_STATE_SCHED gets cleared.
>
> (Nice work finding the bug! I had to jog my memory to understand the
> gnarly busy-poll details again!)
>
> You're right that you need the save/restore if you do arm timer/clear,
> but not if you do what Jakub suggests.
>
> clear_bit(...);
> hrtimer_start();
>
Ah sorry, I didn't read it right the first time because I was too fixed
on the order.
> That would also follow the scheme in napi_schedule_done(). (Note that
> swapping arm/clear does mean that we can get a wasted-timer outcome.)
>
If it is wasted is fine. I figured that this could end up with a timer
scheduled after the napi deletion:
1. busy_poll_stop(): clears SCHED bit.
2. napi_disable() runs past SCHED wait, cancels timer and caller
deletes napi mem.
3. busy_poll_stop(): napi->timer is armed but napi is freed memory
by now.
What am I missing here?
Thanks,
Dragos
^ permalink raw reply
* Re: [PATCH RFC] net/mlx5: check whether VFs are assigned before disabling SR-IOV
From: Jason Gunthorpe @ 2026-04-29 12:38 UTC (permalink / raw)
To: mboone
Cc: Saeed Mahameed, Leon Romanovsky, Tariq Toukan, Mark Bloch,
Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, netdev, linux-rdma, linux-kernel
In-Reply-To: <20260428-mlx5-sriov-in-use-check-v1-1-c7b9e18c99a8@akamai.com>
On Tue, Apr 28, 2026 at 08:04:14PM +0200, Max Boone via B4 Relay wrote:
> From: Max Boone <mboone@akamai.com>
>
> When MLX5 cards are passed through to a VM, disabling SR-IOV by
> setting the sriov_numvfs to 0 will render the machine unstable.
What? How does that happen?
> -void mlx5_sriov_disable(struct pci_dev *pdev, bool num_vf_change)
> +int mlx5_sriov_disable(struct pci_dev *pdev, bool num_vf_change)
> {
> struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
> struct devlink *devlink = priv_to_devlink(dev);
> int num_vfs = pci_num_vf(dev->pdev);
>
> + if (pci_vfs_assigned(dev->pdev)) {
> + mlx5_core_warn(dev, "can't disable sriov, VFs are assigned\n");
> + return -EPERM;
> + }
*barf* WTF did this come from?
Grep says only Xen makes this true, so this is all working around some
Xen brokenness in their "assignment" ?
If people care about Xen pci_is_dev_assigned() should be be purged and
pciback should be fixed to not "make the machine unstable" when it is
removed during a VF teardown.
Or at the very least this nasty Xen intrustion should be placed in the
PCI core code and removed from the drivers.
Also, no, you can't fail mlx5_sriov_disable() it is called during
driver remove and cannot fail in that flow.
Jason
^ permalink raw reply
* Re: [RFC PATCH net-next 2/2] net: napi: Skip poll when arming GRO timer in busy poll
From: Björn Töpel @ 2026-04-29 12:37 UTC (permalink / raw)
To: Dragos Tatulea, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Simon Horman
Cc: Martin Karsten, dtatulea, Gal Pressman, Tariq Toukan, Joe Damato,
Frederik Deweerdt, netdev, linux-kernel
In-Reply-To: <20260428175134.1197036-4-dtatulea@nvidia.com>
Dragos Tatulea <dtatulea@nvidia.com> writes:
> From: Martin Karsten <mkarsten@uwaterloo.ca>
>
> As referenced in the previous patch, having the GRO timer scheduled
> while poll is running can lead to issues.
Outline the issues here as well, so we don't need to cross-reference the
kernel logs.
> Skip the extra call to napi->poll() when the GRO timer is armed. This
> removes the need for having a separate __busy_poll_stop routine and its
> code is moved directly into the relevant places in busy_poll_stop.
Nice!
> Signed-off-by: Martin Karsten <mkarsten@uwaterloo.ca>
> Co-developed-by: Dragos Tatulea <dtatulea@nvidia.com>
> Signed-off-by: Dragos Tatulea <dtatulea@nvidia.com>
> ---
> net/core/dev.c | 61 +++++++++++++++++++++++++-------------------------
> 1 file changed, 30 insertions(+), 31 deletions(-)
>
> diff --git a/net/core/dev.c b/net/core/dev.c
> index 1487d4946dcf..d4829c2484f5 100644
> --- a/net/core/dev.c
> +++ b/net/core/dev.c
> @@ -6869,26 +6869,6 @@ static void skb_defer_free_flush(void)
>
> #if defined(CONFIG_NET_RX_BUSY_POLL)
>
> -static void __busy_poll_stop(struct napi_struct *napi, unsigned long timeout)
> -{
> - unsigned long flags;
> -
> - if (!timeout) {
> - gro_normal_list(&napi->gro);
> - __napi_schedule(napi);
> - return;
> - }
> -
> - /* Flush too old packets. If HZ < 1000, flush all packets */
> - gro_flush_normal(&napi->gro, HZ >= 1000);
> -
> - local_irq_save(flags);
> - hrtimer_start(&napi->timer, ns_to_ktime(timeout),
> - HRTIMER_MODE_REL_PINNED);
> - clear_bit(NAPI_STATE_SCHED, &napi->state);
> - local_irq_restore(flags);
> -}
> -
> enum {
> NAPI_F_PREFER_BUSY_POLL = 1,
> NAPI_F_END_ON_RESCHED = 2,
> @@ -6898,14 +6878,14 @@ static void busy_poll_stop(struct napi_struct *napi, void *have_poll_lock,
> unsigned flags, u16 budget)
> {
> struct bpf_net_context __bpf_net_ctx, *bpf_net_ctx;
> - unsigned long timeout = 0;
> + unsigned long timeout;
> int rc;
>
> /* Busy polling means there is a high chance device driver hard irq
> * could not grab NAPI_STATE_SCHED, and that NAPI_STATE_MISSED was
> * set in napi_schedule_prep().
> - * Since we are about to call napi->poll() once more, we can safely
> - * clear NAPI_STATE_MISSED.
> + * Since we either call napi->poll() once more or start the timer,
> + * we can safely clear NAPI_STATE_MISSED.
> *
> * Note: x86 could use a single "lock and ..." instruction
> * to perform these two clear_bit()
> @@ -6918,13 +6898,28 @@ static void busy_poll_stop(struct napi_struct *napi, void *have_poll_lock,
>
> if (flags & NAPI_F_PREFER_BUSY_POLL) {
> napi->defer_hard_irqs_count = napi_get_defer_hard_irqs(napi);
> - if (napi->defer_hard_irqs_count) {
> - /* Timer will be scheduled after napi poll to avoid
> - * firing during a slow poll which could cause the
> - * queue to get stuck with interrupts disabled and no
> - * scheduled timer.
> + timeout = napi_get_gro_flush_timeout(napi);
> + if (napi->defer_hard_irqs_count && timeout) {
> + unsigned long flags;
> +
> + /* Drop prefer-busy state as in napi_complete_done(). */
> + clear_bit(NAPI_STATE_PREFER_BUSY_POLL, &napi->state);
> + netpoll_poll_unlock(have_poll_lock);
> +
> + /* Flush too old packets. If HZ < 1000, flush all
> + * packets.
> + */
> + gro_flush_normal(&napi->gro, HZ >= 1000);
> + local_irq_save(flags);
> + hrtimer_start(&napi->timer, ns_to_ktime(timeout),
> + HRTIMER_MODE_REL_PINNED);
> + clear_bit(NAPI_STATE_SCHED, &napi->state);
> + local_irq_restore(flags);
(Same swap arm timer/clear as patch 1.)
> +
> + /* Timer started, so need for another call to
^
"so *NO* need for another..."
Björn
^ permalink raw reply
* Re: [PATCH net-next] net: core: Call netif_get_rxqueue() in get_rps_cpu()
From: Eric Dumazet @ 2026-04-29 12:31 UTC (permalink / raw)
To: Yue Haibing; +Cc: davem, kuba, pabeni, horms, netdev, linux-kernel
In-Reply-To: <20260429123741.3777677-1-yuehaibing@huawei.com>
On Wed, Apr 29, 2026 at 5:15 AM Yue Haibing <yuehaibing@huawei.com> wrote:
>
> Refactor netif_get_rxqueue() return NULL when rxq index checking failed
> instead of falling back to first queue, then use it to avoid code
> duplication.
>
> Signed-off-by: Yue Haibing <yuehaibing@huawei.com>
> ---
> net/core/dev.c | 24 +++++++++---------------
> 1 file changed, 9 insertions(+), 15 deletions(-)
>
This code (get_rps_cpu()) is super hot for some of us.
Are you sure netif_get_rxqueue() is kept inline?
I do not think gcc is smart enough:
scripts/bloat-o-meter -t net/core/dev.o.before net/core/dev.o.after
add/remove: 1/0 grow/shrink: 2/2 up/down: 116/-132 (-16)
Function old new delta
netif_get_rxqueue.isra - 84 +84
dev_getbyhwaddr_rcu 133 149 +16
__netif_set_xps_queue 2837 2853 +16
bpf_prog_run_generic_xdp 899 846 -53
get_rps_cpu 835 756 -79
// This is bad,
Total: Before=90848, After=90832, chg -0.02%
^ permalink raw reply
* [PATCH net-next] net: core: Call netif_get_rxqueue() in get_rps_cpu()
From: Yue Haibing @ 2026-04-29 12:37 UTC (permalink / raw)
To: davem, edumazet, kuba, pabeni, horms; +Cc: netdev, linux-kernel, yuehaibing
Refactor netif_get_rxqueue() return NULL when rxq index checking failed
instead of falling back to first queue, then use it to avoid code
duplication.
Signed-off-by: Yue Haibing <yuehaibing@huawei.com>
---
net/core/dev.c | 24 +++++++++---------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/net/core/dev.c b/net/core/dev.c
index e7bc95cbd1fa..72aef872d03c 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -5104,6 +5104,8 @@ set_rps_cpu(struct net_device *dev, struct sk_buff *skb,
return rflow;
}
+static struct netdev_rx_queue *netif_get_rxqueue(struct sk_buff *skb);
+
/*
* get_rps_cpu is called from netif_receive_skb and returns the target
* CPU from the RPS map of the receiving queue for a given skb.
@@ -5112,25 +5114,16 @@ set_rps_cpu(struct net_device *dev, struct sk_buff *skb,
static int get_rps_cpu(struct net_device *dev, struct sk_buff *skb,
struct rps_dev_flow **rflowp)
{
- struct netdev_rx_queue *rxqueue = dev->_rx;
+ struct netdev_rx_queue *rxqueue;
rps_tag_ptr global_tag_ptr, q_tag_ptr;
struct rps_map *map;
int cpu = -1;
u32 tcpu;
u32 hash;
- if (skb_rx_queue_recorded(skb)) {
- u16 index = skb_get_rx_queue(skb);
-
- if (unlikely(index >= dev->real_num_rx_queues)) {
- WARN_ONCE(dev->real_num_rx_queues > 1,
- "%s received packet on queue %u, but number "
- "of RX queues is %u\n",
- dev->name, index, dev->real_num_rx_queues);
- goto done;
- }
- rxqueue += index;
- }
+ rxqueue = netif_get_rxqueue(skb);
+ if (!rxqueue)
+ goto done;
/* Avoid computing hash if RFS/RPS is not active for this rxqueue */
@@ -5442,8 +5435,7 @@ static struct netdev_rx_queue *netif_get_rxqueue(struct sk_buff *skb)
"%s received packet on queue %u, but number "
"of RX queues is %u\n",
dev->name, index, dev->real_num_rx_queues);
-
- return rxqueue; /* Return first rxqueue */
+ return NULL;
}
rxqueue += index;
}
@@ -5473,6 +5465,8 @@ u32 bpf_prog_run_generic_xdp(struct sk_buff *skb, struct xdp_buff *xdp,
frame_sz += SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
rxqueue = netif_get_rxqueue(skb);
+ if (!rxqueue)
+ rxqueue = skb->dev->_rx;
xdp_init_buff(xdp, frame_sz, &rxqueue->xdp_rxq);
xdp_prepare_buff(xdp, hard_start, skb_headroom(skb) - mac_len,
skb_headlen(skb) + mac_len, true);
--
2.34.1
^ permalink raw reply related
* Re: [RFC PATCH net-next 1/2] net: napi: Fix interrupts permanently disabled during busy poll
From: Björn Töpel @ 2026-04-29 12:13 UTC (permalink / raw)
To: Dragos Tatulea, Jakub Kicinski
Cc: David S. Miller, Eric Dumazet, Paolo Abeni, Simon Horman,
Daniel Borkmann, Martin Karsten, Gal Pressman, Tariq Toukan,
Joe Damato, Frederik Deweerdt, netdev, linux-kernel
In-Reply-To: <36csl4lgsy3psknzdpssq4zc2zsy36negybhhvfhozthhnmfl4@c6y75w6udaiv>
Dragos Tatulea <dtatulea@nvidia.com> writes:
> On Tue, Apr 28, 2026 at 05:38:44PM -0700, Jakub Kicinski wrote:
>> On Tue, 28 Apr 2026 17:51:30 +0000 Dragos Tatulea wrote:
>> > + local_irq_save(flags);
>> > + hrtimer_start(&napi->timer, ns_to_ktime(timeout),
>> > + HRTIMER_MODE_REL_PINNED);
>> > clear_bit(NAPI_STATE_SCHED, &napi->state);
>> > + local_irq_restore(flags);
>>
>> I don't think disabling IRQ is necessary?
>> Isn't it legal to clear the bit first then schedule the timer?
>> The timer does not own the napi instance.
>
> Isn't the following scenario possible (but extremely unlikely)?
>
> 1. busy_poll_stop(): napi timer is schedueled.
> 2. Hard irq pre-empts busy_poll_stop() and takes an unusually long time.
> 4. napi timer triggers (also hard irq), napi_watchdog() skips schedule
> because NAPI_STATE_SCHED is set.
> 5. busy_poll_stop(): NAPI_STATE_SCHED gets cleared.
(Nice work finding the bug! I had to jog my memory to understand the
gnarly busy-poll details again!)
You're right that you need the save/restore if you do arm timer/clear,
but not if you do what Jakub suggests.
clear_bit(...);
hrtimer_start();
That would also follow the scheme in napi_schedule_done(). (Note that
swapping arm/clear does mean that we can get a wasted-timer outcome.)
Björn
^ permalink raw reply
* Re: [PATCH net-next 00/11] net: devmem: support devmem with netkit devices
From: Daniel Borkmann @ 2026-04-29 12:08 UTC (permalink / raw)
To: Bobby Eshleman, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Jonathan Corbet,
Shuah Khan, Alex Shi, Yanteng Si, Dongliang Mu, Michael Chan,
Pavan Chebbi, Joshua Washington, Harshitha Ramamurthy,
Saeed Mahameed, Tariq Toukan, Mark Bloch, Leon Romanovsky,
Alexander Duyck, kernel-team, Nikolay Aleksandrov, Shuah Khan,
David Wei
Cc: netdev, linux-doc, linux-kernel, linux-rdma, bpf, linux-kselftest,
Stanislav Fomichev, Mina Almasry, Bobby Eshleman
In-Reply-To: <20260428-tcp-dm-netkit-v1-0-719280eba4d2@meta.com>
Hi Bobby,
On 4/29/26 12:41 AM, Bobby Eshleman wrote:
> This series enables TCP devmem TX through netkit devices.
>
> Netkit now supports queue leasing. A physical NIC's RX queue can be
> leased to a netkit guest interface inside a container namespace. This
> gives the container a devmem-capable data path on the RX side (bind-rx,
> etc...). On the TX side, the container process binds to its netkit guest
> interface and sends traffic that netkit redirects (via BPF or ip
> forwarding) to the physical NIC for DMA.
[...]
Thanks for working on this, after the RX queue leasing got merged, I've
been looking into the same actually. :)
I think the NETMEM_TX_* enum approach seems reasonable.
What I have a PoC on is to build out TX queue leasing as first-class
symmetric infrastructure to complement the RX queue leasing - basically
I implemented an equivalent to the latter in netdev_nl_queue_create_doit
et al, so you can have independent RX and TX leases and per-queue
accountability, such that ynl queue-get op shows the full picture, and
lastly we could also enable AF_XDP TX-only support through this infra.
Would you be open to collab on integrating both and migrating the devmem
code to work off an TX queue object? Next week is LSF/MM/BPF, are you
there by any chance to catch up in person?
Thanks a lot,
Daniel
^ permalink raw reply
* [PATCH net v2] net: airoha: Move entries to queue head in case of DMA mapping failure in airoha_dev_xmit()
From: Lorenzo Bianconi @ 2026-04-29 12:02 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Jacob Keller, Lorenzo Bianconi
Cc: Simon Horman, linux-arm-kernel, linux-mediatek, netdev
In order to respect the original descriptor order and avoid any
potential IOMMU fault or memory corruption, move pending queue entries
to the head of hw queue tx_list if the DMA mapping of current inflight
packet fails in airoha_dev_xmit routine.
Fixes: 3f47e67dff1f7 ("net: airoha: Add the capability to consume out-of-order DMA tx descriptors")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
Changes in v2:
- Remove leftover airoha_queue_entry initialization inside the loop from
the previous version.
- Link to v1: https://lore.kernel.org/r/20260428-airoha-xmit-unmap-error-path-v1-1-aec44c6765c1@kernel.org
---
drivers/net/ethernet/airoha/airoha_eth.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 5effb4a4ae84..fb4f51d67dd7 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2123,14 +2123,12 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
return NETDEV_TX_OK;
error_unmap:
- while (!list_empty(&tx_list)) {
- e = list_first_entry(&tx_list, struct airoha_queue_entry,
- list);
+ list_for_each_entry(e, &tx_list, list) {
dma_unmap_single(dev->dev.parent, e->dma_addr, e->dma_len,
DMA_TO_DEVICE);
e->dma_addr = 0;
- list_move_tail(&e->list, &q->tx_list);
}
+ list_splice(&tx_list, &q->tx_list);
spin_unlock_bh(&q->lock);
error:
---
base-commit: 0c7a5ba011d336df4fcd1f667fcc16ea5549be12
change-id: 20260428-airoha-xmit-unmap-error-path-8125594efb23
Best regards,
--
Lorenzo Bianconi <lorenzo@kernel.org>
^ permalink raw reply related
* [PATCH net 2/2] ovpn: ensure gro_cells_receive() is invoked with BH disabled
From: Antonio Quartulli @ 2026-04-29 12:01 UTC (permalink / raw)
To: netdev
Cc: ralf, Sabrina Dubroca, Jakub Kicinski, Paolo Abeni, Andrew Lunn,
David S. Miller, Eric Dumazet, Antonio Quartulli
In-Reply-To: <20260429120120.514491-1-antonio@openvpn.net>
From: Ralf Lici <ralf@mandelbit.com>
ovpn injects decrypted packets into the netdev RX path through
ovpn_netdev_write() -> gro_cells_receive().
In case of TCP connections, that injection path can be reached
from either softirq or process context.
However, gro_cells_receive() expects to be invoked in softirq
context to avoid racing its lock acquisition.
When being invoked from process context, we must ensure BH are
disabled to safeguard gro_cells_receive() assumption.
As of now this is not the case and the following WARNING is
triggered:
[ 230.183747][ T12] WARNING: net/core/gro_cells.c:30 at gro_cells_receive+0x708/0xaa0, CPU#1: kworker/u16:0/12
Moreover, not disabling BH was also triggering lockdep, which was
reporting a potential deadlock in case of concurrent softirq and
process context gro_cells->bh_lock acquisition (i.e in case of
concurrent UDP and TCP connection for the same ovpn interface):
WARNING: inconsistent lock state
7.0.0-rc4+ #246 Tainted: G W
--------------------------------
inconsistent {IN-SOFTIRQ-W} -> {SOFTIRQ-ON-W} usage.
Fix all this by invoking local_bh_disable/enable() around
gro_cells_receive().
Fixes: 11851cbd60ea ("ovpn: implement TCP transport")
Signed-off-by: Ralf Lici <ralf@mandelbit.com>
Signed-off-by: Antonio Quartulli <antonio@openvpn.net>
---
drivers/net/ovpn/io.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ovpn/io.c b/drivers/net/ovpn/io.c
index d92bb87be2b2..c0fdb9504241 100644
--- a/drivers/net/ovpn/io.c
+++ b/drivers/net/ovpn/io.c
@@ -91,7 +91,13 @@ static void ovpn_netdev_write(struct ovpn_peer *peer, struct sk_buff *skb)
/* cause packet to be "received" by the interface */
pkt_len = skb->len;
+ /* we may get here in process context in case of TCP connections,
+ * therefore we have to disable BHs to ensure gro_cells_receive()
+ * doesn't enter deadlock
+ */
+ local_bh_disable();
ret = gro_cells_receive(&peer->ovpn->gro_cells, skb);
+ local_bh_enable();
if (likely(ret == NET_RX_SUCCESS)) {
/* update RX stats with the size of decrypted packet */
ovpn_peer_stats_increment_rx(&peer->vpn_stats, pkt_len);
--
2.53.0
^ permalink raw reply related
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