* [GIT PULL] wireless-next-2026-04-30
From: Johannes Berg @ 2026-04-30 12:02 UTC (permalink / raw)
To: netdev; +Cc: linux-wireless
Hi,
Looks like 7.2 is going to be interesting with NAN and UHR
both getting major work, but for now we have some (relatively)
minor things - the biggest is the station bandwidth rework,
which is needed en route to UHR.
Please pull and let us know if there's any problem.
Thanks,
johannes
The following changes since commit 254f49634ee16a731174d2ae34bc50bd5f45e731:
Linux 7.1-rc1 (2026-04-26 14:19:00 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git tags/wireless-next-2026-04-30
for you to fetch changes up to 7baf5857e15d722776898510a10546d6b2f18645:
wifi: brcmsmac: phy_lcn: Remove dead code in wlc_lcnphy_radio_2064_channel_tune_4313() (2026-04-28 10:43:27 +0200)
----------------------------------------------------------------
Some new content already, notably:
- mac80211: major rework of station bandwidth handling,
fixing issues with lower capability than AP
- general: cleanups for EMLSR spec issues (drafts differed)
- ath9k: GPIO interface improvements
- ath12k: replace dynamic memory allocation in WMI RX path
----------------------------------------------------------------
Aaradhana Sahu (1):
wifi: ath12k: Fix invalid IRQ requests during AHB probe
Chelsy Ratnawat (1):
wifi: brcmsmac: phy_lcn: Remove dead code in wlc_lcnphy_radio_2064_channel_tune_4313()
Daniel Gabay (1):
wifi: cfg80211: validate cipher suite for NAN Data keys
Dmitry Antipov (1):
wifi: mac80211: use kstrtobool_from_user() in debugfs callbacks
Jeff Johnson (3):
wifi: ath12k: Fix HTC prototype ath12k_base parameters
wifi: ath12k: Fix ath12k_dp_htt_tlv_iter()'s iter() signature
wifi: ath12k: Remove macro HAL_RX_EHT_SIG_OFDMA_EB2_MCS
Johannes Berg (24):
wifi: mac80211: remove NAN guards on ieee80211_sta_cur_vht_bw() calls
wifi: mac80211: set cur_max_bandwidth to maximum
wifi: mac80211: use max BW for HT channel width update
wifi: mac80211: use chandef in ieee80211_get_sta_bw()
wifi: mac80211: use chandef in TDLS chanctx handling
wifi: mac80211: remove ieee80211_sta_cap_chan_bw()
wifi: nl80211: document channel opmode change channel width
wifi: mac80211: simplify ieee80211_sta_rx_bw_to_chan_width()
wifi: mac80211: clean up STA NSS handling
wifi: mac80211: clean up initial STA NSS/bandwidth handling
wifi: mac80211: clean up ieee80211_sta_cap_rx_bw()
wifi: mac80211: remove ieee80211_sta_cur_vht_bw()
wifi: cfg80211: remove HE/SAE H2E required fields
wifi: nl80211: reject beacons with bad HE operation
wifi: cfg80211: move AP HT/VHT/... operation to beacon info
wifi: nl80211: reject too short HT/VHT/HE/EHT capability/operation
wifi: cfg80211: provide HT/VHT operation for AP beacon
wifi: nl80211: always validate AP operation/PHY regulatory
wifi: mac80211: clarify per-STA bandwidth handling
wifi: mac80211: fix per-station PHY capability bandwidth
wifi: mac80211: clarify an 802.11 VHT spec reference
wifi: nl80211: check link is beaconing for color change
wifi: mac80211: always allow transmitting null-data on TXQs
Merge tag 'ath-next-20260427' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath
Linus Walleij (1):
wifi: ath9k: Obtain system GPIOS from descriptors
Louis Kotze (1):
wifi: cfg80211: fix grammar in MLO group key error message
Nicolas Escande (1):
wifi: ath12k: avoid dynamic alloc when parsing wmi tb
Pablo Martin-Gomez (4):
wifi: Remove invalid 128TU transition timeout constant
wifi: Remove EMLMR Delay subfield definitions
wifi: Rename EMLSR delay constants and add EMLMR helpers and definitions
wifi: Update EML function documentation to remove EMLSR-specific references
Ping-Ke Shih (1):
wifi: mac80211: add __packed to union members of struct ieee80211_rx_status
Yuqi Xu (1):
wifi: cfg80211: reject duplicate wiphy cipher suite entries
drivers/gpio/gpio-ath79.c | 57 +++-
drivers/net/wireless/ath/ath12k/ahb.c | 25 +-
drivers/net/wireless/ath/ath12k/core.c | 6 +
drivers/net/wireless/ath/ath12k/dp_htt.c | 2 +-
drivers/net/wireless/ath/ath12k/dp_htt.h | 2 +-
drivers/net/wireless/ath/ath12k/htc.h | 8 +-
drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h | 1 -
drivers/net/wireless/ath/ath12k/wmi.c | 217 +++++--------
drivers/net/wireless/ath/ath12k/wmi.h | 3 +
drivers/net/wireless/ath/ath9k/hw.c | 33 +-
drivers/net/wireless/ath/ath9k/hw.h | 3 +-
.../broadcom/brcm80211/brcmsmac/phy/phy_lcn.c | 13 +-
drivers/net/wireless/intel/iwlwifi/mld/iface.c | 2 +-
drivers/net/wireless/intel/iwlwifi/mld/mac80211.c | 6 +-
drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c | 6 +-
drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 4 +-
drivers/net/wireless/quantenna/qtnfmac/commands.c | 4 +-
drivers/net/wireless/realtek/rtw89/fw.c | 2 +-
include/linux/ieee80211-eht.h | 115 +++++--
include/net/cfg80211.h | 25 +-
include/net/mac80211.h | 10 +-
include/uapi/linux/nl80211.h | 10 +-
net/mac80211/cfg.c | 136 +++++++-
net/mac80211/chan.c | 66 ++--
net/mac80211/debugfs.c | 47 +--
net/mac80211/eht.c | 11 +-
net/mac80211/he.c | 9 +-
net/mac80211/ht.c | 59 +---
net/mac80211/ibss.c | 3 +
net/mac80211/ieee80211_i.h | 28 +-
net/mac80211/mesh_plink.c | 3 +
net/mac80211/mlme.c | 25 +-
net/mac80211/ocb.c | 5 +-
net/mac80211/rate.c | 4 +-
net/mac80211/sta_info.c | 294 ++++++++++++++++-
net/mac80211/sta_info.h | 16 +-
net/mac80211/tdls.c | 24 +-
net/mac80211/tx.c | 2 +-
net/mac80211/util.c | 23 +-
net/mac80211/vht.c | 350 +--------------------
net/wireless/core.c | 21 ++
net/wireless/core.h | 3 +-
net/wireless/nl80211.c | 260 +++++++++------
net/wireless/util.c | 10 +
net/wireless/wext-compat.c | 3 +-
45 files changed, 1097 insertions(+), 859 deletions(-)
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
From: Vladimir Oltean @ 2026-04-30 12:03 UTC (permalink / raw)
To: Josua Mayer
Cc: Andrew Lunn, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Yazan Shhady, Mikhail Anikin,
Alexander Dahl, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, Conor Dooley,
Krzysztof Kozlowski, netdev@vger.kernel.org
In-Reply-To: <75e338eb-afd2-4e2e-9b93-e9fc36871854@solid-run.com>
On Thu, Apr 30, 2026 at 11:48:45AM +0000, Josua Mayer wrote:
> > Also, can you use udev for user
> > interface naming?
> Possibly .... I am aware of systemd (udev) based default behaviour
> for network interface aliases (eth0, eth1, ...).
>
> However I have not seen it for dsa switch ports.
In /etc/udev/rules.d/10-network.rules:
ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p0", NAME="lan0"
ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p1", NAME="lan1"
ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p2", NAME="lan2"
ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p3", NAME="lan3"
ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p4", NAME="lan4"
ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p5", NAME="lan5"
>
> It has been common practice for switch ports to be named lan[0-9]+,
> and I'd prefer to keep it that way here too.
> Predictable names are important for users in particular when interfaces
> are of different types and at different connectors.
>
> Re. the T1 ports names I didn't know whether to use "lan" or "trx".
> For those if "lan" is preferred, I can change them.
No objection to your naming choice. Just want to point out that we
encourage DSA users to use the same naming infrastructure as any other
net device. The device tree labels mostly come from deeply embedded
environments where a full udev implementation is missing (like OpenWrt).
If you don't have that excuse, you can try to leave the labels in the
device tree out and set up predictable names through an udev rule.
^ permalink raw reply
* Re: [PATCH v7 phy-next 17/27] phy: introduce phy_get_max_link_rate() helper for consumers
From: Geert Uytterhoeven @ 2026-04-30 11:59 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Markus Schneider-Pargmann, Andrzej Hajda,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Andy Yan, Marc Kleine-Budde, Vincent Mailhol,
Nicolas Ferre, Alexandre Belloni, Claudiu Beznea,
Geert Uytterhoeven, Magnus Damm
In-Reply-To: <20260430110652.558622-18-vladimir.oltean@nxp.com>
Hi Vladimir,
On Thu, 30 Apr 2026 at 13:07, Vladimir Oltean <vladimir.oltean@nxp.com> wrote:
> Consumer drivers shouldn't dereference struct phy, not even to get to
> its attributes.
>
> We have phy_get_bus_width() as a precedent for getting the bus_width
> attribute, so let's add phy_get_max_link_rate() and use it in DRM and
> CAN drivers.
>
> In CAN drivers, the transceiver is acquired through devm_phy_optional_get()
> and NULL is given by the API as a non-error case, so the PHY API should
> also tolerate NULL coming back to it. This means we can further simplify
> the call sites that test for the NULL quality of the transceiver.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Acked-by: Markus Schneider-Pargmann <msp@baylibre.com> # m_can
Thanks for your patch!
> drivers/net/can/rcar/rcar_canfd.c | 3 +--
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # rcar_canfd
> --- a/include/linux/phy/phy.h
> +++ b/include/linux/phy/phy.h
> @@ -57,6 +57,7 @@ int phy_notify_disconnect(struct phy *phy, int port);
> int phy_notify_state(struct phy *phy, union phy_notify state);
> int phy_get_bus_width(struct phy *phy);
> void phy_set_bus_width(struct phy *phy, int bus_width);
> +u32 phy_get_max_link_rate(struct phy *phy);
This (and all the existing getters) should take a "const struct phy *".
> #else
> static inline struct phy *phy_get(struct device *dev, const char *string)
> {
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
From: Josua Mayer @ 2026-04-30 12:14 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Andrew Lunn, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Yazan Shhady, Mikhail Anikin,
Alexander Dahl, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, Conor Dooley,
Krzysztof Kozlowski, netdev@vger.kernel.org
In-Reply-To: <20260430120341.4sqmblbt2hqoklsb@skbuf>
Am 30.04.26 um 14:03 schrieb Vladimir Oltean:
> On Thu, Apr 30, 2026 at 11:48:45AM +0000, Josua Mayer wrote:
>>> Also, can you use udev for user
>>> interface naming?
>> Possibly .... I am aware of systemd (udev) based default behaviour
>> for network interface aliases (eth0, eth1, ...).
>>
>> However I have not seen it for dsa switch ports.
> In /etc/udev/rules.d/10-network.rules:
>
> ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p0", NAME="lan0"
> ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p1", NAME="lan1"
> ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p2", NAME="lan2"
> ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p3", NAME="lan3"
> ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p4", NAME="lan4"
> ACTION=="add", SUBSYSTEM=="net", KERNELS=="spi2.0", DRIVERS=="sja1105", ATTR{phys_port_name}=="p5", NAME="lan5"
>
>> It has been common practice for switch ports to be named lan[0-9]+,
>> and I'd prefer to keep it that way here too.
>> Predictable names are important for users in particular when interfaces
>> are of different types and at different connectors.
>>
>> Re. the T1 ports names I didn't know whether to use "lan" or "trx".
>> For those if "lan" is preferred, I can change them.
> No objection to your naming choice. Just want to point out that we
> encourage DSA users to use the same naming infrastructure as any other
> net device.
Understood.
> The device tree labels mostly come from deeply embedded
> environments where a full udev implementation is missing (like OpenWrt).
> If you don't have that excuse, you can try to leave the labels in the
> device tree out and set up predictable names through an udev rule.
Today I would claim that even OpenWRT has sufficient mechanisms
for interface naming.
The board in question can run a full OS due to sufficient RAM storage.
So I will drop the labels as suggested, for v3.
Note there is one other board using this same ethernet switch, and it specifies all the labels:
arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: arm: fsl: Add SolidRun i.MX8DXL SoM and HummingBoard
From: Josua Mayer @ 2026-04-30 12:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni
Cc: Yazan Shhady, Mikhail Anikin, Alexander Dahl, devicetree,
linux-kernel, imx, linux-arm-kernel, Vladimir Oltean,
Conor Dooley, Krzysztof Kozlowski, netdev, Josua Mayer,
Krzysztof Kozlowski
In-Reply-To: <20260430-imx8dxl-sr-som-v3-0-ce2b86cf75bc@solid-run.com>
Add binding for the SolidRun i.MX8DXL based System on Module, and the
reference HummingBoard Telematics.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 0023cd1268075..17cd47e8efce8 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1394,6 +1394,13 @@ properties:
- fsl,imx8dxl-evk # i.MX8DXL EVK Board
- const: fsl,imx8dxl
+ - description: SolidRun i.MX8DXL SoM based boards
+ items:
+ - enum:
+ - solidrun,imx8dxl-hummingboard-telematics # SolidRun i.MX8DXL SoM EVK Board
+ - const: solidrun,imx8dxl-sr-som
+ - const: fsl,imx8dxl
+
- description: i.MX8QXP/i.MX8DX Boards with Toradex Colibri iMX8X Modules
items:
- enum:
--
2.51.0
^ permalink raw reply related
* [PATCH v3 2/2] arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
From: Josua Mayer @ 2026-04-30 12:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni
Cc: Yazan Shhady, Mikhail Anikin, Alexander Dahl, devicetree,
linux-kernel, imx, linux-arm-kernel, Vladimir Oltean,
Conor Dooley, Krzysztof Kozlowski, netdev, Josua Mayer
In-Reply-To: <20260430-imx8dxl-sr-som-v3-0-ce2b86cf75bc@solid-run.com>
Add support for the SolidRun i.MX8DXL System-on-Module (revision 2.1)
and its corresponding evaluation carrier board, the HummingBoard
Telematics (revision 2.0).
The SoM features:
- eMMC
- GNSS with 1PPS
- V2X DSRC Radio
- Secure Element for V2X Applications
- Inertial Sensor
- Pressure Sensor
- Compass
The HummingBoard Telematics carrier board features:
- Cellular Modem
- WiFi & Bluetooth
- RTC with backup battery
- CAN
- 100Base-TX Ethernet
- 100Base-T1 Ethernet
- Multi-interface I/O connector
- Multi-interface add-on board connector
The multi-interface I/O connector supplies power and provides basic I/O
(Console UART, 100Base-TX, 100Base-T1, CAN, and power-supply logic level
GPIOs). The SolidRun Evaluation Kit includes a suitable cable and
adapter board that breaks these out into RJ45, USB Type-A, microUSB
Console, and Terminal Block connectors.
The multi-interface add-on board connector provides additional
interfaces (4x 100Base-T1, 2x SGMII, USB 2.0 shared with the cellular
modem, CAN, MDIO, SPI, UART, PCIe, I2C, and GPIO). These add-on
interfaces are disabled by default in the base device tree and are
intended to be enabled and extended via device tree overlays.
Note that a few components physically present on the SoM were omitted
from this description due to a lack of upstream bindings and drivers:
- Pressure Sensor
- V2X DSRC Radio
- Secure Element
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../freescale/imx8dxl-hummingboard-telematics.dts | 523 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi | 458 ++++++++++++++++++
3 files changed, 983 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 711e36cc2c990..7db459f666610 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -111,6 +111,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
imx8dxl-evk-pcie-ep-dtbs += imx8dxl-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb
+DTC_FLAGS_imx8dxl-hummingboard-telematics := -@
+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-hummingboard-telematics.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdps-mb-smarc-2.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts b/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts
new file mode 100644
index 0000000000000..7e822cbd7a528
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts
@@ -0,0 +1,523 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "imx8dxl-sr-som.dtsi"
+
+/ {
+ compatible = "solidrun,imx8dxl-hummingboard-telematics",
+ "solidrun,imx8dxl-sr-som", "fsl,imx8dxl";
+ model = "SolidRun i.MX8DXL HummingBoard Telematics";
+
+ aliases {
+ /* override ethernet aliases from imx8dxl.dtsi */
+ ethernet0 = &eqos;
+ /delete-property/ ethernet1;
+ gpio8 = &tca6408_u2;
+ mmc2 = &usdhc3;
+ rtc0 = &carrier_rtc;
+ rtc1 = &rtc;
+ serial1 = &lpuart1;
+ };
+
+ v_1_1: regulator-1-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v1";
+ pinctrl-0 = <®ulator_1v1_pins>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ vin-supply = <&v_5_0>;
+ gpio = <&lsio_gpio4 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_5_0: regulator-5-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5v0";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ };
+
+ /* can transceiver builtin regulator (STBN1 pin) */
+ reg_flexcan1_stby: regulator-flexcan1-standby {
+ compatible = "regulator-fixed";
+ regulator-name = "flexcan1-standby";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ gpio = <&tca6408_u2 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ /* can transceiver builtin regulator (STBN2 pin) */
+ reg_flexcan2_stby: regulator-flexcan2-standby {
+ compatible = "regulator-fixed";
+ regulator-name = "flexcan2-standby";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ gpio = <&tca6408_u2 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ modem_vbat: regulator-modem-vbat {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ pinctrl-0 = <®ulator_modem_vbat_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <3600000>;
+ regulator-min-microvolt = <3600000>;
+ vin-supply = <&v_5_0>;
+ gpio = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vbus1: regulator-vbus-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus1";
+ pinctrl-0 = <®ulator_usb1_vbus_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpio = <&lsio_gpio0 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usdhc3_pwrseq: usdhc3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&dma_apbh {
+ status = "disabled";
+};
+
+&eqos {
+ /* delays are added by connected ethernet-switch cpu port */
+ phy-mode = "rgmii";
+ pinctrl-0 = <&eqos_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ fixed-link {
+ full-duplex;
+ speed = <1000>;
+ };
+};
+
+&flexcan1 {
+ pinctrl-0 = <&flexcan1_pins>;
+ pinctrl-names = "default";
+ xceiver-supply = <®_flexcan1_stby>;
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
+&flexcan2 {
+ pinctrl-0 = <&flexcan2_pins>;
+ pinctrl-names = "default";
+ xceiver-supply = <®_flexcan2_stby>;
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
+&i2c2 {
+ /* routed to J14: SDA(51), SCL(53) */
+
+ /* regulator@18 */
+
+ tca6408_u2: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names = "DIG_IN1", "DIG_IN2", "CAN_STNB1", "CAN_STNB2",
+ "DIG_OUT1", "DIG_OUT2", "", "";
+ interrupts-extended = <&lsio_gpio0 20 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&tca6408_u2_int_pins>;
+ pinctrl-names = "default";
+ };
+
+ carrier_rtc: rtc@32 {
+ compatible = "epson,rx8111";
+ reg = <0x32>;
+ };
+};
+
+&iomuxc {
+ bluetooth_pins: pinctrl-bluetooth-grp {
+ fsl,pins = <
+ /* BT_REG_ON: io without pull (module integrates pd) */
+ IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 0x0000061
+ >;
+ };
+
+ eqos_pins: pinctrl-eqos-grp {
+ fsl,pins = <
+ /* MDIO to Switch */
+ /* enet0 mdio pads supplied with 3.3v */
+ /* IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT */
+ IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
+ IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
+ /* RGMII to Switch */
+ IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
+ IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
+ IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
+ IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
+ >;
+ };
+
+ flexcan1_pins: pinctrl-flexcan1-grp {
+ fsl,pins = <
+ IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x00000021
+ IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x00000021
+ >;
+ };
+
+ flexcan2_pins: pinctrl-flexcan2-grp {
+ fsl,pins = <
+ IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x00000021
+ IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x00000021
+ >;
+ };
+
+ lpspi0_pins: pinctrl-lpspi0-grp {
+ fsl,pins = <
+ IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK 0x600004c
+ IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO 0x600004c
+ IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI 0x600004c
+ IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 0x0000021
+ IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 0x0000021
+ >;
+ };
+
+ lpuart1_pins: pinctrl-lpuart1-grp {
+ fsl,pins = <
+ IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
+ IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
+ IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
+ IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
+ >;
+ };
+
+ modem_pins: pinctrl-lte-grp {
+ fsl,pins = <
+ /* modem RESET_N: io open drain drive 2mA */
+ IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 0x2000061
+
+ /* modem PWRKEY: io open drain with pull-up, drive 2mA */
+ IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 0x2000021
+ >;
+ };
+
+ regulator_1v1_pins: pinctrl-regulator-1-1-grp {
+ fsl,pins = <
+ /* SW_PE: io without pull-up */
+ IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0000061
+ >;
+ };
+
+ regulator_modem_vbat_pins: pinctrl-regulator-modem-vbat-grp {
+ fsl,pins = <
+ /*
+ * RF_PWR: io without pull-up,
+ * has either external pull-up (R1117) or pull-down (R1118).
+ * With pull-up Modem will boot at system power-up,
+ * with pull-down modem will enter power-down mode once
+ * vbat is enabled -> toggle pwrkey to boot modem.
+ * Hence pull-up (R1117) is preferred.
+ */
+ IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 0x0000061
+ >;
+ };
+
+ regulator_usb1_vbus_pins: pinctrl-regulator-usb1-vbus-grp {
+ fsl,pins = <
+ /* regulator enable: open-drain with pull-up & low drive strength */
+ IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 0x2000021
+ >;
+ };
+
+ switch_pins: pinctrl-switch-grp {
+ fsl,pins = <
+ /* SW_RSTn: io without pull-up */
+ IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0000021
+
+ /* SW_CORE_RSTn: io without pull-up */
+ IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0000021
+
+ /* INT_N: io without pull-up */
+ IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0000021
+ >;
+ };
+
+ tca6408_u2_int_pins: pinctrl-tca6408-u2-int-grp {
+ fsl,pins = <
+ /* gpio-expander interrupt: io with pull-up */
+ IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 0x0000021
+ >;
+ };
+
+ usdhc3_pins: pinctrl-usdhc3-grp {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK 0x06000040
+ IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 0x00000021
+ >;
+ };
+
+ wifi_pins: pinctrl-wifi-grp {
+ fsl,pins = <
+ /* WL_REG_ON: io without pull (module integrates pd) */
+ IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 0x0000061
+ >;
+ };
+};
+
+&lpspi0 {
+ cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>, <&lsio_gpio1 7 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&lpspi0_pins>, <&switch_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ethernet-switch@0 {
+ compatible = "nxp,sja1110a";
+ reg = <0>;
+ reset-gpios = <&lsio_gpio4 3 GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <4000000>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 100Base-TX on connector J26 */
+ port@1 {
+ reg = <0x1>;
+ phy-handle = <&switch_port1_base_tx_phy>;
+ phy-mode = "internal";
+ };
+
+ /* CPU */
+ port@2 {
+ reg = <0x2>;
+ ethernet = <&eqos>;
+ phy-mode = "rgmii-id";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+
+ fixed-link {
+ full-duplex;
+ speed = <1000>;
+ };
+ };
+
+ /* sgmii on addon board connector J21 */
+ port@3 {
+ reg = <0x3>;
+ status = "disabled";
+ };
+
+ /* sgmii on addon board connector J21 */
+ port@4 {
+ reg = <0x4>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ port@5 {
+ reg = <0x5>;
+ phy-handle = <&switch_port5_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ port@6 {
+ reg = <0x6>;
+ phy-handle = <&switch_port6_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ port@7 {
+ reg = <0x7>;
+ phy-handle = <&switch_port7_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ port@8 {
+ reg = <0x8>;
+ phy-handle = <&switch_port8_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ port@9 {
+ reg = <0x9>;
+ phy-handle = <&switch_port9_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100Base-T1 on connector J26 */
+ port@a {
+ reg = <0xa>;
+ phy-handle = <&switch_port10_base_t1_phy>;
+ phy-mode = "internal";
+ };
+ };
+
+ mdios {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ compatible = "nxp,sja1110-base-t1-mdio";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port5_base_t1_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x1>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port6_base_t1_phy: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x2>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port7_base_t1_phy: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x3>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port8_base_t1_phy: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x4>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port9_base_t1_phy: ethernet-phy@5 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x5>;
+ status = "disabled";
+ };
+
+ /* 100Base-T1 on connector J26 */
+ switch_port10_base_t1_phy: ethernet-phy@6 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x6>;
+ };
+ };
+
+ mdio@1 {
+ compatible = "nxp,sja1110-base-tx-mdio";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 100Base-TX on connector J26 */
+ switch_port1_base_tx_phy: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+ };
+ };
+};
+
+/* bluetooth */
+&lpuart1 {
+ pinctrl-0 = <&lpuart1_pins>, <&bluetooth_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ /* Murata 1MW module supports max. 3M baud */
+ max-speed = <3000000>;
+ shutdown-gpios = <&lsio_gpio0 13 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&usbotg1 {
+ vbus-supply = <&vbus1>;
+};
+
+/* cellular modem */
+&usbotg2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adp-disable;
+ disable-over-current;
+ dr_mode = "host";
+ hnp-disable;
+ pinctrl-0 = <&modem_pins>;
+ pinctrl-names = "default";
+ power-active-high;
+ srp-disable;
+ vbus-supply = <&v_5_0>;
+ status = "okay";
+
+ usb-device@1 {
+ compatible = "usb2c7c,125";
+ reg = <1>;
+ reset-duration-us = <150000>;
+ reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
+ vbus-supply = <&v_3_3>;
+ vdd-supply = <&modem_vbat>;
+ };
+};
+
+&usbphy2 {
+ status = "okay";
+};
+
+/* WiFi */
+&usdhc3 {
+ bus-width = <4>;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ non-removable;
+ no-sd;
+ pinctrl-0 = <&usdhc3_pins>, <&wifi_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <&v_3_3>;
+ vqmmc-supply = <&v_1_8>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi
new file mode 100644
index 0000000000000..93a0eb4d7f770
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Josua Mayer <josua@solid-run.com>
+ */
+
+#include "imx8dxl.dtsi"
+/ {
+ compatible = "solidrun,imx8dxl-sr-som", "fsl,imx8dxl";
+ model = "SolidRun i.MX8DXL SoM";
+
+ aliases {
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &lpuart0;
+ serial2 = &lpuart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ imx8dxl-cm4 {
+ compatible = "fsl,imx8qxp-cm4";
+ clocks = <&clk_dummy>;
+ mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>;
+ mbox-names = "tx", "rx", "rxdb";
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
+ fsl,entry-address = <0x34fe0000>;
+ fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ gpios = <&lsio_gpio2 6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&gnss_pps_pins>;
+ pinctrl-names = "default";
+ };
+
+ v_1_2: regulator-1-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v2";
+ pinctrl-0 = <®ulator_1_2_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_1_6: regulator-1-6 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v6";
+ pinctrl-0 = <®ulator_1_6_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <1600000>;
+ regulator-min-microvolt = <1600000>;
+ vin-supply = <&v_1_8>;
+ gpio = <&lsio_gpio1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_1_8: regulator-1-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ };
+
+ v_1_8_se: regulator-1-8-secure-element {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8-se";
+ pinctrl-0 = <®ulator_1_8_se_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ vin-supply = <&v_1_8>;
+ gpio = <&lsio_gpio3 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_3_3: regulator-3-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x98000000 0 0x14000000>;
+ reusable;
+ size = <0 0x14000000>;
+ linux,cma-default;
+ };
+
+ vdev0vring0: memory0@90000000 {
+ reg = <0 0x90000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: memory@90008000 {
+ reg = <0 0x90008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: memory@90010000 {
+ reg = <0 0x90010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: memory@90018000 {
+ reg = <0 0x90018000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table: memory-rsc-table@900ff000 {
+ reg = <0 0x900ff000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: memory-vdevbuffer@90400000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x90400000 0 0x100000>;
+ no-map;
+ };
+
+ /*
+ * Memory reserved for optee usage. Please do not use.
+ * This will be automatically added to dtb if OP-TEE is installed.
+ * optee@96000000 {
+ * reg = <0 0x96000000 0 0x2000000>;
+ * no-map;
+ * };
+ */
+ };
+
+ memory@80000000 {
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ device_type = "memory";
+ };
+};
+
+&i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&i2c2_gpio_pins>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&lsio_gpio3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&lsio_gpio3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-1 = <&i2c3_gpio_pins>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&lsio_gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&lsio_gpio3 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ magnetometer@1e {
+ compatible = "st,iis2mdc";
+ reg = <0x1e>;
+ interrupt-parent = <&lsio_gpio2>;
+ interrupts = <10 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-0 = <&magnetometer_pins>;
+ pinctrl-names = "default";
+ st,drdy-int-pin = <1>;
+ };
+
+ /* pressure-sensor@5c */
+
+ inertial-sensor@6b {
+ compatible = "st,ism330dhcx";
+ reg = <0x6b>;
+ interrupt-parent = <&lsio_gpio2>;
+ interrupts = <11 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-0 = <&imu_pins>;
+ pinctrl-names = "default";
+ st,drdy-int-pin = <1>;
+ };
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_hog>;
+ pinctrl-names = "default";
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
+ >;
+ };
+
+ dsrc_pins: pinctrl-dsrc-grp {
+ fsl,pins = <
+ /* reset: io without pull */
+ IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 0x0000060
+
+ /*
+ * boot0: io without pull
+ * After reset, this pin selects radio boot media:
+ * - 0: flash spi
+ * - 1: slave sdio
+ * Once the firmware boots however, the radio controls
+ * this pin for flow-control to signal readiness.
+ */
+ IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 0x0000060
+ >;
+ };
+
+ gnss_pins: pinctrl-gnss-grp {
+ fsl,pins = <
+ /* gps reset: input with pull-up */
+ IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN 0x0000021
+ /* gps interrupt: io without pull-up */
+ IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN 0x0000061
+ >;
+ };
+
+ gnss_pps_pins: pinctrl-gnss-pps-grp {
+ fsl,pins = <
+ /* gps timepulse: input without pull-up */
+ IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN 0x0000061
+ >;
+ };
+
+ i2c2_gpio_pins: pinctrl-i2c2-gpio-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 0x00000021
+ /* io with pull-up, weak drive, open-drain */
+ IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 0x02000021
+ >;
+ };
+
+ i2c2_pins: pinctrl-i2c2-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
+ IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
+ >;
+ };
+
+ i2c3_gpio_pins: pinctrl-i2c3-gpio-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 0x00000021
+ /* io with pull-up, weak drive, open-drain */
+ IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 0x02000021
+ >;
+ };
+
+ i2c3_pins: pinctrl-i2c3-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
+ IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
+ >;
+ };
+
+ imu_pins: pinctrl-imu-grp {
+ fsl,pins = <
+ /* interrupt: io with pull-down */
+ IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN 0x0000041
+ >;
+ };
+
+ lpspi2_pins: pinctrl-lpspi2-grp {
+ fsl,pins = <
+ IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK 0x600004c
+ IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO 0x600004c
+ IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI 0x600004c
+ IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 0x6000021
+ >;
+ };
+
+ lpuart0_pins: pinctrl-lpuart0-grp {
+ fsl,pins = <
+ IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
+ IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+
+ lpuart2_pins: pinctrl-lpuart2-grp {
+ fsl,pins = <
+ IMX8DXL_UART2_TX_ADMA_UART2_TX 0x06000020
+ IMX8DXL_UART2_RX_ADMA_UART2_RX 0x06000020
+ >;
+ };
+
+ magnetometer_pins: pinctrl-magnetometer-grp {
+ fsl,pins = <
+ /* interrupt: io with pull-down */
+ IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN 0x0000041
+ >;
+ };
+
+ regulator_1_2_pins: pinctrl-regulator-1-2-grp {
+ fsl,pins = <
+ /* io without pull-up */
+ /* has etxernal pull-down */
+ IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 0x0000061
+ >;
+ };
+
+ regulator_1_6_pins: pinctrl-regulator-1-6-grp {
+ fsl,pins = <
+ /* io without pull-up */
+ /* has etxernal pull-down */
+ IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 0x0000061
+ >;
+ };
+
+ regulator_1_8_se_pins: pinctrl-regulator-1-8-secure-element-grp {
+ fsl,pins = <
+ /* v2x-secure-element power switch: io with pull-down */
+ IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x0000041
+ >;
+ };
+
+ se_pins: pinctrl-secure-element-grp {
+ fsl,pins = <
+ /* v2x-secure-element reset: io with pull-up */
+ IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x0000021
+
+ /*
+ * v2x-secure-element gpio0: io with pull-up
+ * pulled low by sxf after boot indicating ready for commands
+ */
+ IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x0000021
+
+ /* v2x-secure-element gpio1: io with pull-up */
+ IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x0000021
+ >;
+ };
+
+ usdhc1_pins: pinctrl-usdhc1-grp {
+ fsl,pins = <
+ IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000061
+ >;
+ };
+
+ usdhc2_pins: pinctrl-usdhc2-grp {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000040
+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
+ >;
+ };
+};
+
+&lpspi2 {
+ cs-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
+ num-cs = <1>;
+ pinctrl-0 = <&lpspi2_pins>, <&se_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* console */
+&lpuart0 {
+ pinctrl-0 = <&lpuart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* gnss */
+&lpuart2 {
+ pinctrl-0 = <&lpuart2_pins>, <&gnss_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&lsio_gpio3 {
+ gpio-line-names = "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "SXF_RST", "SXF_GPIO0", "SXF_GPIO1", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&lsio_mu5 {
+ status = "okay";
+};
+
+/* OTG port for boot */
+&usbotg1 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "peripheral";
+ hnp-disable;
+ power-active-high;
+ srp-disable;
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc1 {
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ non-removable;
+ no-sd;
+ no-sdio;
+ pinctrl-0 = <&usdhc1_pins>;
+ pinctrl-1 = <&usdhc1_pins>;
+ pinctrl-2 = <&usdhc1_pins>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ vmmc-supply = <&v_3_3>;
+ vqmmc-supply = <&v_1_8>;
+ status = "okay";
+};
+
+/* DSRC Radio */
+&usdhc2 {
+ bus-width = <4>;
+ keep-power-in-suspend;
+ max-frequency = <40000000>;
+ non-removable;
+ no-sd;
+ pinctrl-0 = <&usdhc2_pins>, <&dsrc_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <&v_3_3>;
+ vqmmc-supply = <&v_1_8>;
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related
* [PATCH v3 0/2] arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
From: Josua Mayer @ 2026-04-30 12:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni
Cc: Yazan Shhady, Mikhail Anikin, Alexander Dahl, devicetree,
linux-kernel, imx, linux-arm-kernel, Vladimir Oltean,
Conor Dooley, Krzysztof Kozlowski, netdev, Josua Mayer,
Krzysztof Kozlowski
Add bindings and description for SolidRUn i.MX8DXL based SoM and
HummingBoard Telematics.
Modify SJA1110 Ethernet Switch bindings to allow SPI Mode 0.
This patch-set is based on v7.0-rc2, because rc1 was experiencing
deadlocks with imx8qxp clock driver.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Changes in v3:
- rebased on v7.1-rc1.
- dropped dsa swtch port labels, should be handled by udev rules if
required.
- Fixed spelling error in alias comment.
- Dropped superfluous status okay properties from switch sub-nodes.
- Link to v2: https://lore.kernel.org/r/20260409-imx8dxl-sr-som-v2-0-83ff20629ba0@solid-run.com
Changes in v2:
- Dropped accidental change to unrelated imx8mp-sr-som.dtsi file.
- Fixed phy-mode on fixed link between cpu and ethernet switch.
(Reported-by: Andrew Lunn <andrew@lunn.ch>)
- Removed spi-cpol property from ethernet-switch on spi bus, fixing
sja1110a driver probe.
- Changed SJA1110 bindings to allow removing spi-cpol property.
- Aligned comments on all ethernet switch port nodes to be consistent.
- Dropped regulator-always-on from dsrc radio power-supplies.
- Link to v1: https://lore.kernel.org/r/20260408-imx8dxl-sr-som-v1-0-ce5a39acd713@solid-run.com
---
Josua Mayer (2):
dt-bindings: arm: fsl: Add SolidRun i.MX8DXL SoM and HummingBoard
arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
Documentation/devicetree/bindings/arm/fsl.yaml | 7 +
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../freescale/imx8dxl-hummingboard-telematics.dts | 523 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi | 458 ++++++++++++++++++
4 files changed, 990 insertions(+)
---
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
change-id: 20260408-imx8dxl-sr-som-f141ec343173
Best regards,
--
Josua Mayer <josua@solid-run.com>
^ permalink raw reply
* Re: [PATCH net v2] net: airoha: Move entries to queue head in case of DMA mapping failure in airoha_dev_xmit()
From: Lorenzo Bianconi @ 2026-04-30 12:23 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Jacob Keller
Cc: Simon Horman, linux-arm-kernel, linux-mediatek, netdev
In-Reply-To: <20260429-airoha-xmit-unmap-error-path-v2-1-32e43b7c6d25@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 2338 bytes --]
> In order to respect the original descriptor order and avoid any
> potential IOMMU fault or memory corruption, move pending queue entries
> to the head of hw queue tx_list if the DMA mapping of current inflight
> packet fails in airoha_dev_xmit routine.
>
> Fixes: 3f47e67dff1f7 ("net: airoha: Add the capability to consume out-of-order DMA tx descriptors")
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
> Changes in v2:
> - Remove leftover airoha_queue_entry initialization inside the loop from
> the previous version.
> - Link to v1: https://lore.kernel.org/r/20260428-airoha-xmit-unmap-error-path-v1-1-aec44c6765c1@kernel.org
> ---
> drivers/net/ethernet/airoha/airoha_eth.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 5effb4a4ae84..fb4f51d67dd7 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -2123,14 +2123,12 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
> return NETDEV_TX_OK;
>
> error_unmap:
> - while (!list_empty(&tx_list)) {
> - e = list_first_entry(&tx_list, struct airoha_queue_entry,
> - list);
> + list_for_each_entry(e, &tx_list, list) {
> dma_unmap_single(dev->dev.parent, e->dma_addr, e->dma_len,
> DMA_TO_DEVICE);
> e->dma_addr = 0;
> - list_move_tail(&e->list, &q->tx_list);
> }
> + list_splice(&tx_list, &q->tx_list);
>
> spin_unlock_bh(&q->lock);
> error:
commenting on Sashiko's reported issues:
https://sashiko.dev/#/patchset/20260429-airoha-xmit-unmap-error-path-v2-1-32e43b7c6d25%40kernel.org
- Should the driver be updated to use skb_frag_dma_map() for mapping the SKB
fragments, and correspondingly use dma_unmap_page() for those fragments in
this error handling path?
As we already pointed out here [0], we decided to skip this request and keep
using dma_map_single() even for skb fragments.
Regards,
Lorenzo
[0] https://lore.kernel.org/netdev/20260427173935.6a1e36ee@kernel.org/
>
> ---
> base-commit: 0c7a5ba011d336df4fcd1f667fcc16ea5549be12
> change-id: 20260428-airoha-xmit-unmap-error-path-8125594efb23
>
> Best regards,
> --
> Lorenzo Bianconi <lorenzo@kernel.org>
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* [PATCH 0/5] ice: five small fixes and cleanups
From: Aleksandr Loktionov @ 2026-04-30 12:25 UTC (permalink / raw)
To: intel-wired-lan, anthony.l.nguyen, aleksandr.loktionov; +Cc: netdev
Three correctness fixes and two cleanups for the ice driver.
Patch 1 corrects a kernel-doc comment in ice_ptp_hw.h that described the
ETH56G MAC Rx offset field as unsigned when it is signed (trivial doc fix,
no functional change).
Patch 2 removes the PF_SB_REM_DEV_CTL sideband register write from
ice_ptp_init_phc_e82x(). PHY access is enabled by default on E82X and
the register write was a leftover from an earlier SWITCH_MODE workaround
that is no longer needed.
Patch 3 renames ICE_SMA2_UFL2_RX_DIS to ICE_SMA2_UFL2_RX_EN to match
the actual active-high hardware semantics and inverts the three use sites
in ice_dpll.c so that the logic remains correct.
Patch 4 replaces the static per-type frequency tables for CGU pins with a
single DPLL_PIN_FREQUENCY_RANGE(1, 25 MHz) entry. The firmware defines
an any_freq capability for configurable CGU inputs, but the old tables
restricted users to 1 PPS or 10 MHz. GNSS pins retain a 1 PPS-only
entry since they are physically constrained.
Patch 5 exports ice_dcb_need_recfg() and calls it in the four SW LLDP
netlink setters instead of memcmp() on a non-packed struct, which is
undefined behaviour due to uninitialised padding bytes. The redundant
memcmp in ice_pf_dcb_cfg() is removed since callers now guard it.
Aleksandr Loktionov (2):
ice: add correct handling of SMA/u.FL states
ice: use element-by-element comparison for DCB config changes
Arkadiusz Kubalewski (1):
ice: fix DPLL pin frequency range in CGU pin descriptors
Karol Kolacinski (2):
ice: fix ETH56G Rx offset type description in kernel-doc comment
ice: remove unnecessary PF_SB_REM_DEV_CTL write for E82X
drivers/net/ethernet/intel/ice/ice_dcb_lib.c | 13 +-
drivers/net/ethernet/intel/ice/ice_dcb_lib.h | 2 +
drivers/net/ethernet/intel/ice/ice_dcb_nl.c | 30 +++-
drivers/net/ethernet/intel/ice/ice_dpll.c | 6 +-
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 141 ++++++++++---------
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 8 +-
6 files changed, 113 insertions(+), 87 deletions(-)
--
2.52.0
^ permalink raw reply
* [PATCH 1/5] ice: fix ETH56G Rx offset type description in kernel-doc comment
From: Aleksandr Loktionov @ 2026-04-30 12:25 UTC (permalink / raw)
To: intel-wired-lan, anthony.l.nguyen, aleksandr.loktionov; +Cc: netdev
In-Reply-To: <20260430122602.126722-1-aleksandr.loktionov@intel.com>
From: Karol Kolacinski <karol.kolacinski@intel.com>
The ETH56G MAC register configuration Rx offset field stores a signed
integer, not an unsigned one. Correct the struct comment that incorrectly
described it as '11 bit unsigned int'. Also update 'unsigned ints' to
'unsigned integers' for consistency.
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
index 9bfd3e7..c1aa408 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
@@ -144,9 +144,9 @@ struct ice_vernier_info_e82x {
* @tx_offset: total Tx offset, fixed point
* @rx_offset: total Rx offset, contains value for bitslip/deskew, fixed point
*
- * All fixed point registers except Rx offset are 23 bit unsigned ints with
+ * All fixed point registers except Rx offset are 23 bit unsigned integers with
* a 9 bit fractional.
- * Rx offset is 11 bit unsigned int with a 9 bit fractional.
+ * Rx offset is 11 bit signed integer with a 9 bit fractional.
*/
struct ice_eth56g_mac_reg_cfg {
struct {
--
2.52.0
^ permalink raw reply related
* [PATCH 2/5] ice: remove unnecessary PF_SB_REM_DEV_CTL write for E82X
From: Aleksandr Loktionov @ 2026-04-30 12:25 UTC (permalink / raw)
To: intel-wired-lan, anthony.l.nguyen, aleksandr.loktionov; +Cc: netdev
In-Reply-To: <20260430122602.126722-1-aleksandr.loktionov@intel.com>
From: Karol Kolacinski <karol.kolacinski@intel.com>
Remove the PF_SB_REM_DEV_CTL register write from ice_ptp_init_phc_e82x().
PHY access is enabled by default on E82X devices and the driver does not
need to configure switch device access. The register write was a
remnant of an earlier SWITCH_MODE workaround for a FIFO issue and is
no longer needed.
Also update the kernel-doc comment to refer to the E82X family rather than
E822.
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 61c0a0d..7b1b402 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -2767,22 +2767,13 @@ static int ice_ptp_set_vernier_wl(struct ice_hw *hw)
}
/**
- * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization
+ * ice_ptp_init_phc_e82x - Perform E82X specific PHC initialization
* @hw: pointer to HW struct
*
- * Perform PHC initialization steps specific to E822 devices.
+ * Perform PHC initialization steps specific to E82X devices.
*/
static int ice_ptp_init_phc_e82x(struct ice_hw *hw)
{
- u32 val;
-
- /* Enable reading switch and PHY registers over the sideband queue */
-#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
-#define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
- val = rd32(hw, PF_SB_REM_DEV_CTL);
- val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0);
- wr32(hw, PF_SB_REM_DEV_CTL, val);
-
/* Set window length for all the ports */
return ice_ptp_set_vernier_wl(hw);
}
--
2.52.0
^ permalink raw reply related
* [PATCH 3/5] ice: add correct handling of SMA/u.FL states
From: Aleksandr Loktionov @ 2026-04-30 12:26 UTC (permalink / raw)
To: intel-wired-lan, anthony.l.nguyen, aleksandr.loktionov; +Cc: netdev
In-Reply-To: <20260430122602.126722-1-aleksandr.loktionov@intel.com>
The ICE_SMA2_UFL2_RX_DIS bit name is wrong: the bit is active high
(setting it *enables* RX for u.FL2 / SMA2), not active low. Rename
it to ICE_SMA2_UFL2_RX_EN and invert the use sites in ice_dpll.c so
that enabling the u.FL2 pin clears the bit (as it used to do) and
disabling sets it.
Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
---
drivers/net/ethernet/intel/ice/ice_dpll.c | 6 +++---
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
index 62f75701d..7e8bb63 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
@@ -672,7 +672,7 @@ ice_dpll_sw_pins_update(struct ice_pf *pf)
p->active = false;
p = &d->ufl[ICE_DPLL_PIN_SW_2_IDX];
- p->active = (data & ICE_SMA2_DIR_EN) && !(data & ICE_SMA2_UFL2_RX_DIS);
+ p->active = (data & ICE_SMA2_DIR_EN) && !(data & ICE_SMA2_UFL2_RX_EN);
d->sma_data = data;
return 0;
@@ -1264,10 +1264,10 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv,
case ICE_DPLL_PIN_SW_2_IDX:
if (state == DPLL_PIN_STATE_SELECTABLE) {
data |= ICE_SMA2_DIR_EN;
- data &= ~ICE_SMA2_UFL2_RX_DIS;
+ data &= ~ICE_SMA2_UFL2_RX_EN;
enable = true;
} else if (state == DPLL_PIN_STATE_DISCONNECTED) {
- data |= ICE_SMA2_UFL2_RX_DIS;
+ data |= ICE_SMA2_UFL2_RX_EN;
enable = false;
} else {
goto unlock;
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
index c1aa408..278d757 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
@@ -655,12 +655,12 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw)
/* SMA controller pin control */
#define ICE_SMA1_DIR_EN BIT(4)
#define ICE_SMA1_TX_EN BIT(5)
-#define ICE_SMA2_UFL2_RX_DIS BIT(3)
+#define ICE_SMA2_UFL2_RX_EN BIT(3)
#define ICE_SMA2_DIR_EN BIT(6)
#define ICE_SMA2_TX_EN BIT(7)
#define ICE_SMA1_MASK (ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN)
-#define ICE_SMA2_MASK (ICE_SMA2_UFL2_RX_DIS | ICE_SMA2_DIR_EN | \
+#define ICE_SMA2_MASK (ICE_SMA2_UFL2_RX_EN | ICE_SMA2_DIR_EN | \
ICE_SMA2_TX_EN)
#define ICE_SMA2_INACTIVE_MASK (ICE_SMA2_DIR_EN | ICE_SMA2_TX_EN)
#define ICE_ALL_SMA_MASK (ICE_SMA1_MASK | ICE_SMA2_MASK)
--
2.52.0
^ permalink raw reply related
* [PATCH 4/5] ice: fix DPLL pin frequency range in CGU pin descriptors
From: Aleksandr Loktionov @ 2026-04-30 12:26 UTC (permalink / raw)
To: intel-wired-lan, anthony.l.nguyen, aleksandr.loktionov
Cc: netdev, Arkadiusz Kubalewski
In-Reply-To: <20260430122602.126722-1-aleksandr.loktionov@intel.com>
From: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Replace the per-type frequency tables (ice_cgu_pin_freq_1_hz and
ice_cgu_pin_freq_10_mhz) and the two-entry ice_cgu_pin_freq_common array
with a named range constant ICE_CGU_MAX_FREQ_HZ (25 MHz), a new
ice_cgu_pin_freq_range array containing DPLL_PIN_FREQUENCY_RANGE(1,
ICE_CGU_MAX_FREQ_HZ), and a separate ice_cgu_pin_freq_gnss array that
retains DPLL_PIN_FREQUENCY_1PPS for GNSS input pins.
The hardware firmware spec defines an any_freq capability for CGU inputs
(ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ), but the static pin descriptor
tables constrained configurable pins to 1PPS or 10MHz, preventing users
from setting valid intermediate frequencies. Use a range entry so the
DPLL netlink interface correctly reflects what the firmware will accept.
The firmware validates the actual value and rejects out-of-range requests.
MUX, SyncE ETH port, and configurable EXT pins now advertise the full
frequency range, matching the hardware capability. GNSS input pins retain
the 1PPS-only advertisement since a GNSS receiver is physically
constrained to 1 Hz.
Fixes: 6db5f2cd9ebb ("ice: dpll: fix output pin capabilities")
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 128 +++++++++++---------
1 file changed, 72 insertions(+), 56 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 7b1b402..3949138 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -7,127 +7,143 @@
#include "ice_ptp_hw.h"
#include "ice_ptp_consts.h"
-static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = {
- DPLL_PIN_FREQUENCY_1PPS,
- DPLL_PIN_FREQUENCY_10MHZ,
-};
+/* Maximum frequency supported by CGU pins, in Hz */
+#define ICE_CGU_MAX_FREQ_HZ 25000000
-static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = {
- DPLL_PIN_FREQUENCY_1PPS,
+static struct dpll_pin_frequency ice_cgu_pin_freq_range[] = {
+ DPLL_PIN_FREQUENCY_RANGE(1, ICE_CGU_MAX_FREQ_HZ),
};
-static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = {
- DPLL_PIN_FREQUENCY_10MHZ,
+static struct dpll_pin_frequency ice_cgu_pin_freq_gnss[] = {
+ DPLL_PIN_FREQUENCY_1PPS,
};
static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = {
{ "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
- { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
- { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
- ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+ ARRAY_SIZE(ice_cgu_pin_freq_gnss), ice_cgu_pin_freq_gnss },
};
static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = {
{ "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
- { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
- { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
- { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, },
- { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
- ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+ ARRAY_SIZE(ice_cgu_pin_freq_gnss), ice_cgu_pin_freq_gnss },
};
static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = {
{ "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
- { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
- { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
};
static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = {
{ "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
- { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
- { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
- { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
};
static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = {
{ "NONE", SI_REF0P, 0, 0 },
{ "NONE", SI_REF0N, 0, 0 },
- { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 },
- { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 },
+ { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "NONE", SI_REF2N, 0, 0 },
{ "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
};
static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = {
{ "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
- { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
};
static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = {
{ "NONE", ZL_REF0P, 0, 0 },
{ "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
- { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 },
- { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "NONE", ZL_REF2P, 0, 0 },
{ "NONE", ZL_REF2N, 0, 0 },
{ "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "NONE", ZL_REF3N, 0, 0 },
{ "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 },
};
static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = {
{ "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
- { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
- { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
+ { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT,
- ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
+ ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },
{ "NONE", ZL_OUT5, 0, 0 },
};
--
2.52.0
^ permalink raw reply related
* [PATCH 5/5] ice: use element-by-element comparison for DCB config changes
From: Aleksandr Loktionov @ 2026-04-30 12:26 UTC (permalink / raw)
To: intel-wired-lan, anthony.l.nguyen, aleksandr.loktionov; +Cc: netdev
In-Reply-To: <20260430122602.126722-1-aleksandr.loktionov@intel.com>
Comparing two ice_dcbx_cfg structs with memcmp() is unreliable on
non-packed structs due to uninitialised padding bytes. The HW DCB
path already has ice_dcb_need_recfg() that compares fields
individually; export it and use it in the SW DCB netlink setters
(setets, setpfc, setapp, cee_set_all) instead of the unsafe memcmp.
Remove the now-redundant memcmp check from ice_pf_dcb_cfg() so that
function always attempts the HW reconfiguration when called.
Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
---
drivers/net/ethernet/intel/ice/ice_dcb_lib.c | 13 ++-------
drivers/net/ethernet/intel/ice/ice_dcb_lib.h | 2 ++
drivers/net/ethernet/intel/ice/ice_dcb_nl.c | 30 ++++++++++++++++++--
3 files changed, 32 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_dcb_lib.c b/drivers/net/ethernet/intel/ice/ice_dcb_lib.c
index bd77f1c..2e85fae 100644
--- a/drivers/net/ethernet/intel/ice/ice_dcb_lib.c
+++ b/drivers/net/ethernet/intel/ice/ice_dcb_lib.c
@@ -353,15 +353,11 @@ int ice_pf_dcb_cfg(struct ice_pf *pf, struct ice_dcbx_cfg *new_cfg, bool locked)
struct ice_dcbx_cfg *old_cfg, *curr_cfg;
struct device *dev = ice_pf_to_dev(pf);
struct iidc_rdma_event *event;
- int ret = ICE_DCB_NO_HW_CHG;
struct ice_vsi *pf_vsi;
+ int ret;
curr_cfg = &pf->hw.port_info->qos_cfg.local_dcbx_cfg;
- /* FW does not care if change happened */
- if (!pf->hw.port_info->qos_cfg.is_sw_lldp)
- ret = ICE_DCB_HW_CHG_RST;
-
/* Enable DCB tagging only when more than one TC */
if (ice_dcb_get_num_tc(new_cfg) > 1) {
dev_dbg(dev, "DCB tagging enabled (num TC > 1)\n");
@@ -377,11 +373,6 @@ int ice_pf_dcb_cfg(struct ice_pf *pf, struct ice_dcbx_cfg *new_cfg, bool locked)
clear_bit(ICE_FLAG_DCB_ENA, pf->flags);
}
- if (!memcmp(new_cfg, curr_cfg, sizeof(*new_cfg))) {
- dev_dbg(dev, "No change in DCB config required\n");
- return ret;
- }
-
if (ice_dcb_bwchk(pf, new_cfg))
return -EINVAL;
@@ -481,7 +472,7 @@ static void ice_cfg_etsrec_defaults(struct ice_port_info *pi)
* @old_cfg: current DCB config
* @new_cfg: new DCB config
*/
-static bool
+bool
ice_dcb_need_recfg(struct ice_pf *pf, struct ice_dcbx_cfg *old_cfg,
struct ice_dcbx_cfg *new_cfg)
{
diff --git a/drivers/net/ethernet/intel/ice/ice_dcb_lib.h b/drivers/net/ethernet/intel/ice/ice_dcb_lib.h
index da9ba81..a7eaa2f9 100644
--- a/drivers/net/ethernet/intel/ice/ice_dcb_lib.h
+++ b/drivers/net/ethernet/intel/ice/ice_dcb_lib.h
@@ -20,6 +20,8 @@ u8 ice_dcb_get_num_tc(struct ice_dcbx_cfg *dcbcfg);
void ice_vsi_set_dcb_tc_cfg(struct ice_vsi *vsi);
bool ice_is_pfc_causing_hung_q(struct ice_pf *pf, unsigned int txqueue);
u8 ice_dcb_get_tc(struct ice_vsi *vsi, int queue_index);
+bool ice_dcb_need_recfg(struct ice_pf *pf, struct ice_dcbx_cfg *old_cfg,
+ struct ice_dcbx_cfg *new_cfg);
int
ice_pf_dcb_cfg(struct ice_pf *pf, struct ice_dcbx_cfg *new_cfg, bool locked);
int ice_dcb_bwchk(struct ice_pf *pf, struct ice_dcbx_cfg *dcbcfg);
diff --git a/drivers/net/ethernet/intel/ice/ice_dcb_nl.c b/drivers/net/ethernet/intel/ice/ice_dcb_nl.c
index a10c1c8d..13a52c1 100644
--- a/drivers/net/ethernet/intel/ice/ice_dcb_nl.c
+++ b/drivers/net/ethernet/intel/ice/ice_dcb_nl.c
@@ -108,11 +108,17 @@ static int ice_dcbnl_setets(struct net_device *netdev, struct ieee_ets *ets)
if (!bwrec)
new_cfg->etsrec.tcbwtable[0] = 100;
+ if (!ice_dcb_need_recfg(pf, &pf->hw.port_info->qos_cfg.local_dcbx_cfg,
+ new_cfg)) {
+ err = ICE_DCB_NO_HW_CHG;
+ goto ets_out;
+ }
+
err = ice_pf_dcb_cfg(pf, new_cfg, true);
/* return of zero indicates new cfg applied */
- if (err == ICE_DCB_HW_CHG_RST)
+ if (!err)
ice_dcbnl_devreset(netdev);
- if (err == ICE_DCB_NO_HW_CHG)
+ else if (err == ICE_DCB_NO_HW_CHG)
err = ICE_DCB_HW_CHG_RST;
ets_out:
@@ -287,11 +293,18 @@ static int ice_dcbnl_setpfc(struct net_device *netdev, struct ieee_pfc *pfc)
new_cfg->pfc.pfcena = pfc->pfc_en;
+ if (!ice_dcb_need_recfg(pf, &pf->hw.port_info->qos_cfg.local_dcbx_cfg,
+ new_cfg)) {
+ err = ICE_DCB_NO_HW_CHG;
+ goto pfc_out;
+ }
+
err = ice_pf_dcb_cfg(pf, new_cfg, true);
if (err == ICE_DCB_HW_CHG_RST)
ice_dcbnl_devreset(netdev);
if (err == ICE_DCB_NO_HW_CHG)
err = ICE_DCB_HW_CHG_RST;
+pfc_out:
mutex_unlock(&pf->tc_mutex);
return err;
}
@@ -845,6 +858,12 @@ static int ice_dcbnl_setapp(struct net_device *netdev, struct dcb_app *app)
new_cfg->dscp_map[app->protocol] = app->priority;
new_cfg->app[new_cfg->numapps++] = new_app;
+ if (!ice_dcb_need_recfg(pf, &pf->hw.port_info->qos_cfg.local_dcbx_cfg,
+ new_cfg)) {
+ ret = ICE_DCB_NO_HW_CHG;
+ goto setapp_out;
+ }
+
ret = ice_pf_dcb_cfg(pf, new_cfg, true);
/* return of zero indicates new cfg applied */
if (ret == ICE_DCB_HW_CHG_RST)
@@ -991,8 +1010,15 @@ static u8 ice_dcbnl_cee_set_all(struct net_device *netdev)
mutex_lock(&pf->tc_mutex);
+ if (!ice_dcb_need_recfg(pf, &pf->hw.port_info->qos_cfg.local_dcbx_cfg,
+ new_cfg)) {
+ err = ICE_DCB_NO_HW_CHG;
+ goto out;
+ }
+
err = ice_pf_dcb_cfg(pf, new_cfg, true);
+out:
mutex_unlock(&pf->tc_mutex);
return (err != ICE_DCB_HW_CHG_RST) ? ICE_DCB_NO_HW_CHG : err;
}
--
2.52.0
^ permalink raw reply related
* [PATCH net] vsock/virtio: fix potential unbounded skb queue
From: Eric Dumazet @ 2026-04-30 12:26 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Paolo Abeni
Cc: Simon Horman, netdev, eric.dumazet, Eric Dumazet, Arseniy Krasnov,
Stefan Hajnoczi, Stefano Garzarella, Michael S. Tsirkin,
Jason Wang, Xuan Zhuo, Eugenio Pérez, kvm, virtualization
virtio_transport_inc_rx_pkt() checks vvs->rx_bytes + len > vvs->buf_alloc.
virtio_transport_recv_enqueue() skips coalescing for packets
with VIRTIO_VSOCK_SEQ_EOM.
If fed with packets with len == 0 and VIRTIO_VSOCK_SEQ_EOM,
a very large number of packets can be queued
because vvs->rx_bytes stays at 0.
Fix this by estimating the skb metadata size:
(Number of skbs in the queue) * SKB_TRUESIZE(0)
Fixes: 077706165717 ("virtio/vsock: don't use skbuff state to account credit")
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Arseniy Krasnov <AVKrasnov@sberdevices.ru>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Cc: "Eugenio Pérez" <eperezma@redhat.com>
Cc: kvm@vger.kernel.org
Cc: virtualization@lists.linux.dev
---
net/vmw_vsock/virtio_transport_common.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/net/vmw_vsock/virtio_transport_common.c b/net/vmw_vsock/virtio_transport_common.c
index 416d533f493d7b07e9c77c43f741d28cfcd0953e..9b8014516f4fb1130ae184635fbba4dfee58bd64 100644
--- a/net/vmw_vsock/virtio_transport_common.c
+++ b/net/vmw_vsock/virtio_transport_common.c
@@ -447,7 +447,9 @@ static int virtio_transport_send_pkt_info(struct vsock_sock *vsk,
static bool virtio_transport_inc_rx_pkt(struct virtio_vsock_sock *vvs,
u32 len)
{
- if (vvs->buf_used + len > vvs->buf_alloc)
+ u64 skb_overhead = (skb_queue_len(&vvs->rx_queue) + 1) * SKB_TRUESIZE(0);
+
+ if (skb_overhead + vvs->buf_used + len > vvs->buf_alloc)
return false;
vvs->rx_bytes += len;
--
2.54.0.545.g6539524ca2-goog
^ permalink raw reply related
* [PATCH linux-firmware v1] ice: add DDP COMMS triple VLAN package 1.3.2.0
From: Aleksandr Loktionov @ 2026-04-30 12:30 UTC (permalink / raw)
To: intel-wired-lan, anthony.l.nguyen, aleksandr.loktionov; +Cc: netdev, Mark Craig
Add ice_comms_triple_vlan-1.3.2.0.pkg, a variant of the ICE COMMS DDP
package that enables transparent passthrough of a third inner VLAN tag
to a SR-IOV Virtual Function.
The standard COMMS DDP package operates in Double VLAN Mode (DVM),
which gives the hardware two VLAN tag slots: one consumed by the outer
port-VLAN (used for DCB traffic classification) and one visible to the
VF. Any third tag present in the frame is stripped before delivery. This
package extends the classification pipeline so that the third tag is
treated as opaque payload and forwarded intact to the VF.
The outermost tag remains subject to DVM constraints because it drives
DCB scheduling; only 0x8100 and 0x88a8 are supported as the outermost
TPID. The middle and innermost tags, including 0x88e7 (ETH_P_8021AH),
are forwarded transparently without modification. Frames with 0x88e7 as
the outermost tag are out of scope as they conflict with DCB
classification.
Testing hints:
# Install ice_comms_triple_vlan package - refer to Dynamic Device
# Personalization section in:
# Documentation/networking/device_drivers/ethernet/intel/ice.rst
# in kernel tree.
modprobe ice
echo 1 > /sys/class/net/$PF/device/sriov_numvfs
ip link set dev $PF vf 0 trust on spoofchk off
ip link set $VF promisc on
ethtool -K $PF rx-vlan-offload off tx-vlan-offload off
ethtool -K $VF rx-vlan-offload off tx-vlan-offload off
# Create triple VLAN stack on link partner and ping through VF:
ip link add link $LP type vlan proto 802.1Q id 100
ip link add link $LP.100 type vlan proto 802.1ad id 200
ip link add link $LP.100.200 type vlan proto 802.1Q id 300
ip addr add 192.168.1.1/24 dev $LP.100.200
ip link set $LP.100 up; ip link set $LP.100.200 up; ip link set $LP.100.200.300 up
# On the VF side create matching stack and verify ping succeeds:
ip link add link $VF type vlan proto 802.1Q id 200
ip link add link $VF.200 type vlan proto 802.1Q id 300
ip addr add 192.168.1.2/24 dev $VF.200.300
ip link set $VF.200 up; ip link set $VF.200.300 up
ping -c 3 192.168.1.1
Signed-off-by: Mark Craig <mark.craig@intel.com>
Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
---
.../ice_comms_triple_vlan-1.3.2.0.pkg | Bin 0 -> 1442692 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
create mode 100644 intel/ice/ddp-comms/ice_comms_triple_vlan-1.3.2.0.pkg
diff --git a/intel/ice/ddp-comms/ice_comms_triple_vlan-1.3.2.0.pkg b/intel/ice/ddp-comms/ice_comms_triple_vlan-1.3.2.0.pkg
new file mode 100644
index 0000000000000000000000000000000000000000..2eda04565817ff94e74642adff31ffc17d638b97
GIT binary patch
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yIs@r6zRBb7^q%HtnDIZOd73R+4F7xtnrNqhot&JUoSdAToSdAToSdBQ8vQ>scN@t7
literal 0
HcmV?d00001
--
2.52.0
^ permalink raw reply
* Re: [PATCH net-next 5/5] selftests: net: add veth BQL stress test
From: Jesper Dangaard Brouer @ 2026-04-30 12:31 UTC (permalink / raw)
To: Simon Schippers, Jonas Köppeler
Cc: andrew+netdev, davem, edumazet, horms, jhs, jiri, kernel-team,
kuba, netdev, pabeni
In-Reply-To: <7bc8edc9-1b46-471a-9a6e-cd2c27aebcfc@tu-dortmund.de>
On 30/04/2026 11.45, Simon Schippers wrote:
> On 4/30/26 11:17, Jonas Köppeler wrote:
>> On 3/28/26 4:19 PM, Simon Schippers wrote:
>>> Hi, thanks for your work! I am really interested in this patchset.
>>>
>>> I am planning to submit a similar patch set (see [1]) for the tun/tap
>>> driver, where I am currently implementing qdisc backpressure similar
>>> to that used in veth.
>>>
>>> Can you run pktgen [2] to see if there is a regression?
>>> I think that there might be a slowdown due to BQL not choosing a big
>>> enough queue size.
>> I ran some tests using pktgen by replacing the trafficgen from the
>> selftest with samples/pktgen/pktgen_sample01_simple.sh (Patch v3)
>> and used --nrules 0. In general the throughput is quite similar:
>>
>> BQL disabled (using --bql-disable):
>> 2378694pps 1141Mb/sec (1141773120bps) errors: 0
>> 2400898pps 1152Mb/sec (1152431040bps) errors: 0
>> 2358125pps 1131Mb/sec (1131900000bps) errors: 0
>> 2402034pps 1152Mb/sec (1152976320bps) errors: 0
>> 2362061pps 1133Mb/sec (1133789280bps) errors: 0
>> 2416301pps 1159Mb/sec (1159824480bps) errors: 0
>> 2398496pps 1151Mb/sec (1151278080bps) errors: 0
>> 2415200pps 1159Mb/sec (1159296000bps) errors: 0
>> 2375921pps 1140Mb/sec (1140442080bps) errors: 0
>> 2427419pps 1165Mb/sec (1165161120bps) errors: 0
>> 2382461pps 1143Mb/sec (1143581280bps) errors: 0
>>
>> mean: 2392510pps
>>
>> BQL enabled:
>> 2159545pps 1036Mb/sec (1036581600bps) errors: 0
>> 2321899pps 1114Mb/sec (1114511520bps) errors: 0
>> 2477853pps 1189Mb/sec (1189369440bps) errors: 0
>> 2447857pps 1174Mb/sec (1174971360bps) errors: 0
>> 2400284pps 1152Mb/sec (1152136320bps) errors: 0
>> 2442841pps 1172Mb/sec (1172563680bps) errors: 0
>> 2442540pps 1172Mb/sec (1172419200bps) errors: 0
>> 2410585pps 1157Mb/sec (1157080800bps) errors: 0
>> 2395902pps 1150Mb/sec (1150032960bps) errors: 0
>> 2393260pps 1148Mb/sec (1148764800bps) errors: 0
>> 2401959pps 1152Mb/sec (1152940320bps) errors: 0
>>
>> mean: 2390411pps
>>
>> BQL enabled is ~2099pps (~0.09%) lower than BQL disabled.
>
> Sounds great!
>
> One more thing:
> Could you check what BQL limit settles during the test run using
> something like:
>
> watch -n 0.1 'cat /sys/class/net/XXXXX/queues/tx-0/byte_queue_limits/limit'
FYI: The selftest already tracks BQL "limit" and "inflight".
- Jonas can just report those BQL inflight logs
+print_periodic_stats() {
+ local elapsed="$1"
+
+ # BQL stats and watchdog counter
+ WD_CNT=$(cat /sys/class/net/${VETH_A}/queues/tx-0/tx_timeout \
+ 2>/dev/null) || WD_CNT="?"
+ if [ -n "$BQL_DIR" ] && [ -d "$BQL_DIR" ]; then
+ INFLIGHT=$(cat "$BQL_DIR/inflight" 2>/dev/null || echo "?")
+ LIMIT=$(cat "$BQL_DIR/limit" 2>/dev/null || echo "?")
+ echo " [${elapsed}s] BQL inflight=${INFLIGHT} limit=${LIMIT}" \
+ "watchdog=${WD_CNT}"
+ else
+ echo " [${elapsed}s] watchdog=${WD_CNT} (no BQL sysfs)"
+ fi
> I guess it will just choose the ptr_ring size as limit in this case,
> but it would be nice if you could briefly verify this :)
>
> Thanks!
>
>>
>>> Thanks!
>>>
>>> [1] Link:https://lore.kernel.org/all/20260312130639.138988-1-simon.schippers@tu-dortmund.de/
>>> [2] Link:https://www.kernel.org/doc/html/latest/networking/pktgen.html
^ permalink raw reply
* [PATCH net] ixgbe: fix X550 AQ PHY identification returning ixgbe_phy_unknown
From: Aleksandr Loktionov @ 2026-04-30 12:31 UTC (permalink / raw)
To: intel-wired-lan, anthony.l.nguyen, aleksandr.loktionov; +Cc: netdev
ixgbe_get_phy_id() reads the two MII_PHYSID registers and combines them
into hw->phy.id with the lower 4 revision bits masked out by
IXGBE_PHY_REVISION_MASK (0xFFFFFFF0).
Commit 5f1c3589b0f0 ("ixgbe: Correct X550 phy ID") replaced
X550_PHY_ID (0x01540220) with X550_PHY_ID2 (0x01540223) and
X550_PHY_ID3 (0x01540221). These are the raw values read directly off
hardware, but after revision-bit masking both reduce to 0x01540220.
The switch cases in ixgbe_get_phy_type_from_id() therefore never match,
and X550 AQ PHY devices always fall through to ixgbe_phy_unknown. A
wrong PHY type means the wrong ops vector is selected, resulting in
failed PHY initialization and no link.
Restore X550_PHY_ID (0x01540220) as the match value -- the
revision-stripped ID that the driver actually stores. Keep X550_PHY_ID2
and X550_PHY_ID3 as documentation of the hardware-reported values.
Fixes: 5f1c3589b0f0 ("ixgbe: Correct X550 phy ID")
Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
---
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c | 3 +--
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h | 1 +
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
index ab733e7..ca98dad 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
@@ -364,8 +364,7 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
case TN1010_PHY_ID:
phy_type = ixgbe_phy_tn;
break;
- case X550_PHY_ID2:
- case X550_PHY_ID3:
+ case X550_PHY_ID:
case X540_PHY_ID:
phy_type = ixgbe_phy_aq;
break;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
index 61f2ef6..0d47622 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
@@ -1412,6 +1412,7 @@ struct ixgbe_nvm_version {
#define TN1010_PHY_ID 0x00A19410
#define TNX_FW_REV 0xB
#define X540_PHY_ID 0x01540200
+#define X550_PHY_ID 0x01540220
#define X550_PHY_ID2 0x01540223
#define X550_PHY_ID3 0x01540221
#define X557_PHY_ID 0x01540240
--
2.52.0
^ permalink raw reply related
* Re: [PATCH net] ipvs: fix shift-out-of-bounds in ip_vs_rht_desired_size
From: Simon Horman @ 2026-04-30 12:39 UTC (permalink / raw)
To: ja
Cc: 'Simon Horman', horms, pablo, fw, lvs-devel,
netfilter-devel, netdev
In-Reply-To: <20260427234014.86256-1-ja@ssi.bg>
From: 'Simon Horman' <horms@kernel.org>
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
Full review at: https://sashiko.dev
---
ipvs: fix shift-out-of-bounds in ip_vs_rht_desired_size
This commit addresses a shift-out-of-bounds issue when roundup_pow_of_two()
is called with 0 in ip_vs_rht_desired_size. It updates the assignment to fall
back to 1 if n is 0.
> diff --git a/net/netfilter/ipvs/ip_vs_core.c b/net/netfilter/ipvs/ip_vs_core.c
> index f5b7a2047291..ea450944465f 100644
> --- a/net/netfilter/ipvs/ip_vs_core.c
> +++ b/net/netfilter/ipvs/ip_vs_core.c
> @@ -237,7 +237,7 @@ int ip_vs_rht_desired_size(struct netns_ipvs *ipvs, struct ip_vs_rht *t, int n,
> {
> if (!t)
> return 1 << min_bits;
> - n = roundup_pow_of_two(n);
> + n = n ? roundup_pow_of_two(n) : 1;
The parameter n is a signed int. If n happens to be negative, it will evaluate
to true and be passed to roundup_pow_of_two().
Because roundup_pow_of_two() casts the input to unsigned long, a negative
value like -1 becomes ULONG_MAX. This results in a shift exponent of 64,
triggering a shift-out-of-bounds regression. Would it be safer to check
for n <= 0 instead?
Additionally, if n exceeds 1.07 billion (1 << 30) on systems with large
amounts of RAM, roundup_pow_of_two(n) evaluates to 1UL << 31. Since n is
a 32-bit signed int, assigning 1UL << 31 back to n overflows and results
in a negative number.
Since subsequent bounds checks use signed comparisons:
> if (lfactor < 0) {
> int factor = min(-lfactor, max_bits);
>
> n = min(n, 1 << (max_bits - factor));
These checks will fail to constrain the size correctly.
[ ... ]
> /* Shrink but keep it n * 2 to prevent frequent resizing */
> return clamp(n << 1, 1 << min_bits, 1 << max_bits);
> }
Eventually, the function returns clamp(n << 1, 1 << min_bits, 1 << max_bits).
Shifting a negative number causes undefined behavior, and the clamp operation
will force the hash table to its absolute minimum size.
Could this cause millions of connections to be placed into a minimally sized
hash table, causing severe collisions during RCU hash lookups?
^ permalink raw reply
* [PATCH 0/3] Add Reorder Completion Queue (RCQ) support
From: Abhijit Gangurde @ 2026-04-30 12:39 UTC (permalink / raw)
To: jgg, leon, brett.creeley, andrew+netdev, davem, edumazet, kuba,
pabeni
Cc: allen.hubbe, nikhil.agarwal, linux-rdma, netdev, linux-kernel,
Abhijit Gangurde
This series adds support for the Reorder Completion Queue (RCQ) feature in the
ionic RDMA driver, enabling userspace to create and configure QPs.
Patch 1 extends the net/ionic firmware identity structure to expose the
default_qp_transport_mode and rcq_sign_bit fields from the RDMA LIF identity.
Patch 2 plumbs these new firmware capabilities through the RDMA driver's LIF
configuration and exposes them to userspace via the ucontext response,
so that rdma-core can discover device support at context allocation time.
Patch 3 allows userspace to select the QP transport mode during QP creation.
The transport mode maps to the corresponding firmware QP type, and the
RCQ path count is forwarded to firmware during QP modify.
Together, these patches provide the kernel-side plumbing needed for the
rdma-core ionic provider to make use of the RCQ feature on capable hardware.
PR: https://github.com/linux-rdma/rdma-core/pull/1733
Abhijit Gangurde (3):
net: ionic: Fetch default QP transport mode and RCQ capabilities from
firmware
RDMA/ionic: Expose QP transport mode and RCQ sign bit to userspace
RDMA/ionic: Support QP transport mode selection in create and modify
.../infiniband/hw/ionic/ionic_controlpath.c | 20 +++++++++++++------
drivers/infiniband/hw/ionic/ionic_fw.h | 18 ++++++++++++++---
drivers/infiniband/hw/ionic/ionic_ibdev.h | 1 +
drivers/infiniband/hw/ionic/ionic_lif_cfg.c | 2 ++
drivers/infiniband/hw/ionic/ionic_lif_cfg.h | 2 ++
.../net/ethernet/pensando/ionic/ionic_if.h | 12 ++++++++++-
include/uapi/rdma/ionic-abi.h | 9 +++++++--
7 files changed, 52 insertions(+), 12 deletions(-)
--
2.43.0
^ permalink raw reply
* [PATCH 1/3] net: ionic: Fetch default QP transport mode and RCQ capabilities from firmware
From: Abhijit Gangurde @ 2026-04-30 12:39 UTC (permalink / raw)
To: jgg, leon, brett.creeley, andrew+netdev, davem, edumazet, kuba,
pabeni
Cc: allen.hubbe, nikhil.agarwal, linux-rdma, netdev, linux-kernel,
Abhijit Gangurde
In-Reply-To: <20260430123931.3256130-1-abhijit.gangurde@amd.com>
Read the default_qp_transport_mode and rcq_sign_bit from the RDMA
LIF identity reported by firmware.
Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com>
---
drivers/net/ethernet/pensando/ionic/ionic_if.h | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_if.h b/drivers/net/ethernet/pensando/ionic/ionic_if.h
index 23d6e2b4791e..f6c2ca335dfb 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_if.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_if.h
@@ -553,6 +553,11 @@ enum ionic_lif_rdma_cap_stats {
* @rdma.eq_qtype: RDMA Event Qtype
* @rdma.stats_type: Supported statistics type
* (enum ionic_lif_rdma_cap_stats)
+ * @rdma.rsvd: Reserved byte
+ * @rdma.rcq_sign_bit: RCQ sign bit
+ * @rdma.srq_qtype: RDMA Shared Receive Qtype
+ * @rdma.rsvd2: Reserved byte
+ * @rdma.default_qp_transport_mode: Default QP transport mode
* @rdma.rsvd1: Reserved byte(s)
* @words: word access to struct contents
*/
@@ -598,7 +603,12 @@ union ionic_lif_identity {
struct ionic_lif_logical_qtype cq_qtype;
struct ionic_lif_logical_qtype eq_qtype;
__le16 stats_type;
- u8 rsvd1[162];
+ u8 rsvd;
+ u8 rcq_sign_bit;
+ struct ionic_lif_logical_qtype srq_qtype;
+ u8 rsvd2;
+ u8 default_qp_transport_mode;
+ u8 rsvd1[146];
} __packed rdma;
} __packed;
__le32 words[478];
--
2.43.0
^ permalink raw reply related
* [PATCH 2/3] RDMA/ionic: Expose QP transport mode and RCQ sign bit to userspace
From: Abhijit Gangurde @ 2026-04-30 12:39 UTC (permalink / raw)
To: jgg, leon, brett.creeley, andrew+netdev, davem, edumazet, kuba,
pabeni
Cc: allen.hubbe, nikhil.agarwal, linux-rdma, netdev, linux-kernel,
Abhijit Gangurde
In-Reply-To: <20260430123931.3256130-1-abhijit.gangurde@amd.com>
Read the default_qp_transport_mode and rcq_sign_bit fields from the
RDMA LIF identity reported by firmware, store them in the driver's
lif_cfg, and expose them to userspace via the ucontext response.
The default_qp_transport_mode indicates which QP transport type the device
uses. The rcq_sign_bit indicates the Reorder Completion Queue
(RCQ) sign bit capability.
Co-developed-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com>
---
drivers/infiniband/hw/ionic/ionic_controlpath.c | 4 +++-
drivers/infiniband/hw/ionic/ionic_lif_cfg.c | 2 ++
drivers/infiniband/hw/ionic/ionic_lif_cfg.h | 2 ++
include/uapi/rdma/ionic-abi.h | 4 +++-
4 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/infiniband/hw/ionic/ionic_controlpath.c b/drivers/infiniband/hw/ionic/ionic_controlpath.c
index 7051a81cca94..6bb645713d6b 100644
--- a/drivers/infiniband/hw/ionic/ionic_controlpath.c
+++ b/drivers/infiniband/hw/ionic/ionic_controlpath.c
@@ -408,13 +408,15 @@ int ionic_alloc_ucontext(struct ib_ucontext *ibctx, struct ib_udata *udata)
resp.udma_count = dev->lif_cfg.udma_count;
resp.expdb_mask = dev->lif_cfg.expdb_mask;
+ resp.rcq_sign_bit = dev->lif_cfg.rcq_sign_bit;
+ resp.default_qp_transport_mode = dev->lif_cfg.default_qp_transport_mode;
if (dev->lif_cfg.sq_expdb)
resp.expdb_qtypes |= IONIC_EXPDB_SQ;
if (dev->lif_cfg.rq_expdb)
resp.expdb_qtypes |= IONIC_EXPDB_RQ;
- rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
+ rc = ib_respond_udata(udata, resp);
if (rc)
goto err_resp;
diff --git a/drivers/infiniband/hw/ionic/ionic_lif_cfg.c b/drivers/infiniband/hw/ionic/ionic_lif_cfg.c
index f3cd281c3a2f..2a27dd22e4c4 100644
--- a/drivers/infiniband/hw/ionic/ionic_lif_cfg.c
+++ b/drivers/infiniband/hw/ionic/ionic_lif_cfg.c
@@ -84,6 +84,8 @@ void ionic_fill_lif_cfg(struct ionic_lif *lif, struct ionic_lif_cfg *cfg)
cfg->udma_count = 2;
cfg->max_stride = ident->rdma.max_stride;
+ cfg->rcq_sign_bit = ident->rdma.rcq_sign_bit;
+ cfg->default_qp_transport_mode = ident->rdma.default_qp_transport_mode;
cfg->expdb_mask = ionic_get_expdb(lif);
cfg->sq_expdb =
diff --git a/drivers/infiniband/hw/ionic/ionic_lif_cfg.h b/drivers/infiniband/hw/ionic/ionic_lif_cfg.h
index 20853429f623..abf169d2727a 100644
--- a/drivers/infiniband/hw/ionic/ionic_lif_cfg.h
+++ b/drivers/infiniband/hw/ionic/ionic_lif_cfg.h
@@ -56,6 +56,8 @@ struct ionic_lif_cfg {
bool sq_expdb;
bool rq_expdb;
u8 expdb_mask;
+ u8 rcq_sign_bit;
+ u8 default_qp_transport_mode;
};
void ionic_fill_lif_cfg(struct ionic_lif *lif, struct ionic_lif_cfg *cfg);
diff --git a/include/uapi/rdma/ionic-abi.h b/include/uapi/rdma/ionic-abi.h
index 7b589d3e9728..fb0d13094c12 100644
--- a/include/uapi/rdma/ionic-abi.h
+++ b/include/uapi/rdma/ionic-abi.h
@@ -46,8 +46,10 @@ struct ionic_ctx_resp {
__u8 udma_count;
__u8 expdb_mask;
__u8 expdb_qtypes;
+ __u8 rcq_sign_bit;
+ __u8 default_qp_transport_mode;
- __u8 rsvd2[3];
+ __u8 rsvd2;
};
struct ionic_qdesc {
--
2.43.0
^ permalink raw reply related
* [PATCH 3/3] RDMA/ionic: Support QP transport mode selection in create and modify
From: Abhijit Gangurde @ 2026-04-30 12:39 UTC (permalink / raw)
To: jgg, leon, brett.creeley, andrew+netdev, davem, edumazet, kuba,
pabeni
Cc: allen.hubbe, nikhil.agarwal, linux-rdma, netdev, linux-kernel,
Abhijit Gangurde
In-Reply-To: <20260430123931.3256130-1-abhijit.gangurde@amd.com>
Allow userspace to specify the QP transport mode and number of
reorder completion queue paths during QP creation and modification.
Extend ionic_qp_req with transport_mode, num_rcq_paths, and
ionic_flags fields. The transport mode selects the firmware QP type,
ionic_flags are forwarded in the upper bits of priv_flags during
QP creation, and num_rcq_paths is passed to firmware during QP
modify.
Co-developed-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com>
---
.../infiniband/hw/ionic/ionic_controlpath.c | 16 +++++++++++-----
drivers/infiniband/hw/ionic/ionic_fw.h | 18 +++++++++++++++---
drivers/infiniband/hw/ionic/ionic_ibdev.h | 1 +
include/uapi/rdma/ionic-abi.h | 5 ++++-
4 files changed, 31 insertions(+), 9 deletions(-)
diff --git a/drivers/infiniband/hw/ionic/ionic_controlpath.c b/drivers/infiniband/hw/ionic/ionic_controlpath.c
index 6bb645713d6b..5a6d4036ea98 100644
--- a/drivers/infiniband/hw/ionic/ionic_controlpath.c
+++ b/drivers/infiniband/hw/ionic/ionic_controlpath.c
@@ -1326,7 +1326,9 @@ static int ionic_create_qp_cmd(struct ionic_ibdev *dev,
struct ionic_qp *qp,
struct ionic_tbl_buf *sq_buf,
struct ionic_tbl_buf *rq_buf,
- struct ib_qp_init_attr *attr)
+ struct ib_qp_init_attr *attr,
+ u32 ionic_flags,
+ enum ionic_qp_transport_mode transport_mode)
{
const u16 dbid = ionic_obj_dbid(dev, pd->ibpd.uobject);
const u32 flags = to_ionic_qp_flags(0, 0,
@@ -1342,8 +1344,9 @@ static int ionic_create_qp_cmd(struct ionic_ibdev *dev,
.len = cpu_to_le16(IONIC_ADMIN_CREATE_QP_IN_V1_LEN),
.cmd.create_qp = {
.pd_id = cpu_to_le32(pd->pdid),
- .priv_flags = cpu_to_be32(flags),
- .type_state = to_ionic_qp_type(attr->qp_type),
+ .priv_flags = cpu_to_be32(flags |
+ (ionic_flags & IONIC_QP_USER_FLAGS_MASK)),
+ .type_state = to_ionic_qp_type(attr->qp_type, transport_mode),
.dbid_flags = cpu_to_le16(dbid),
.id_ver = cpu_to_le32(qp->qpid),
}
@@ -1412,6 +1415,7 @@ static int ionic_modify_qp_cmd(struct ionic_ibdev *dev,
(attr->rnr_retry << 4)),
.rnr_timer = attr->min_rnr_timer,
.retry_timeout = attr->timeout,
+ .mrc_num_paths = qp->num_rcq_paths,
.type_state = state,
.id_ver = cpu_to_le32(qp->qpid),
}
@@ -2156,7 +2160,7 @@ int ionic_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attr,
int rc;
if (udata) {
- rc = ib_copy_validate_udata_in(udata, req, rsvd);
+ rc = ib_copy_validate_udata_in(udata, req, ionic_flags);
if (rc)
return rc;
} else {
@@ -2203,6 +2207,7 @@ int ionic_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attr,
qp->sig_all = attr->sq_sig_type == IB_SIGNAL_ALL_WR;
qp->has_ah = attr->qp_type == IB_QPT_RC;
+ qp->num_rcq_paths = req.num_rcq_paths;
if (qp->has_ah) {
qp->hdr = kzalloc_obj(*qp->hdr);
@@ -2239,7 +2244,8 @@ int ionic_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attr,
rc = ionic_create_qp_cmd(dev, pd,
to_ionic_vcq_cq(attr->send_cq, qp->udma_idx),
to_ionic_vcq_cq(attr->recv_cq, qp->udma_idx),
- qp, &sq_buf, &rq_buf, attr);
+ qp, &sq_buf, &rq_buf, attr, req.ionic_flags,
+ req.transport_mode);
if (rc)
goto err_cmd;
diff --git a/drivers/infiniband/hw/ionic/ionic_fw.h b/drivers/infiniband/hw/ionic/ionic_fw.h
index adfbb89d856c..3a31cd9073ca 100644
--- a/drivers/infiniband/hw/ionic/ionic_fw.h
+++ b/drivers/infiniband/hw/ionic/ionic_fw.h
@@ -105,6 +105,8 @@ enum ionic_qp_flags {
IONIC_QPF_SQ_CMB = BIT(13),
IONIC_QPF_RQ_CMB = BIT(14),
IONIC_QPF_PRIVILEGED = BIT(15),
+
+ IONIC_QP_USER_FLAGS_MASK = GENMASK(31, 16),
};
static inline int from_ionic_qp_flags(int flags)
@@ -218,6 +220,11 @@ static inline int ionic_to_ib_status(int sts)
}
}
+enum ionic_qp_transport_mode {
+ IONIC_QPT_TRANSPORT_ROCE_V2 = BIT(0),
+ IONIC_QPT_TRANSPORT_MRC = BIT(1),
+};
+
/* admin queue qp type */
enum ionic_qp_type {
IONIC_QPT_RC,
@@ -228,16 +235,21 @@ enum ionic_qp_type {
IONIC_QPT_XRC_INI,
IONIC_QPT_XRC_TGT,
IONIC_QPT_XRC_SRQ,
+ IONIC_QPT_MRC,
};
-static inline int to_ionic_qp_type(enum ib_qp_type type)
+static inline int to_ionic_qp_type(enum ib_qp_type type,
+ enum ionic_qp_transport_mode tm)
{
switch (type) {
case IB_QPT_GSI:
case IB_QPT_UD:
return IONIC_QPT_UD;
case IB_QPT_RC:
- return IONIC_QPT_RC;
+ if (tm == IONIC_QPT_TRANSPORT_MRC)
+ return IONIC_QPT_MRC;
+ else
+ return IONIC_QPT_RC;
case IB_QPT_UC:
return IONIC_QPT_UC;
case IB_QPT_XRC_INI:
@@ -808,7 +820,7 @@ struct ionic_admin_mod_qp {
__le32 ah_id_len;
__u8 en_pcp;
__u8 ip_dscp;
- __u8 rsvd2;
+ __u8 mrc_num_paths;
__u8 type_state;
union {
struct {
diff --git a/drivers/infiniband/hw/ionic/ionic_ibdev.h b/drivers/infiniband/hw/ionic/ionic_ibdev.h
index 63828240d659..24a7f93e1f00 100644
--- a/drivers/infiniband/hw/ionic/ionic_ibdev.h
+++ b/drivers/infiniband/hw/ionic/ionic_ibdev.h
@@ -253,6 +253,7 @@ struct ionic_qp {
u8 has_sq:1;
u8 has_rq:1;
u8 sig_all:1;
+ u8 num_rcq_paths;
struct list_head qp_list_counter;
diff --git a/include/uapi/rdma/ionic-abi.h b/include/uapi/rdma/ionic-abi.h
index fb0d13094c12..bd02e4541d85 100644
--- a/include/uapi/rdma/ionic-abi.h
+++ b/include/uapi/rdma/ionic-abi.h
@@ -85,7 +85,10 @@ struct ionic_qp_req {
__u8 sq_cmb;
__u8 rq_cmb;
__u8 udma_mask;
- __u8 rsvd[3];
+ __u8 num_rcq_paths;
+ __u8 transport_mode;
+ __u8 rsvd;
+ __u32 ionic_flags;
};
struct ionic_qp_resp {
--
2.43.0
^ permalink raw reply related
* Re: [PATCH net v5] ipv6: Implement limits on extension header parsing
From: Ido Schimmel @ 2026-04-30 12:40 UTC (permalink / raw)
To: Daniel Borkmann
Cc: kuba, edumazet, dsahern, tom, willemdebruijn.kernel, pabeni,
justin.iurman, netdev
In-Reply-To: <20260429154648.809751-1-daniel@iogearbox.net>
On Wed, Apr 29, 2026 at 05:46:48PM +0200, Daniel Borkmann wrote:
> ipv6_{skip_exthdr,find_hdr}() and ip6_{tnl_parse_tlv_enc_lim,
> protocol_deliver_rcu}() iterate over IPv6 extension headers until they
> find a non-extension-header protocol or run out of packet data. The
> loops have no iteration counter, relying solely on the packet length
> to bound them. For a crafted packet with 8-byte extension headers
> filling a 64KB jumbogram, this means a worst case of up to ~8k
> iterations with a skb_header_pointer call each. ipv6_skip_exthdr(),
> for example, is used where it parses the inner quoted packet inside
> an incoming ICMPv6 error:
>
> - icmpv6_rcv
> - checksum validation
> - case ICMPV6_DEST_UNREACH
> - icmpv6_notify
> - pskb_may_pull() <- pull inner IPv6 header
> - ipv6_skip_exthdr() <- iterates here
> - pskb_may_pull()
> - ipprot->err_handler() <- sk lookup
>
> The per-iteration cost of ipv6_skip_exthdr itself is generally
> light, but skb_header_pointer becomes more costly on reassembled
> packets: the first ~1232 bytes of the inner packet are in the skb's
> linear area, but the remaining ~63KB are in the frag_list where
> skb_copy_bits is needed to read data.
>
> Initially, the idea was to add a configurable limit via a new
> sysctl knob with default 8, in line with knobs from commit
> 47d3d7ac656a ("ipv6: Implement limits on Hop-by-Hop and Destination
> options"), but two reasons eventually argued against it:
>
> - It adds to UAPI that needs to be maintained forever, and
> upcoming work is restricting extension header ordering anyway,
> leaving little reason for another sysctl knob
> - exthdrs_core.c is always built-in even when CONFIG_IPV6=n,
> where struct net has no .ipv6 member, so the read site would
> need an ifdef'd fallback to a constant anyway
>
> Therefore, just use a constant (IP6_MAX_EXT_HDRS_CNT). All four
> extension header walking functions are now bound by this limit.
>
> Note that the check in ip6_protocol_deliver_rcu() happens right
> before the goto resubmit, such that we don't have to have a test
> for ipv6_ext_hdr() in the fast-path.
>
> There's an ongoing IETF draft-iurman-6man-eh-occurrences to enforce
> IPv6 extension headers ordering and occurrence. The latter also
> discusses security implications. As per RFC8200 section 4.1, the
> occurrence rules for extension headers provide a practical upper
> bound which is 8. In order to be conservative, let's define
> IP6_MAX_EXT_HDRS_CNT as 12 to leave enough room for quirky setups.
> In the unlikely event that this is still not enough, then we might
> need to reconsider a sysctl.
>
> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
^ permalink raw reply
* [PATCH net-next v2 0/2] mv88e6xxx: SERDES on mv88e6321 letter
From: Fidan Aliyeva @ 2026-04-30 12:49 UTC (permalink / raw)
To: andrew, olteanv, davem, edumazet, kuba, pabeni, netdev
Cc: linux-kernel, thomas.eckerman.ext, Fidan Aliyeva
This patch series add code support to be able to use SERDES feature of
mv88e6321 version of Marvel mv88e6xxx series. mv88e6321 has 2 ports to
support high speed SERDES but the support is lacking in the driver.
mv88e6321 version has a similar architecture to mv88e6352 version making it
possible to reuse its pcs functions. That's why the patch series consist of
2 parts:
1. Refactor the serdes functions and pcs_init of mv88e6352 to be more
generic
2. Add the SERDES support for mv88e6321 reusing 6352's pcs functions
The final code has been built on top of net-next tree and tested on
mv88e6321 ethernet device directly by ip ping tests, performance tests and
also verifying the switch's expected register values.
Referred document: 88E6321/88E6320 Functional Specification
Code has been built with allmodconfig and allyesconfig. checkpatch.pl was
also run
---
Changes in v2:
- Removed 6321-specific pcs_init and made 6352's pcs_init more generic
as suggested by Andrew Lunn
- Added the correct mailing list
---
Fidan Aliyeva (2):
mv88e6xxx: Refactor 6352's serdes functions
mv88e6xxx: Add SERDES Support for mv88e6321
drivers/net/dsa/mv88e6xxx/chip.c | 8 +++
drivers/net/dsa/mv88e6xxx/pcs-6352.c | 12 ++--
drivers/net/dsa/mv88e6xxx/serdes.c | 87 ++++++++++++++++++++++------
drivers/net/dsa/mv88e6xxx/serdes.h | 5 ++
4 files changed, 86 insertions(+), 26 deletions(-)
--
2.36.0
^ permalink raw reply
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