* [PATCH v19 net-next 11/11] net/nebula-matrix: add common dev start/stop operation
From: illusion.wang @ 2026-06-17 4:46 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, horms, linux-doc, pabeni,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
In-Reply-To: <20260617044702.2439-1-illusion.wang@nebula-matrix.com>
This patch wires up nbl_dev_start() and nbl_dev_stop() to configure
the MSI-X map, allocate vectors, and request/enable the mailbox IRQ.
It also replaces module_pci_driver() with explicit init/exit functions
that additionally create and destroy the driver's workqueue via
nbl_common_create_wq() / nbl_common_destroy_wq(), which is needed
because the new IRQ handler schedules work through
nbl_common_queue_work().
Signed-off-by: illusion.wang <illusion.wang@nebula-matrix.com>
---
.../nebula-matrix/nbl/nbl_common/nbl_common.c | 24 ++
.../nebula-matrix/nbl/nbl_core/nbl_dev.c | 250 +++++++++++++++++-
.../nebula-matrix/nbl/nbl_hw/nbl_resource.c | 2 +-
.../nbl/nbl_include/nbl_def_common.h | 6 +
4 files changed, 280 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c
index 2954cbbe0f95..bae1a7e401ce 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c
@@ -6,6 +6,30 @@
#include <linux/device.h>
#include "nbl_common.h"
+void nbl_common_queue_work(struct nbl_common_info *common,
+ struct work_struct *task)
+{
+ queue_work(common->wq, task);
+}
+
+void nbl_common_destroy_wq(struct nbl_common_info *common)
+{
+ destroy_workqueue(common->wq);
+}
+
+int nbl_common_create_wq(struct nbl_common_info *common)
+{
+ common->wq = alloc_workqueue("nbl_wq", WQ_UNBOUND, 0);
+ if (!common->wq) {
+ pr_err("Failed to create workqueue nbl_wq\n");
+ goto alloc_wq_failed;
+ }
+
+ return 0;
+alloc_wq_failed:
+ return -ENOMEM;
+}
+
u32 nbl_common_pf_id_subtraction_mgtpf_id(struct nbl_common_info *common,
u32 pf_id)
{
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c
index 8feae561d0f1..288b2dae8681 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c
@@ -6,6 +6,17 @@
#include <linux/pci.h>
#include "nbl_dev.h"
+static void nbl_dev_clean_mailbox_schedule(struct nbl_dev_mgt *dev_mgt);
+
+/* ---------- Interrupt config ---------- */
+static irqreturn_t nbl_dev_clean_mailbox(int __always_unused irq, void *data)
+{
+ struct nbl_dev_mgt *dev_mgt = (struct nbl_dev_mgt *)data;
+
+ nbl_dev_clean_mailbox_schedule(dev_mgt);
+ return IRQ_HANDLED;
+}
+
static void nbl_dev_init_msix_cnt(struct nbl_dev_mgt *dev_mgt)
{
struct nbl_dev_common *dev_common = dev_mgt->common_dev;
@@ -14,6 +25,182 @@ static void nbl_dev_init_msix_cnt(struct nbl_dev_mgt *dev_mgt)
msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].num = 1;
}
+static int nbl_dev_request_mailbox_irq(struct nbl_dev_mgt *dev_mgt)
+{
+ struct nbl_dev_common *dev_common = dev_mgt->common_dev;
+ struct nbl_msix_info *msix_info = &dev_common->msix_info;
+ struct nbl_common_info *common = dev_mgt->common;
+ u16 local_vec_id;
+ int irq_num;
+ int err;
+
+ if (!msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].num)
+ return 0;
+
+ local_vec_id =
+ msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].base_vector_id;
+ irq_num = pci_irq_vector(common->pdev, local_vec_id);
+ if (irq_num < 0) {
+ dev_err(common->dev, "Failed to get mailbox IRQ vector: %d\n",
+ irq_num);
+ return irq_num;
+ }
+
+ snprintf(dev_common->mailbox_name, sizeof(dev_common->mailbox_name),
+ "nbl_mailbox@pci:%s", pci_name(common->pdev));
+ err = request_irq(irq_num, nbl_dev_clean_mailbox, 0,
+ dev_common->mailbox_name, dev_mgt);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static void nbl_dev_free_mailbox_irq(struct nbl_dev_mgt *dev_mgt)
+{
+ struct nbl_dev_common *dev_common = dev_mgt->common_dev;
+ struct nbl_msix_info *msix_info = &dev_common->msix_info;
+ struct nbl_common_info *common = dev_mgt->common;
+ u16 local_vec_id;
+ int irq_num;
+
+ if (!msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].num)
+ return;
+
+ local_vec_id =
+ msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].base_vector_id;
+ irq_num = pci_irq_vector(common->pdev, local_vec_id);
+ if (irq_num >= 0)
+ free_irq(irq_num, dev_mgt);
+}
+
+static int nbl_dev_enable_mailbox_irq(struct nbl_dev_mgt *dev_mgt)
+{
+ struct nbl_dispatch_ops *disp_ops = dev_mgt->disp_ops_tbl->ops;
+ struct nbl_channel_ops *chan_ops = dev_mgt->chan_ops_tbl->ops;
+ struct nbl_dev_common *dev_common = dev_mgt->common_dev;
+ struct nbl_msix_info *msix_info = &dev_common->msix_info;
+ u16 local_vec_id;
+
+ if (!msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].num)
+ return 0;
+
+ local_vec_id =
+ msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].base_vector_id;
+ chan_ops->set_queue_state(dev_mgt->chan_ops_tbl->priv,
+ NBL_CHAN_INTERRUPT_READY,
+ NBL_CHAN_TYPE_MAILBOX, true);
+
+ return disp_ops->set_mailbox_irq(dev_mgt->disp_ops_tbl->priv,
+ local_vec_id, true);
+}
+
+static int nbl_dev_disable_mailbox_irq(struct nbl_dev_mgt *dev_mgt)
+{
+ struct nbl_dispatch_ops *disp_ops = dev_mgt->disp_ops_tbl->ops;
+ struct nbl_channel_ops *chan_ops = dev_mgt->chan_ops_tbl->ops;
+ struct nbl_dev_common *dev_common = dev_mgt->common_dev;
+ struct nbl_msix_info *msix_info = &dev_common->msix_info;
+ u16 local_vec_id;
+
+ if (!msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].num)
+ return 0;
+
+ local_vec_id =
+ msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].base_vector_id;
+ /*
+ * Disable order: software state first, then hardware.
+ *
+ * Review suggested HW-then-state for symmetry with enable, but that
+ * causes "Channel waiting ack failed" errors. The reason: after
+ * set_mailbox_irq(..., false) disables the hardware, the device may
+ * still be sending ACKs for in-flight messages. If we then switch to
+ * polling mode (clear INTERRUPT_READY), the ACK handler won't process
+ * those pending ACKs, leading to "waiting ack failed" and "Skip ack
+ * with invalid status" errors.
+ *
+ * The original state-then-HW order avoids this: we switch to polling
+ * first, so any late interrupts are silently ignored (no ACK expected),
+ * then we disable the hardware. The theoretical window where an
+ * interrupt could fire and be ignored is harmless here because this
+ * function is only called on the error path of nbl_dev_start(),
+ * immediately followed by nbl_dev_free_mailbox_irq() and
+ * cancel_work_sync(&clean_mbx_task). The channel is torn down right
+ * after, so no descriptors can be left stuck.
+ *
+ * Do NOT change to HW-then-state.
+ */
+ chan_ops->set_queue_state(dev_mgt->chan_ops_tbl->priv,
+ NBL_CHAN_INTERRUPT_READY,
+ NBL_CHAN_TYPE_MAILBOX, false);
+
+ return disp_ops->set_mailbox_irq(dev_mgt->disp_ops_tbl->priv,
+ local_vec_id, false);
+}
+
+static int nbl_dev_configure_msix_map(struct nbl_dev_mgt *dev_mgt)
+{
+ struct nbl_dispatch_ops *disp_ops = dev_mgt->disp_ops_tbl->ops;
+ struct nbl_dev_common *dev_common = dev_mgt->common_dev;
+ struct nbl_msix_info *msix_info = &dev_common->msix_info;
+ bool mask_en = msix_info->serv_info[NBL_MSIX_NET_TYPE].hw_self_mask_en;
+ u16 msix_net_num = msix_info->serv_info[NBL_MSIX_NET_TYPE].num;
+ u16 msix_not_net_num = 0;
+ int err, i;
+
+ msix_info->serv_info[NBL_MSIX_VIRTIO_TYPE].base_vector_id = 0;
+ for (i = NBL_MSIX_NET_TYPE; i < NBL_MSIX_TYPE_MAX; i++)
+ msix_info->serv_info[i].base_vector_id =
+ msix_info->serv_info[i - 1].base_vector_id +
+ msix_info->serv_info[i - 1].num;
+
+ for (i = NBL_MSIX_MAILBOX_TYPE; i < NBL_MSIX_TYPE_MAX; i++)
+ msix_not_net_num += msix_info->serv_info[i].num;
+
+ err = disp_ops->configure_msix_map(dev_mgt->disp_ops_tbl->priv,
+ msix_net_num, msix_not_net_num,
+ mask_en);
+
+ return err;
+}
+
+static int nbl_dev_destroy_msix_map(struct nbl_dev_mgt *dev_mgt)
+{
+ struct nbl_dispatch_ops *disp_ops = dev_mgt->disp_ops_tbl->ops;
+
+ return disp_ops->destroy_msix_map(dev_mgt->disp_ops_tbl->priv);
+}
+
+static int nbl_dev_init_interrupt_scheme(struct nbl_dev_mgt *dev_mgt)
+{
+ struct nbl_dev_common *dev_common = dev_mgt->common_dev;
+ struct nbl_msix_info *msix_info = &dev_common->msix_info;
+ struct nbl_common_info *common = dev_mgt->common;
+ int needed = 0;
+ int err;
+ int i;
+
+ for (i = 0; i < NBL_MSIX_TYPE_MAX; i++)
+ needed += msix_info->serv_info[i].num;
+
+ err = pci_alloc_irq_vectors(common->pdev, needed, needed,
+ PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
+ if (err < 0) {
+ dev_err(common->dev,
+ "pci_alloc_irq_vectors failed, err = %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static void nbl_dev_clear_interrupt_scheme(struct nbl_dev_mgt *dev_mgt)
+{
+ struct nbl_common_info *common = dev_mgt->common;
+
+ pci_free_irq_vectors(common->pdev);
+}
+
/* ---------- Channel config ---------- */
static void nbl_dev_setup_chan_qinfo(struct nbl_dev_mgt *dev_mgt, u8 chan_type)
{
@@ -72,6 +259,14 @@ static void nbl_dev_clean_mailbox_task(struct work_struct *work)
NBL_CHAN_TYPE_MAILBOX);
}
+static void nbl_dev_clean_mailbox_schedule(struct nbl_dev_mgt *dev_mgt)
+{
+ struct nbl_dev_common *common_dev = dev_mgt->common_dev;
+ struct nbl_common_info *common = dev_mgt->common;
+
+ nbl_common_queue_work(common, &common_dev->clean_mbx_task);
+}
+
/* ---------- Dev init process ---------- */
static int nbl_dev_setup_common_dev(struct nbl_adapter *adapter)
{
@@ -189,7 +384,7 @@ int nbl_dev_init(struct nbl_adapter *adapter)
dev_mgt->disp_ops_tbl = disp_ops_tbl;
dev_mgt->chan_ops_tbl = chan_ops_tbl;
adapter->core.dev_mgt = dev_mgt;
-
+ ret = nbl_common_create_wq(common);
ret = nbl_dev_setup_common_dev(adapter);
if (ret)
return ret;
@@ -213,14 +408,67 @@ void nbl_dev_remove(struct nbl_adapter *adapter)
if (common->has_ctrl)
nbl_dev_remove_ctrl_dev(adapter);
nbl_dev_remove_common_dev(adapter);
+ nbl_common_destroy_wq(common);
}
/* ---------- Dev start process ---------- */
int nbl_dev_start(struct nbl_adapter *adapter)
{
+ struct nbl_dev_mgt *dev_mgt = adapter->core.dev_mgt;
+ struct nbl_dev_common *common_dev = dev_mgt->common_dev;
+ int cleanup_ret;
+ int ret;
+
+ ret = nbl_dev_configure_msix_map(dev_mgt);
+ if (ret)
+ return ret;
+
+ ret = nbl_dev_init_interrupt_scheme(dev_mgt);
+ if (ret)
+ goto init_interrupt_scheme_err;
+ ret = nbl_dev_request_mailbox_irq(dev_mgt);
+ if (ret)
+ goto mailbox_request_irq_err;
+ ret = nbl_dev_enable_mailbox_irq(dev_mgt);
+ if (ret)
+ goto enable_mailbox_irq_err;
+
return 0;
+enable_mailbox_irq_err:
+ cleanup_ret = nbl_dev_disable_mailbox_irq(dev_mgt);
+ /* just log err*/
+ if (cleanup_ret)
+ dev_err(dev_mgt->common->dev,
+ "Failed to disable mailbox IRQ: %d\n", cleanup_ret);
+ nbl_dev_free_mailbox_irq(dev_mgt);
+ cancel_work_sync(&common_dev->clean_mbx_task);
+mailbox_request_irq_err:
+ nbl_dev_clear_interrupt_scheme(dev_mgt);
+init_interrupt_scheme_err:
+ cleanup_ret = nbl_dev_destroy_msix_map(dev_mgt);
+ /* just log err*/
+ if (cleanup_ret)
+ dev_err(dev_mgt->common->dev,
+ "Failed to destroy MSI-X map: %d\n", cleanup_ret);
+ return ret;
}
void nbl_dev_stop(struct nbl_adapter *adapter)
{
+ struct nbl_dev_mgt *dev_mgt = adapter->core.dev_mgt;
+ struct nbl_dev_common *common_dev = dev_mgt->common_dev;
+ int ret;
+
+ /* just log err*/
+ ret = nbl_dev_disable_mailbox_irq(dev_mgt);
+ if (ret)
+ dev_err(dev_mgt->common->dev,
+ "Failed to disable mailbox IRQ: %d\n", ret);
+ nbl_dev_free_mailbox_irq(dev_mgt);
+ cancel_work_sync(&common_dev->clean_mbx_task);
+ nbl_dev_clear_interrupt_scheme(dev_mgt);
+ ret = nbl_dev_destroy_msix_map(dev_mgt);
+ if (ret)
+ dev_err(dev_mgt->common->dev,
+ "Failed to destroy MSI-X map: %d\n", ret);
}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c
index 6742da7c6637..e8d43bef8687 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c
@@ -112,7 +112,7 @@ int nbl_res_get_eth_id(struct nbl_resource_mgt *res_mgt, u16 func_id,
return -EINVAL;
}
if (abs_pf_id != pfid) {
- dev_err(dev, "invalid pf id %u\n", pfid);
+ dev_err(dev, "invalid pf id %u vsi %u\n", pfid, vsi_id);
return -EINVAL;
}
rel_pf_id = abs_pf_id - common->mgt_pf;
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
index bc741b7df7b9..4621b3ce5856 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
@@ -29,6 +29,7 @@ struct nbl_hash_tbl_mgt;
})
struct nbl_common_info {
+ struct workqueue_struct *wq;
struct pci_dev *pdev;
struct device *dev;
u32 msg_enable;
@@ -61,6 +62,11 @@ struct nbl_hash_tbl_del_key {
void (*action_func)(void *priv, void *key, void *data);
};
+void nbl_common_queue_work(struct nbl_common_info *common,
+ struct work_struct *task);
+
+void nbl_common_destroy_wq(struct nbl_common_info *common);
+int nbl_common_create_wq(struct nbl_common_info *common);
u32 nbl_common_pf_id_subtraction_mgtpf_id(struct nbl_common_info *common,
u32 pf_id);
--
2.47.3
^ permalink raw reply related
* [PATCH v19 net-next 05/11] net/nebula-matrix: add channel layer
From: illusion.wang @ 2026-06-17 4:46 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, horms, linux-doc, pabeni,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
In-Reply-To: <20260617044702.2439-1-illusion.wang@nebula-matrix.com>
A channel management layer provides a structured approach to handle
communication between different components and drivers. Here's a summary
of its key functionalities:
1. Message Handling Framework
Message Registration: Functions (nbl_chan_register_msg) allow dynamic
registration of message handlers for specific message types, enabling
extensible communication protocols.
Message Sending/Acknowledgment: Core functions (nbl_chan_send_msg,
nbl_chan_send_ack) handle message transmission, including asynchronous
operations with acknowledgment (ACK) support. Received ACKs are
processed via nbl_chan_recv_ack_msg.
Hash-Based Handler Lookup: A hash table (`handle_hash_tbl`) stores
message handlers for efficient O(1) lookup by message type. The
entire table is removed via `nbl_chan_remove_msg_handler` during
driver teardown (per-message-type removal is not implemented
in this version).
2. Channel Types and Queue Management
Mailbox Channel: For direct communication between PF0 and Other PF.
Queue Initialization: Functions (nbl_chan_init_queue,
nbl_chan_init_tx_queue) allocate resources:
- TX descriptors: dmam_alloc_coherent()
- RX descriptors: dmam_alloc_coherent()
- TX/RX buffer metadata arrays (txq->buf, rxq->buf): devm_kcalloc()
Queue Teardown: nbl_chan_teardown_queue() stops queues, cancels
pending work items (clean_task), and destroys mutexes. It does NOT
free DMA memory, which is released automatically via devm on driver
remove.
IMPORTANT - Resource Lifecycle Design:
DMA memory allocated with dmam_alloc_coherent() is intentionally NOT
freed in nbl_chan_teardown_queue(). The queues are allocated once
during driver probe and freed only during driver remove (when all
devm_ resources are released). This assumes queues are NOT dynamically
torn down and recreated per-PF during normal operation.
Queue Configuration: Hardware-specific queue parameters (e.g., buffer
sizes, entry counts) are set via nbl_chan_config_queue, with hardware
interactions delegated to hw_ops.
3. Hardware Abstraction Layer (HW Ops)
Hardware-Specific Operations: The nbl_hw_ops structure abstracts
hardware interactions: queue configuration (config_mailbox_txq/rxq),
tail pointer updates (update_mailbox_queue_tail_ptr).
Signed-off-by: illusion.wang <illusion.wang@nebula-matrix.com>
---
.../net/ethernet/nebula-matrix/nbl/Makefile | 3 +-
.../nbl/nbl_channel/nbl_channel.c | 1006 ++++++++++++++++-
.../nbl/nbl_channel/nbl_channel.h | 137 +++
.../nebula-matrix/nbl/nbl_common/nbl_common.c | 193 ++++
.../nebula-matrix/nbl/nbl_common/nbl_common.h | 33 +
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 146 +++
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h | 57 +
.../nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h | 1 +
.../nbl/nbl_include/nbl_def_channel.h | 83 ++
.../nbl/nbl_include/nbl_def_common.h | 26 +
.../nbl/nbl_include/nbl_def_hw.h | 27 +
.../nbl/nbl_include/nbl_include.h | 6 +
12 files changed, 1714 insertions(+), 4 deletions(-)
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
index 63116d1d7043..c9bc060732e7 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile
+++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
@@ -3,7 +3,8 @@
obj-$(CONFIG_NBL) := nbl.o
-nbl-objs += nbl_channel/nbl_channel.o \
+nbl-objs += nbl_common/nbl_common.o \
+ nbl_channel/nbl_channel.o \
nbl_hw/nbl_hw_leonis/nbl_hw_leonis.o \
nbl_hw/nbl_hw_leonis/nbl_resource_leonis.o \
nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.o \
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
index c7689f0e4029..6839972324b0 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
@@ -2,12 +2,981 @@
/*
* Copyright (c) 2025 Nebula Matrix Limited.
*/
-
+#include <linux/delay.h>
#include <linux/device.h>
+#include <linux/bitfield.h>
#include <linux/pci.h>
+#include <linux/bits.h>
+#include <linux/dma-mapping.h>
#include "nbl_channel.h"
+static int nbl_chan_add_msg_handler(struct nbl_channel_mgt *chan_mgt,
+ u16 msg_type, nbl_chan_resp func,
+ void *priv)
+{
+ struct nbl_chan_msg_node_data handler = { 0 };
+ int ret;
+
+ handler.func = func;
+ handler.priv = priv;
+ ret = nbl_common_alloc_hash_node(chan_mgt->handle_hash_tbl, &msg_type,
+ &handler, NULL);
+
+ return ret;
+}
+
+static int nbl_chan_init_msg_handler(struct nbl_channel_mgt *chan_mgt)
+{
+ struct nbl_common_info *common = chan_mgt->common;
+ struct nbl_hash_tbl_key tbl_key = { 0 };
+
+ tbl_key.dev = common->dev;
+ tbl_key.key_size = sizeof(u16);
+ tbl_key.data_size = sizeof(struct nbl_chan_msg_node_data);
+ tbl_key.bucket_size = NBL_CHAN_HANDLER_TBL_BUCKET_SIZE;
+
+ chan_mgt->handle_hash_tbl = nbl_common_init_hash_table(&tbl_key);
+ if (!chan_mgt->handle_hash_tbl)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void nbl_chan_remove_msg_handler(struct nbl_channel_mgt *chan_mgt)
+{
+ nbl_common_remove_hash_table(chan_mgt->handle_hash_tbl, NULL);
+
+ chan_mgt->handle_hash_tbl = NULL;
+}
+
+static void nbl_chan_init_queue_param(struct nbl_chan_info *chan_info,
+ u16 num_txq_entries, u16 num_rxq_entries,
+ u16 txq_buf_size, u16 rxq_buf_size)
+{
+ mutex_init(&chan_info->txq_lock);
+ chan_info->num_txq_entries = num_txq_entries;
+ chan_info->num_rxq_entries = num_rxq_entries;
+ chan_info->txq_buf_size = txq_buf_size;
+ chan_info->rxq_buf_size = rxq_buf_size;
+}
+
+static int nbl_chan_init_tx_queue(struct nbl_common_info *common,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_chan_ring *txq = &chan_info->txq;
+ struct device *dev = common->dev;
+ size_t size =
+ chan_info->num_txq_entries * sizeof(struct nbl_chan_tx_desc);
+ int i;
+
+ txq->desc.tx_desc =
+ dmam_alloc_coherent(dev, size, &txq->dma, GFP_KERNEL);
+ if (!txq->desc.tx_desc)
+ return -ENOMEM;
+
+ chan_info->wait = devm_kcalloc(dev, chan_info->num_txq_entries,
+ sizeof(*chan_info->wait), GFP_KERNEL);
+ if (!chan_info->wait)
+ return -ENOMEM;
+ for (i = 0; i < chan_info->num_txq_entries; i++) {
+ init_waitqueue_head(&chan_info->wait[i].wait_queue);
+ chan_info->wait[i].status = NBL_MBX_STATUS_IDLE;
+ spin_lock_init(&chan_info->wait[i].status_lock);
+ }
+
+ txq->buf = devm_kcalloc(dev, chan_info->num_txq_entries,
+ sizeof(*txq->buf), GFP_KERNEL);
+ if (!txq->buf)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int nbl_chan_init_rx_queue(struct nbl_common_info *common,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_chan_ring *rxq = &chan_info->rxq;
+ struct device *dev = common->dev;
+ size_t size =
+ chan_info->num_rxq_entries * sizeof(struct nbl_chan_rx_desc);
+
+ rxq->desc.rx_desc =
+ dmam_alloc_coherent(dev, size, &rxq->dma, GFP_KERNEL);
+ if (!rxq->desc.rx_desc) {
+ dev_err(dev,
+ "Allocate DMA for chan rx descriptor ring failed\n");
+ return -ENOMEM;
+ }
+
+ rxq->buf = devm_kcalloc(dev, chan_info->num_rxq_entries,
+ sizeof(*rxq->buf), GFP_KERNEL);
+ if (!rxq->buf)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int nbl_chan_init_queue(struct nbl_common_info *common,
+ struct nbl_chan_info *chan_info)
+{
+ int err;
+
+ err = nbl_chan_init_tx_queue(common, chan_info);
+ if (err)
+ return err;
+
+ err = nbl_chan_init_rx_queue(common, chan_info);
+
+ return err;
+}
+
+static void nbl_chan_config_queue(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info, bool tx)
+{
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+ struct nbl_hw_mgt *p = chan_mgt->hw_ops_tbl->priv;
+ int size_bwid;
+ struct nbl_chan_ring *ring;
+ dma_addr_t dma_addr;
+
+ if (tx)
+ ring = &chan_info->txq;
+ else
+ ring = &chan_info->rxq;
+ dma_addr = ring->dma;
+ if (tx) {
+ size_bwid = ilog2(chan_info->num_txq_entries);
+ hw_ops->config_mailbox_txq(p, dma_addr, size_bwid);
+ } else {
+ size_bwid = ilog2(chan_info->num_rxq_entries);
+ hw_ops->config_mailbox_rxq(p, dma_addr, size_bwid);
+ }
+}
+
+static int nbl_chan_alloc_all_tx_bufs(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_chan_ring *txq = &chan_info->txq;
+ struct device *dev = chan_mgt->common->dev;
+ struct nbl_chan_buf *buf;
+ u16 i;
+
+ for (i = 0; i < chan_info->num_txq_entries; i++) {
+ buf = &txq->buf[i];
+ buf->va = dmam_alloc_coherent(dev, chan_info->txq_buf_size,
+ &buf->pa, GFP_KERNEL);
+ if (!buf->va) {
+ dev_err(dev,
+ "Allocate buffer for chan tx queue failed\n");
+ return -ENOMEM;
+ }
+ }
+
+ txq->next_to_clean = 0;
+ txq->next_to_use = 0;
+ txq->tail_ptr = 0;
+
+ return 0;
+}
+
+static void nbl_chan_cfg_qinfo_map_table(struct nbl_channel_mgt *chan_mgt)
+{
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+ struct nbl_common_info *common = chan_mgt->common;
+ struct nbl_hw_mgt *p = chan_mgt->hw_ops_tbl->priv;
+ u8 func_id;
+ u32 pf_mask;
+
+ pf_mask = hw_ops->get_host_pf_mask(p);
+ for (func_id = 0; func_id < NBL_MAX_PF; func_id++) {
+ if (!(pf_mask & (1 << func_id)))
+ hw_ops->cfg_mailbox_qinfo(p, func_id, common->hw_bus,
+ common->devid,
+ common->function + func_id);
+ }
+}
+
+#define NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, tail_ptr, qid)\
+do { \
+ (void)(chan_info); \
+ typeof(hw_ops) _hw_ops = (hw_ops); \
+ typeof(chan_mgt) _chan_mgt = (chan_mgt); \
+ typeof(tail_ptr) _tail_ptr = (tail_ptr); \
+ typeof(qid) _qid = (qid); \
+ (_hw_ops)->update_mailbox_queue_tail_ptr( \
+ _chan_mgt->hw_ops_tbl->priv, _tail_ptr, _qid); \
+} while (0)
+
+static int nbl_chan_alloc_all_rx_bufs(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_chan_ring *rxq = &chan_info->rxq;
+ struct device *dev = chan_mgt->common->dev;
+ struct nbl_chan_rx_desc *desc;
+ struct nbl_chan_buf *buf;
+ u16 i;
+
+ for (i = 0; i < chan_info->num_rxq_entries; i++) {
+ buf = &rxq->buf[i];
+ buf->va = dmam_alloc_coherent(dev, chan_info->rxq_buf_size,
+ &buf->pa, GFP_KERNEL);
+ if (!buf->va) {
+ dev_err(dev,
+ "Allocate buffer for chan rx queue failed\n");
+ goto err;
+ }
+ }
+
+ desc = rxq->desc.rx_desc;
+ for (i = 0; i < chan_info->num_rxq_entries - 1; i++) {
+ buf = &rxq->buf[i];
+ desc[i].buf_addr = cpu_to_le64(buf->pa);
+ desc[i].buf_len = cpu_to_le32(chan_info->rxq_buf_size);
+ desc[i].flags = cpu_to_le16(BIT(NBL_CHAN_RX_DESC_AVAIL));
+ }
+
+ rxq->next_to_clean = 0;
+ rxq->next_to_use = chan_info->num_rxq_entries - 1;
+ rxq->tail_ptr = chan_info->num_rxq_entries - 1;
+
+ return 0;
+err:
+ return -ENOMEM;
+}
+
+static int nbl_chan_alloc_all_bufs(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info)
+{
+ int err;
+
+ err = nbl_chan_alloc_all_tx_bufs(chan_mgt, chan_info);
+ if (err)
+ return err;
+ err = nbl_chan_alloc_all_rx_bufs(chan_mgt, chan_info);
+
+ return err;
+}
+
+static void nbl_chan_stop_queue(struct nbl_channel_mgt *chan_mgt)
+{
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+
+ hw_ops->stop_mailbox_rxq(chan_mgt->hw_ops_tbl->priv);
+ hw_ops->stop_mailbox_txq(chan_mgt->hw_ops_tbl->priv);
+}
+
+static int nbl_chan_teardown_queue(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+ struct nbl_chan_waitqueue_head *wait_head;
+ u16 i;
+
+ /* Mark the channel as abnormal to prevent new operations */
+ set_bit(NBL_CHAN_ABNORMAL, chan_info->state);
+
+ /* Stop hardware queues */
+ nbl_chan_stop_queue(chan_mgt);
+
+ /* Cancel any pending cleanup work */
+ if (chan_info->clean_task)
+ cancel_work_sync(chan_info->clean_task);
+ /*
+ * Wake up all threads waiting for ACKs to prevent use-after-free.
+ * This is critical because these threads may be sleeping on waitqueues
+ * that will be freed when the device is detached.
+ */
+ for (i = 0; i < chan_info->num_txq_entries; i++) {
+ wait_head = &chan_info->wait[i];
+ spin_lock_irq(&wait_head->status_lock);
+ /* Only wake threads that are actually waiting */
+ if (wait_head->status == NBL_MBX_STATUS_WAITING) {
+ /* Mark as timeout so waking threads know to abort */
+ wait_head->status = NBL_MBX_STATUS_TIMEOUT;
+ wait_head->acked = 1;
+ wait_head->ack_err = -EIO;
+ /* Ensure status is written */
+ smp_wmb();
+ }
+ spin_unlock_irq(&wait_head->status_lock);
+ if (wait_head->status == NBL_MBX_STATUS_TIMEOUT)
+ wake_up(&wait_head->wait_queue);
+ }
+
+ /*
+ * Lock and unlock to ensure all in-flight callers have released the
+ * lock. After unlock returns, we're guaranteed no other thread is
+ * using the lock, so it's safe to destroy it.
+ */
+ mutex_lock(&chan_info->txq_lock);
+ mutex_unlock(&chan_info->txq_lock);
+ mutex_destroy(&chan_info->txq_lock);
+
+ return 0;
+}
+
+static int nbl_chan_setup_queue(struct nbl_channel_mgt *chan_mgt, u8 chan_type)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+ struct nbl_common_info *common = chan_mgt->common;
+ struct nbl_chan_ring *rxq = &chan_info->rxq;
+ int err;
+
+ /* Clear state from previous teardown */
+ clear_bit(NBL_CHAN_ABNORMAL, chan_info->state);
+ nbl_chan_init_queue_param(chan_info, NBL_CHAN_QUEUE_LEN,
+ NBL_CHAN_QUEUE_LEN, NBL_CHAN_BUF_LEN,
+ NBL_CHAN_BUF_LEN);
+ err = nbl_chan_init_queue(common, chan_info);
+ if (err)
+ goto chan_setup_fail;
+ err = nbl_chan_alloc_all_bufs(chan_mgt, chan_info);
+ if (err)
+ goto chan_setup_fail;
+ nbl_chan_config_queue(chan_mgt, chan_info, true); /* tx */
+ nbl_chan_config_queue(chan_mgt, chan_info, false); /* rx */
+ NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, rxq->tail_ptr,
+ NBL_MB_RX_QID);
+ return 0;
+chan_setup_fail:
+ mutex_destroy(&chan_info->txq_lock);
+ return err;
+}
+
+static int nbl_chan_update_txqueue(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info,
+ struct nbl_chan_tx_param *param)
+{
+ struct nbl_chan_ring *txq = &chan_info->txq;
+ struct nbl_chan_tx_desc *tx_desc =
+ NBL_CHAN_TX_RING_TO_DESC(txq, txq->next_to_use);
+ struct nbl_chan_buf *tx_buf =
+ NBL_CHAN_TX_RING_TO_BUF(txq, txq->next_to_use);
+
+ if (param->arg_len > NBL_CHAN_BUF_LEN - sizeof(*tx_desc))
+ return -EINVAL;
+
+ tx_desc->dstid = cpu_to_le16(param->dstid);
+ tx_desc->msg_type = cpu_to_le16(param->msg_type);
+ tx_desc->msgid = cpu_to_le16(param->msgid);
+
+ if (param->arg_len > NBL_CHAN_TX_DESC_EMBEDDED_DATA_LEN) {
+ memcpy(tx_buf->va, param->arg, param->arg_len);
+ tx_desc->buf_addr = cpu_to_le64(tx_buf->pa);
+ tx_desc->buf_len = cpu_to_le16(param->arg_len);
+ tx_desc->data_len = 0;
+ memset(tx_desc->data, 0, sizeof(tx_desc->data));
+ } else {
+ memset(tx_desc->data, 0, sizeof(tx_desc->data));
+ memcpy(tx_desc->data, param->arg, param->arg_len);
+ tx_desc->buf_len = 0;
+ tx_desc->data_len = cpu_to_le16(param->arg_len);
+ }
+ /* Ensure desc body is visible to DMA before writing AVAIL flag */
+ dma_wmb();
+ tx_desc->flags = cpu_to_le16(BIT(NBL_CHAN_TX_DESC_AVAIL));
+
+ txq->next_to_use =
+ NBL_NEXT_ID(txq->next_to_use, chan_info->num_txq_entries - 1);
+ txq->tail_ptr++;
+
+ return 0;
+}
+
+static int nbl_chan_kick_tx_ring(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+ struct nbl_chan_ring *txq = &chan_info->txq;
+ struct device *dev = chan_mgt->common->dev;
+ int max_retries = NBL_CHAN_TX_WAIT_TIMES;
+ struct nbl_chan_tx_desc *tx_desc;
+ int retry_count = 0;
+
+ NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, txq->tail_ptr,
+ NBL_MB_TX_QID);
+
+ tx_desc = NBL_CHAN_TX_RING_TO_DESC(txq, txq->next_to_clean);
+ while (retry_count < max_retries) {
+ if (le16_to_cpu(READ_ONCE(tx_desc->flags)) &
+ BIT(NBL_CHAN_TX_DESC_USED)) {
+ dma_rmb();
+ break;
+ }
+
+ retry_count++;
+ if (retry_count == max_retries) {
+ dev_err(dev, "chan send message type: %d timeout\n",
+ le16_to_cpu(READ_ONCE(tx_desc->msg_type)));
+ txq->next_to_clean = txq->next_to_use;
+ return -ETIMEDOUT;
+ }
+ usleep_range(NBL_CHAN_TX_WAIT_US, NBL_CHAN_TX_WAIT_US_MAX);
+ }
+
+ txq->next_to_clean = txq->next_to_use;
+
+ return 0;
+}
+
+static void nbl_chan_recv_ack_msg(void *priv, u16 srcid, u16 msgid, void *data,
+ u32 data_len)
+{
+ struct nbl_channel_mgt *chan_mgt = (struct nbl_channel_mgt *)priv;
+ struct nbl_chan_waitqueue_head *wait_head = NULL;
+ struct device *dev = chan_mgt->common->dev;
+ struct nbl_chan_info *chan_info =
+ chan_mgt->chan_info[NBL_CHAN_TYPE_MAILBOX];
+ u32 ack_datalen, ack_msgtype = 0;
+ u32 *payload = data;
+ u16 ack_msgid = 0;
+ u32 copy_len;
+
+ if (data_len > NBL_CHAN_BUF_LEN ||
+ data_len < NBL_CHAN_ACK_HEAD_LEN * sizeof(u32)) {
+ dev_err(dev, "Invalid ACK data_len: %u\n", data_len);
+ return;
+ }
+ ack_datalen = data_len - NBL_CHAN_ACK_HEAD_LEN * sizeof(u32);
+ ack_msgtype = le16_to_cpu(*(__le16 *)(payload + NBL_CHAN_MSG_TYPE_POS));
+ ack_msgid = le16_to_cpu(*(__le16 *)(payload + NBL_CHAN_MSG_ID_POS));
+ if (FIELD_GET(NBL_CHAN_MSGID_LOC_MASK, ack_msgid) >=
+ chan_info->num_txq_entries) {
+ dev_err(dev, "chan recv msg id: %d err\n", ack_msgid);
+ return;
+ }
+ wait_head =
+ &chan_info->wait[FIELD_GET(NBL_CHAN_MSGID_LOC_MASK, ack_msgid)];
+ spin_lock_irq(&wait_head->status_lock);
+ if (srcid != wait_head->dstid) {
+ /* Do not modify the status; the slot remains WAITING,
+ * and the sender will time out normally
+ */
+ spin_unlock_irq(&wait_head->status_lock);
+ dev_err(dev, "ACK srcid=%u != dstid=%u, rejecting\n", srcid,
+ wait_head->dstid);
+ return;
+ }
+ if (wait_head->status != NBL_MBX_STATUS_WAITING) {
+ spin_unlock_irq(&wait_head->status_lock);
+ dev_err(dev,
+ "Skip ack with invalid status, wait_head msgtype:%u msg_index:%u status:%d ack_data_len:%d, ack msgtype:%u msgid:%u datalen:%d\n",
+ wait_head->msg_type, wait_head->msg_index,
+ wait_head->status, wait_head->ack_data_len, ack_msgtype,
+ ack_msgid, ack_datalen);
+ return;
+ }
+
+ if (wait_head->msg_type != ack_msgtype) {
+ /*
+ * Mismatched ACK. Restore state to WAITING so the original
+ * sender will time out and not reuse the slot.
+ */
+ wait_head->status = NBL_MBX_STATUS_WAITING;
+
+ dev_err(dev,
+ "Skip ack msg type donot match, wait_head msgtype:%u msg_index:%u status:%d ack_data_len:%d, ack msgtype:%u msgid:%u datalen:%d\n",
+ wait_head->msg_type, wait_head->msg_index,
+ wait_head->status, wait_head->ack_data_len, ack_msgtype,
+ ack_msgid, ack_datalen);
+ spin_unlock_irq(&wait_head->status_lock);
+ /* Wake up the sender to let it know the ACK was invalid */
+ wake_up(&wait_head->wait_queue);
+ return;
+ }
+ if (FIELD_GET(NBL_CHAN_MSGID_INDEX_MASK, ack_msgid) !=
+ wait_head->msg_index) {
+ /*
+ * Stale ACK. Restore state to WAITING so the original
+ * sender will time out and not reuse the slot.
+ */
+ wait_head->status = NBL_MBX_STATUS_WAITING;
+
+ dev_err(dev,
+ "Stale ACK: expected index=%u, got msgid %u\n",
+ wait_head->msg_index, ack_msgid);
+ spin_unlock_irq(&wait_head->status_lock);
+ /* Wake up the sender to let it know the ACK was stale */
+ wake_up(&wait_head->wait_queue);
+ return;
+ }
+
+ wait_head->ack_err =
+ le32_to_cpu(*(__le32 *)(payload + NBL_CHAN_ACK_RET_POS));
+
+ copy_len = min_t(u32, wait_head->ack_data_len, ack_datalen);
+ if (wait_head->ack_err >= 0 && copy_len > 0) {
+ if (!wait_head->ack_data) {
+ dev_err(dev, "ACK payload dropped: ack_data is NULL\n");
+ wait_head->ack_data_len = 0;
+ goto ack_done;
+ }
+ memcpy((char *)wait_head->ack_data,
+ payload + NBL_CHAN_ACK_HEAD_LEN, copy_len);
+ wait_head->ack_data_len = (u16)copy_len;
+ } else {
+ wait_head->ack_data_len = 0;
+ }
+ack_done:
+ /*
+ * Ensure all writes to ack_data and ack_data_len are completed
+ * before setting the 'acked' flag. This prevents other threads
+ * from observing stale or partially updated data.
+ */
+ smp_wmb();
+ wait_head->acked = 1;
+ spin_unlock_irq(&wait_head->status_lock);
+ if (wait_head->acked)
+ wake_up(&wait_head->wait_queue);
+}
+
+static void nbl_chan_recv_msg(struct nbl_channel_mgt *chan_mgt, void *data)
+{
+ struct device *dev = chan_mgt->common->dev;
+ struct nbl_chan_msg_node_data *msg_handler;
+ u16 msg_type, payload_len, srcid, msgid;
+ struct nbl_chan_tx_desc *tx_desc;
+ void *payload;
+
+ tx_desc = data;
+ msg_type = le16_to_cpu(tx_desc->msg_type);
+ dev_dbg(dev, "recv msg_type: %d\n", msg_type);
+
+ srcid = le16_to_cpu(tx_desc->srcid);
+ msgid = le16_to_cpu(tx_desc->msgid);
+ /* Only check if the value exceeds the maximum, relying on the hash
+ * table to filter invalid message IDs.
+ * The gap values are reserved for future protocol extensions.
+ */
+ if (msg_type >= NBL_CHAN_MSG_MAILBOX_MAX)
+ return;
+
+ if (tx_desc->data_len) {
+ payload_len = le16_to_cpu(tx_desc->data_len);
+ if (payload_len > NBL_CHAN_TX_DESC_EMBEDDED_DATA_LEN) {
+ dev_err(dev,
+ "data_len=%u exceeds embedded buffer size=%u\n",
+ payload_len,
+ NBL_CHAN_TX_DESC_EMBEDDED_DATA_LEN);
+ return;
+ }
+ payload = tx_desc->data;
+ } else {
+ payload_len = le16_to_cpu(tx_desc->buf_len);
+ if (payload_len > NBL_CHAN_BUF_LEN - sizeof(*tx_desc)) {
+ dev_err(dev,
+ "buf_len=%u exceeds external buffer size=%zu\n",
+ payload_len,
+ NBL_CHAN_BUF_LEN - sizeof(*tx_desc));
+ return;
+ }
+ payload = tx_desc + 1;
+ }
+
+ msg_handler =
+ nbl_common_get_hash_node(chan_mgt->handle_hash_tbl, &msg_type);
+ if (!msg_handler || !msg_handler->func) {
+ dev_err(dev,
+ "No handler for msg_type: %u (srcid=%u, msgid=%u)\n",
+ msg_type, srcid, msgid);
+ return;
+ }
+ msg_handler->func(msg_handler->priv, srcid, msgid, payload,
+ payload_len);
+}
+
+static void nbl_chan_advance_rx_ring(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info,
+ struct nbl_chan_ring *rxq)
+{
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+ struct nbl_chan_rx_desc *rx_desc;
+ struct nbl_chan_buf *rx_buf;
+ u16 next_to_use;
+
+ next_to_use = rxq->next_to_use;
+ rx_desc = NBL_CHAN_RX_RING_TO_DESC(rxq, next_to_use);
+ rx_buf = NBL_CHAN_RX_RING_TO_BUF(rxq, next_to_use);
+
+ rx_desc->buf_addr = cpu_to_le64(rx_buf->pa);
+ rx_desc->buf_len = cpu_to_le32(chan_info->rxq_buf_size);
+
+ /*
+ * DMA Write Memory Barrier:
+ * Ensures all previous DMA-mapped writes (buffer address/length)
+ * are completed before the descriptor flags are updated.
+ * This prevents hardware from seeing a partially updated descriptor
+ * where flags are set but buffer info isn't ready yet.
+ */
+ dma_wmb();
+
+ rx_desc->flags = cpu_to_le16(BIT(NBL_CHAN_RX_DESC_AVAIL));
+
+ /*
+ * CPU Write Memory Barrier:
+ * Ensures the descriptor flags update is visible to other CPUs
+ * before we update the tail pointer. This is important for:
+ * 1. Software cleaning threads that might be checking the tail pointer
+ * 2. Maintaining proper memory ordering in multi-core systems
+ */
+ wmb();
+ rxq->next_to_use++;
+ if (rxq->next_to_use == chan_info->num_rxq_entries)
+ rxq->next_to_use = 0;
+ rxq->tail_ptr++;
+
+ NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, rxq->tail_ptr,
+ NBL_MB_RX_QID);
+}
+
+/*
+ * Since the channel operates in either polling mode or interrupt mode
+ * (mutually exclusive, configured via set_queue_state), nbl_chan_clean_queue
+ * is always called in a serialized manner:
+ * 1. In polling mode: nbl_chan_clean_queue is called directly within
+ * nbl_chan_send_msg, in the same thread after txq_lock has been released.
+ * No other thread can call it concurrently.
+ * 2. In interrupt mode: nbl_chan_clean_queue is called from a workqueue
+ * (nbl_dev_clean_mailbox_task). Linux workqueue guarantees that the same
+ * work item never runs concurrently on multiple CPUs.
+ * Therefore, at any given time, only one execution context can be inside
+ * nbl_chan_clean_queue. There is no concurrency, and thus no need for
+ * locking
+ */
+static void nbl_chan_clean_queue(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_chan_ring *rxq = &chan_info->rxq;
+ struct device *dev = chan_mgt->common->dev;
+ struct nbl_chan_rx_desc *rx_desc;
+ struct nbl_chan_buf *rx_buf;
+ u16 next_to_clean;
+
+ next_to_clean = rxq->next_to_clean;
+ rx_desc = NBL_CHAN_RX_RING_TO_DESC(rxq, next_to_clean);
+ rx_buf = NBL_CHAN_RX_RING_TO_BUF(rxq, next_to_clean);
+ while (le16_to_cpu(rx_desc->flags) & BIT(NBL_CHAN_RX_DESC_USED)) {
+ if (!(le16_to_cpu(rx_desc->flags) &
+ BIT(NBL_CHAN_RX_DESC_WRITE)))
+ dev_dbg(dev,
+ "mailbox rx flag 0x%x has no NBL_CHAN_RX_DESC_WRITE\n",
+ le16_to_cpu(rx_desc->flags));
+
+ dma_rmb();
+ nbl_chan_recv_msg(chan_mgt, rx_buf->va);
+ nbl_chan_advance_rx_ring(chan_mgt, chan_info, rxq);
+ next_to_clean++;
+ if (next_to_clean == chan_info->num_rxq_entries)
+ next_to_clean = 0;
+ rx_desc = NBL_CHAN_RX_RING_TO_DESC(rxq, next_to_clean);
+ rx_buf = NBL_CHAN_RX_RING_TO_BUF(rxq, next_to_clean);
+ }
+ rxq->next_to_clean = next_to_clean;
+}
+
+static void nbl_chan_clean_queue_subtask(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+
+ if (!test_bit(NBL_CHAN_INTERRUPT_READY, chan_info->state))
+ return;
+
+ nbl_chan_clean_queue(chan_mgt, chan_info);
+}
+
+static int nbl_chan_get_msg_id(struct nbl_chan_info *chan_info,
+ u16 *msgid)
+{
+ int valid_loc = chan_info->wait_head_index, i;
+ struct nbl_chan_waitqueue_head *wait = NULL;
+ int status;
+
+ for (i = 0; i < NBL_CHAN_QUEUE_LEN; i++) {
+ wait = &chan_info->wait[valid_loc];
+ status = wait->status;
+ if (status == NBL_MBX_STATUS_IDLE ||
+ status == NBL_MBX_STATUS_TIMEOUT) {
+ wait->msg_index = NBL_NEXT_ID(wait->msg_index,
+ NBL_CHAN_MSG_INDEX_MAX);
+ *msgid =
+ FIELD_PREP(NBL_CHAN_MSGID_INDEX_MASK,
+ wait->msg_index) |
+ FIELD_PREP(NBL_CHAN_MSGID_LOC_MASK, valid_loc);
+ valid_loc = NBL_NEXT_ID(valid_loc,
+ chan_info->num_txq_entries - 1);
+ chan_info->wait_head_index = valid_loc;
+ return 0;
+ }
+
+ valid_loc =
+ NBL_NEXT_ID(valid_loc, chan_info->num_txq_entries - 1);
+ }
+
+ /*
+ * the current NBL_CHAN_QUEUE_LEN configuration meets the design
+ * requirements and theoretically should not return errors, the
+ * following scenarios may still cause the waiting queue to
+ * become full:
+ * High-concurrency scenarios:
+ * If the sender (calling nbl_chan_send_msg()) generates messages
+ * at a rate far exceeding the receiver's ability to process
+ * acknowledgments (ACKs),the waiting queue may become fully occupied.
+ * Delayed or failed ACK handling by the receiver:
+ * The receiver may fail to send ACKs in a timely manner due to
+ * processing delays, blocking, or faults, causing the sender's
+ * waiting queue slots to remain occupied for an extended period.
+ */
+ return -EAGAIN;
+}
+
+static int nbl_chan_send_msg(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_send_info *chan_send)
+{
+ struct nbl_common_info *common = chan_mgt->common;
+ struct nbl_chan_waitqueue_head *wait_head;
+ struct nbl_chan_tx_param tx_param = { 0 };
+ u16 msgid = 0;
+ int i = NBL_CHAN_TX_WAIT_ACK_TIMES, ret;
+ struct nbl_chan_info *chan_info =
+ chan_mgt->chan_info[NBL_CHAN_TYPE_MAILBOX];
+ struct device *dev = common->dev;
+
+ if (test_bit(NBL_CHAN_ABNORMAL, chan_info->state))
+ return -EIO;
+ if (chan_send->resp_len > NBL_CHAN_BUF_LEN) {
+ dev_err(dev, "resp_len %zu exceeds max %d\n",
+ chan_send->resp_len, NBL_CHAN_BUF_LEN);
+ return -EINVAL;
+ }
+ mutex_lock(&chan_info->txq_lock);
+
+ ret = nbl_chan_get_msg_id(chan_info, &msgid);
+ if (ret) {
+ mutex_unlock(&chan_info->txq_lock);
+ dev_err(dev,
+ "Channel tx wait head full, send msgtype:%u to dstid:%u failed\n",
+ chan_send->msg_type, chan_send->dstid);
+ return ret;
+ }
+
+ tx_param.msg_type = chan_send->msg_type;
+ tx_param.arg = chan_send->arg;
+ tx_param.arg_len = chan_send->arg_len;
+ tx_param.dstid = chan_send->dstid;
+ tx_param.msgid = msgid;
+
+ ret = nbl_chan_update_txqueue(chan_mgt, chan_info, &tx_param);
+ if (ret) {
+ mutex_unlock(&chan_info->txq_lock);
+ dev_err(dev,
+ "Channel tx queue full, send msgtype:%u to dstid:%u failed\n",
+ chan_send->msg_type, chan_send->dstid);
+ return ret;
+ }
+
+ wait_head =
+ &chan_info->wait[FIELD_GET(NBL_CHAN_MSGID_LOC_MASK, msgid)];
+ spin_lock_irq(&wait_head->status_lock);
+ wait_head->acked = 0;
+ wait_head->ack_data = chan_send->resp;
+ wait_head->ack_data_len = chan_send->resp_len;
+ wait_head->msg_type = chan_send->msg_type;
+ wait_head->msg_index = FIELD_GET(NBL_CHAN_MSGID_INDEX_MASK, msgid);
+ wait_head->dstid = chan_send->dstid;
+ /* Ensure all fields above are visible before status update, so receiver
+ * won't see WAITING with stale data
+ */
+ smp_wmb();
+ wait_head->status = chan_send->ack ? NBL_MBX_STATUS_WAITING :
+ NBL_MBX_STATUS_IDLE;
+ spin_unlock_irq(&wait_head->status_lock);
+
+ ret = nbl_chan_kick_tx_ring(chan_mgt, chan_info);
+ mutex_unlock(&chan_info->txq_lock);
+ if (ret) {
+ mutex_lock(&chan_info->txq_lock);
+ spin_lock_irq(&wait_head->status_lock);
+ wait_head->status = NBL_MBX_STATUS_TIMEOUT;
+ spin_unlock_irq(&wait_head->status_lock);
+ mutex_unlock(&chan_info->txq_lock);
+ return ret;
+ }
+
+ if (!chan_send->ack)
+ return 0;
+
+ if (test_bit(NBL_CHAN_INTERRUPT_READY, chan_info->state)) {
+ spin_lock_irq(&wait_head->status_lock);
+ while (!wait_head->acked) {
+ spin_unlock_irq(&wait_head->status_lock);
+ ret = wait_event_timeout(wait_head->wait_queue,
+ wait_head->acked,
+ NBL_CHAN_ACK_WAIT_TIME);
+ spin_lock_irq(&wait_head->status_lock);
+
+ if (ret == 0) {
+ if (wait_head->status ==
+ NBL_MBX_STATUS_WAITING) {
+ wait_head->status =
+ NBL_MBX_STATUS_TIMEOUT;
+ wait_head->acked = 0;
+ wait_head->ack_data = NULL;
+ wait_head->ack_data_len = 0;
+ }
+ spin_unlock_irq(&wait_head->status_lock);
+ dev_err(dev,
+ "Channel waiting ack failed, message type: %d, msg id: %u\n",
+ chan_send->msg_type, msgid);
+ return -ETIMEDOUT;
+ }
+
+ if (wait_head->acked)
+ break;
+ }
+ /*
+ * ensure that after observing 'acked == 1', all
+ * subsequent reads (ack_data_len, ack_err) observe
+ * the latest values written by the sender
+ * (nbl_chan_recv_ack_msg()). This prevents stale reads
+ * of ACK data or status.
+ */
+ smp_rmb();
+ chan_send->ack_len = wait_head->ack_data_len;
+ ret = wait_head->ack_err;
+ wait_head->acked = 0;
+ wait_head->status = NBL_MBX_STATUS_IDLE;
+ spin_unlock_irq(&wait_head->status_lock);
+
+ return ret;
+ }
+
+ /*
+ * Polling mode is only used during init and deinit, when interrupt
+ * mode is disabled.At that point, the channel is not yet in service
+ * (init) or already being torn down (deinit), so there is no
+ * concurrent traffic and no other caller can enter the polling loop.
+ */
+ /*polling wait mailbox ack*/
+
+ while (i--) {
+ nbl_chan_clean_queue(chan_mgt, chan_info);
+
+ spin_lock_irq(&wait_head->status_lock);
+ if (wait_head->acked) {
+ /*
+ * ensure that after observing 'acked == 1', all
+ * subsequent reads (ack_data_len, ack_err) observe
+ * the latest values written by the sender
+ * (nbl_chan_recv_ack_msg()). This prevents stale reads
+ * of ACK data or status.
+ */
+ smp_rmb();
+ chan_send->ack_len = wait_head->ack_data_len;
+ ret = wait_head->ack_err;
+ wait_head->acked = 0;
+ wait_head->status = NBL_MBX_STATUS_IDLE;
+ spin_unlock_irq(&wait_head->status_lock);
+ return ret;
+ }
+ spin_unlock_irq(&wait_head->status_lock);
+
+ usleep_range(NBL_CHAN_TX_WAIT_ACK_US_MIN,
+ NBL_CHAN_TX_WAIT_ACK_US_MAX);
+ }
+
+ spin_lock_irq(&wait_head->status_lock);
+ wait_head->acked = 0;
+ wait_head->status = NBL_MBX_STATUS_TIMEOUT;
+ spin_unlock_irq(&wait_head->status_lock);
+
+ dev_err(dev,
+ "Channel polling ack failed, message type: %d msg id: %u\n",
+ chan_send->msg_type, msgid);
+ return -ETIMEDOUT;
+}
+
+static int nbl_chan_send_ack(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_ack_info *chan_ack)
+{
+ size_t head_len = NBL_CHAN_ACK_HEAD_LEN * sizeof(u32);
+ size_t data_len = chan_ack->data_len;
+ struct nbl_chan_send_info chan_send;
+ __le32 *tmp;
+ size_t len;
+ int ret;
+
+ if (data_len >
+ NBL_CHAN_BUF_LEN - sizeof(struct nbl_chan_tx_desc) - head_len)
+ return -EINVAL;
+
+ len = head_len + data_len;
+ tmp = kzalloc(len, GFP_KERNEL);
+ if (!tmp)
+ return -ENOMEM;
+
+ *(__le16 *)&tmp[NBL_CHAN_MSG_TYPE_POS] =
+ cpu_to_le16(chan_ack->msg_type);
+ *(__le16 *)&tmp[NBL_CHAN_MSG_ID_POS] = cpu_to_le16(chan_ack->msgid);
+ tmp[NBL_CHAN_ACK_RET_POS] = cpu_to_le32(chan_ack->err);
+ if (chan_ack->data && chan_ack->data_len)
+ memcpy(&tmp[NBL_CHAN_ACK_HEAD_LEN], chan_ack->data,
+ chan_ack->data_len);
+
+ NBL_CHAN_SEND(chan_send, chan_ack->dstid, NBL_CHAN_MSG_ACK, tmp, len,
+ NULL, 0, 0);
+ ret = nbl_chan_send_msg(chan_mgt, &chan_send);
+ kfree(tmp);
+
+ return ret;
+}
+
+static int nbl_chan_register_msg(struct nbl_channel_mgt *chan_mgt, u16 msg_type,
+ nbl_chan_resp func, void *callback)
+{
+ return nbl_chan_add_msg_handler(chan_mgt, msg_type, func, callback);
+}
+
+static bool nbl_chan_check_queue_exist(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+
+ return chan_info ? true : false;
+}
+
+static void nbl_chan_register_chan_task(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type, struct work_struct *task)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+
+ chan_info->clean_task = task;
+}
+
+static void nbl_chan_set_queue_state(struct nbl_channel_mgt *chan_mgt,
+ enum nbl_chan_state state, u8 chan_type,
+ u8 set)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+
+ if (set)
+ set_bit(state, chan_info->state);
+ else
+ clear_bit(state, chan_info->state);
+}
+
static struct nbl_channel_ops chan_ops = {
+ .send_msg = nbl_chan_send_msg,
+ .send_ack = nbl_chan_send_ack,
+ .register_msg = nbl_chan_register_msg,
+ .cfg_chan_qinfo_map_table = nbl_chan_cfg_qinfo_map_table,
+ .check_queue_exist = nbl_chan_check_queue_exist,
+ .setup_queue = nbl_chan_setup_queue,
+ .teardown_queue = nbl_chan_teardown_queue,
+ .clean_queue_subtask = nbl_chan_clean_queue_subtask,
+ .register_chan_task = nbl_chan_register_chan_task,
+ .set_queue_state = nbl_chan_set_queue_state,
};
static struct nbl_channel_mgt *
@@ -18,6 +987,7 @@ nbl_chan_setup_chan_mgt(struct nbl_adapter *adapter)
struct device *dev = &adapter->pdev->dev;
struct nbl_channel_mgt *chan_mgt;
struct nbl_chan_info *mailbox;
+ int ret;
chan_mgt = devm_kzalloc(dev, sizeof(*chan_mgt), GFP_KERNEL);
if (!chan_mgt)
@@ -32,6 +1002,10 @@ nbl_chan_setup_chan_mgt(struct nbl_adapter *adapter)
mailbox->chan_type = NBL_CHAN_TYPE_MAILBOX;
chan_mgt->chan_info[NBL_CHAN_TYPE_MAILBOX] = mailbox;
+ ret = nbl_chan_init_msg_handler(chan_mgt);
+ if (ret)
+ return ERR_PTR(-ENOMEM);
+
return chan_mgt;
}
@@ -39,6 +1013,7 @@ static struct nbl_channel_ops_tbl *
nbl_chan_setup_ops(struct device *dev, struct nbl_channel_mgt *chan_mgt)
{
struct nbl_channel_ops_tbl *chan_ops_tbl;
+ int ret;
chan_ops_tbl = devm_kzalloc(dev, sizeof(*chan_ops_tbl), GFP_KERNEL);
if (!chan_ops_tbl)
@@ -47,6 +1022,11 @@ nbl_chan_setup_ops(struct device *dev, struct nbl_channel_mgt *chan_mgt)
chan_ops_tbl->ops = &chan_ops;
chan_ops_tbl->priv = chan_mgt;
+ ret = nbl_chan_register_msg(chan_mgt, NBL_CHAN_MSG_ACK,
+ nbl_chan_recv_ack_msg, chan_mgt);
+ if (ret)
+ return ERR_PTR(-ENOMEM);
+
return chan_ops_tbl;
}
@@ -60,19 +1040,39 @@ int nbl_chan_init_common(struct nbl_adapter *adap)
chan_mgt = nbl_chan_setup_chan_mgt(adap);
if (IS_ERR(chan_mgt)) {
ret = PTR_ERR(chan_mgt);
- return ret;
+ goto exit;
}
chan_ops_tbl = nbl_chan_setup_ops(dev, chan_mgt);
if (IS_ERR(chan_ops_tbl)) {
ret = PTR_ERR(chan_ops_tbl);
- return ret;
+ goto exit;
}
adap->intf.channel_ops_tbl = chan_ops_tbl;
adap->core.chan_mgt = chan_mgt;
return 0;
+
+exit:
+ if (!IS_ERR(chan_mgt)) {
+ nbl_chan_remove_msg_handler(chan_mgt);
+ adap->core.chan_mgt = NULL;
+ }
+ return ret;
}
void nbl_chan_remove_common(struct nbl_adapter *adap)
{
+ struct nbl_channel_mgt *chan_mgt = adap->core.chan_mgt;
+
+ if (chan_mgt) {
+ nbl_chan_remove_msg_handler(chan_mgt);
+ adap->core.chan_mgt = NULL;
+ }
+ /*
+ * Note: nbl_chan_remove_common() does not call teardown_queue() here.
+ * The work cancellation (cancel_work_sync) is already handled in
+ * nbl_dev_remove() -> nbl_dev_remove_common_dev()
+ * -> nbl_dev_remove_chan_queue()-> teardown_queue(),
+ * which is guaranteed to be called before this function.
+ */
}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h
index 637912d1e806..01e1a56ef0d1 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h
@@ -15,10 +15,147 @@
#include "../nbl_include/nbl_def_common.h"
#include "../nbl_core.h"
+#define NBL_CHAN_TX_RING_TO_DESC(tx_ring, i) \
+ (&((((tx_ring)->desc.tx_desc))[i]))
+#define NBL_CHAN_RX_RING_TO_DESC(rx_ring, i) \
+ (&((((rx_ring)->desc.rx_desc))[i]))
+#define NBL_CHAN_TX_RING_TO_BUF(tx_ring, i) (&(((tx_ring)->buf)[i]))
+#define NBL_CHAN_RX_RING_TO_BUF(rx_ring, i) (&(((rx_ring)->buf)[i]))
+
+#define NBL_CHAN_TX_WAIT_US 100
+#define NBL_CHAN_TX_WAIT_US_MAX 120
+#define NBL_CHAN_TX_WAIT_TIMES 100
+#define NBL_CHAN_TX_WAIT_ACK_US_MIN 100
+#define NBL_CHAN_TX_WAIT_ACK_US_MAX 120
+#define NBL_CHAN_TX_WAIT_ACK_TIMES 50000
+#define NBL_CHAN_QUEUE_LEN 256
+#define NBL_CHAN_CLEAN_BATCH_SIZE 32
+#define NBL_CHAN_BUF_LEN 4096
+#define NBL_CHAN_TX_DESC_EMBEDDED_DATA_LEN 16
+
+#define NBL_CHAN_TX_DESC_AVAIL 0
+#define NBL_CHAN_TX_DESC_USED 1
+#define NBL_CHAN_RX_DESC_WRITE 1
+#define NBL_CHAN_RX_DESC_AVAIL 3
+#define NBL_CHAN_RX_DESC_USED 4
+
+#define NBL_CHAN_ACK_HEAD_LEN 3
+#define NBL_CHAN_ACK_RET_POS 2
+#define NBL_CHAN_MSG_ID_POS 1
+#define NBL_CHAN_MSG_TYPE_POS 0
+
+#define NBL_CHAN_ACK_WAIT_TIME (3 * HZ)
+
+#define NBL_CHAN_HANDLER_TBL_BUCKET_SIZE 512
+
+enum {
+ NBL_MB_RX_QID = 0,
+ NBL_MB_TX_QID = 1,
+};
+
+enum {
+ NBL_MBX_STATUS_IDLE = 0,
+ NBL_MBX_STATUS_WAITING,
+ NBL_MBX_STATUS_TIMEOUT,
+};
+
+struct nbl_chan_tx_param {
+ enum nbl_chan_msg_type msg_type;
+ void *arg;
+ size_t arg_len;
+ u16 dstid;
+ u16 msgid;
+};
+
+struct nbl_chan_buf {
+ void *va;
+ dma_addr_t pa;
+ size_t size;
+};
+
+struct nbl_chan_tx_desc {
+ __le16 flags;
+ __le16 srcid;
+ __le16 dstid;
+ __le16 data_len;
+ __le16 buf_len;
+ __le64 buf_addr;
+ __le16 msg_type;
+ u8 data[16];
+ __le16 msgid;
+ u8 rsv[26];
+} __packed;
+
+struct nbl_chan_rx_desc {
+ __le16 flags;
+ __le32 buf_len;
+ __le16 buf_id;
+ __le64 buf_addr;
+} __packed;
+
+union nbl_chan_desc_ptr {
+ struct nbl_chan_tx_desc *tx_desc;
+ struct nbl_chan_rx_desc *rx_desc;
+};
+
+struct nbl_chan_ring {
+ union nbl_chan_desc_ptr desc;
+ struct nbl_chan_buf *buf;
+ u16 next_to_use;
+ u16 tail_ptr;
+ u16 next_to_clean;
+ dma_addr_t dma;
+};
+
+#define NBL_CHAN_MSG_INDEX_MAX 63
+
+#define NBL_CHAN_MSGID_INDEX_MASK GENMASK(5, 0)
+#define NBL_CHAN_MSGID_LOC_MASK GENMASK(13, 6)
+
+struct nbl_chan_waitqueue_head {
+ struct wait_queue_head wait_queue;
+ char *ack_data;
+ int acked;
+ int ack_err;
+ u16 ack_data_len;
+ u16 msg_type;
+ /*
+ * Spinlock protecting all fields.
+ * Must be held when reading/writing: status, acked, ack_err,
+ * ack_data_len, etc.
+ * The lock ensures atomic updates of these fields and
+ * proper memory ordering with smp_wmb()/smp_rmb().
+ */
+ spinlock_t status_lock;
+ int status;
+ u8 msg_index;
+ u16 dstid;
+};
+
struct nbl_chan_info {
+ struct nbl_chan_ring txq;
+ struct nbl_chan_ring rxq;
+ struct nbl_chan_waitqueue_head *wait;
+ /*
+ *Protects access to the TX queue (txq) and related metadata.
+ *This mutex ensures exclusive access when updating the TX queue
+ */
+ struct mutex txq_lock;
+ struct work_struct *clean_task;
+ u16 wait_head_index;
+ u16 num_txq_entries;
+ u16 num_rxq_entries;
+ u16 txq_buf_size;
+ u16 rxq_buf_size;
+ DECLARE_BITMAP(state, NBL_CHAN_STATE_NBITS);
u8 chan_type;
};
+struct nbl_chan_msg_node_data {
+ nbl_chan_resp func;
+ void *priv;
+};
+
struct nbl_channel_mgt {
struct nbl_common_info *common;
struct nbl_hw_ops_tbl *hw_ops_tbl;
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c
new file mode 100644
index 000000000000..2954cbbe0f95
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#include <linux/device.h>
+#include "nbl_common.h"
+
+u32 nbl_common_pf_id_subtraction_mgtpf_id(struct nbl_common_info *common,
+ u32 pf_id)
+{
+ u32 diff = U32_MAX;
+
+ if (pf_id >= common->mgt_pf)
+ diff = pf_id - common->mgt_pf;
+
+ return diff;
+}
+
+#define FNV_PRIME_32 0x01000193
+#define FNV_OFFSET_32 0x811C9DC5
+static u32 nbl_common_calc_hash_key(void *key, u32 key_size, u32 bucket_size)
+{
+ u32 hash = FNV_OFFSET_32;
+ u8 *p = (u8 *)key;
+ u32 i;
+
+ if (bucket_size == 0 || bucket_size == NBL_HASH_TBL_LIST_BUCKET_SIZE)
+ return 0;
+
+ for (i = 0; i < key_size; i++) {
+ hash ^= p[i];
+ hash *= FNV_PRIME_32;
+ }
+ /* Use bitmask if bucket_size is a power of 2 */
+ if ((bucket_size & (bucket_size - 1)) == 0)
+ return hash & (bucket_size - 1);
+ else
+ return hash % bucket_size;
+}
+
+/*
+ * alloc a hash table
+ * the table support multi thread
+ */
+struct nbl_hash_tbl_mgt *
+nbl_common_init_hash_table(struct nbl_hash_tbl_key *key)
+{
+ struct nbl_hash_tbl_mgt *tbl_mgt;
+ int bucket_size;
+ int i;
+
+ tbl_mgt = devm_kzalloc(key->dev, sizeof(*tbl_mgt), GFP_KERNEL);
+ if (!tbl_mgt)
+ return NULL;
+
+ bucket_size = key->bucket_size;
+ tbl_mgt->hash = devm_kcalloc(key->dev, bucket_size,
+ sizeof(struct hlist_head), GFP_KERNEL);
+ if (!tbl_mgt->hash)
+ goto alloc_hash_failed;
+
+ for (i = 0; i < bucket_size; i++)
+ INIT_HLIST_HEAD(tbl_mgt->hash + i);
+
+ memcpy(&tbl_mgt->tbl_key, key, sizeof(struct nbl_hash_tbl_key));
+
+ return tbl_mgt;
+
+alloc_hash_failed:
+ return NULL;
+}
+
+/*
+ * Allocate a hash node and add to the hash table.
+ *
+ * Note: The hash table is protected by the caller's mutex (txq_lock),
+ * not lock-free. The "single context" comment in nbl_common_alloc_hash_node
+ * refers to: this function is only called during init from
+ * nbl_chan_init_msg_handler, so there is no concurrent mutation during init.
+ * After init, the table is read-only (no unregister API), so no lock is needed
+ * for lookups either.
+ *
+ * The tbl_mgt and bucket array are devm-allocated, so they are automatically
+ * freed on device detach. Only the hash nodes themselves need explicit cleanup.
+ */
+int nbl_common_alloc_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key,
+ void *data, void **out_data)
+{
+ struct nbl_hash_entry_node *hash_node;
+ u16 data_size;
+ u32 hash_val;
+ u16 key_size;
+
+ hash_node = devm_kzalloc(tbl_mgt->tbl_key.dev, sizeof(*hash_node),
+ GFP_KERNEL);
+ if (!hash_node)
+ return -ENOMEM;
+
+ key_size = tbl_mgt->tbl_key.key_size;
+ hash_node->key =
+ devm_kzalloc(tbl_mgt->tbl_key.dev, key_size, GFP_KERNEL);
+ if (!hash_node->key)
+ goto alloc_key_failed;
+
+ data_size = tbl_mgt->tbl_key.data_size;
+ hash_node->data =
+ devm_kzalloc(tbl_mgt->tbl_key.dev, data_size, GFP_KERNEL);
+ if (!hash_node->data)
+ goto alloc_data_failed;
+
+ memcpy(hash_node->key, key, key_size);
+ memcpy(hash_node->data, data, data_size);
+
+ hash_val = nbl_common_calc_hash_key(key, key_size,
+ tbl_mgt->tbl_key.bucket_size);
+
+ hlist_add_head(&hash_node->node, tbl_mgt->hash + hash_val);
+ tbl_mgt->node_num++;
+ if (out_data)
+ *out_data = hash_node->data;
+
+ return 0;
+
+alloc_data_failed:
+ devm_kfree(tbl_mgt->tbl_key.dev, hash_node->key);
+alloc_key_failed:
+ devm_kfree(tbl_mgt->tbl_key.dev, hash_node);
+ return -ENOMEM;
+}
+
+/*
+ * get a hash node, return the data if node exist
+ */
+void *nbl_common_get_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key)
+{
+ struct nbl_hash_entry_node *hash_node;
+ struct hlist_head *head;
+ void *data = NULL;
+ u32 hash_val;
+ u16 key_size;
+
+ key_size = tbl_mgt->tbl_key.key_size;
+ hash_val = nbl_common_calc_hash_key(key, key_size,
+ tbl_mgt->tbl_key.bucket_size);
+ head = tbl_mgt->hash + hash_val;
+
+ hlist_for_each_entry(hash_node, head, node)
+ if (!memcmp(hash_node->key, key, key_size)) {
+ data = hash_node->data;
+ break;
+ }
+
+ return data;
+}
+
+static void nbl_common_detach_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt,
+ struct nbl_hash_entry_node *hash_node)
+{
+ hlist_del(&hash_node->node);
+ devm_kfree(tbl_mgt->tbl_key.dev, hash_node->key);
+ devm_kfree(tbl_mgt->tbl_key.dev, hash_node->data);
+ devm_kfree(tbl_mgt->tbl_key.dev, hash_node);
+ tbl_mgt->node_num--;
+}
+
+/*
+ * Free all hash nodes in the table.
+ *
+ * Note: This function only frees the per-node allocations (key/data/node).
+ * The table skeleton (tbl_mgt + bucket array) is devm-allocated and will be
+ * automatically released by the devm framework on device detach. No need
+ * to free them here.
+ */
+void nbl_common_remove_hash_table(struct nbl_hash_tbl_mgt *tbl_mgt,
+ struct nbl_hash_tbl_del_key *key)
+{
+ struct nbl_hash_entry_node *hash_node;
+ struct hlist_node *safe_node;
+ struct hlist_head *head;
+ u32 i;
+
+ for (i = 0; i < tbl_mgt->tbl_key.bucket_size; i++) {
+ head = tbl_mgt->hash + i;
+ hlist_for_each_entry_safe(hash_node, safe_node, head, node) {
+ if (key && key->action_func)
+ key->action_func(key->action_priv,
+ hash_node->key,
+ hash_node->data);
+ nbl_common_detach_hash_node(tbl_mgt, hash_node);
+ }
+ }
+}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h
new file mode 100644
index 000000000000..7a91d4eca105
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_COMMON_H_
+#define _NBL_COMMON_H_
+
+#include <linux/types.h>
+
+#include "../nbl_include/nbl_include.h"
+#include "../nbl_include/nbl_def_common.h"
+
+/* list only need one bucket size */
+#define NBL_HASH_TBL_LIST_BUCKET_SIZE 1
+
+struct nbl_common_wq_mgt {
+ struct workqueue_struct *ctrl_dev_wq;
+};
+
+struct nbl_hash_tbl_mgt {
+ struct nbl_hash_tbl_key tbl_key;
+ struct hlist_head *hash;
+ u16 node_num;
+};
+
+struct nbl_hash_entry_node {
+ struct hlist_node node;
+ void *key;
+ void *data;
+};
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
index 08ddbf5b0eb2..1d25d7770d8d 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
@@ -7,9 +7,153 @@
#include <linux/bits.h>
#include <linux/io.h>
#include <linux/spinlock.h>
+#include <linux/bitfield.h>
#include "nbl_hw_leonis.h"
+static void nbl_hw_write_mbx_regs(struct nbl_hw_mgt *hw_mgt, u64 reg,
+ const u32 *data, u32 len)
+{
+ u32 i;
+
+ if (len % 4)
+ return;
+
+ for (i = 0; i < len / 4; i++)
+ nbl_mbx_wr32(hw_mgt, reg + i * sizeof(u32), data[i]);
+}
+
+static void nbl_hw_rd_regs(struct nbl_hw_mgt *hw_mgt, u64 reg, u32 *data,
+ u32 len)
+{
+ u32 size = len / 4;
+ u32 i;
+
+ if (len % 4)
+ return;
+
+ spin_lock(&hw_mgt->reg_lock);
+
+ for (i = 0; i < size; i++)
+ data[i] = rd32(hw_mgt->hw_addr, reg + i * sizeof(u32));
+ spin_unlock(&hw_mgt->reg_lock);
+}
+
+static void nbl_hw_wr_regs(struct nbl_hw_mgt *hw_mgt, u64 reg, const u32 *data,
+ u32 len)
+{
+ u32 size = len / 4;
+ u32 i;
+
+ if (len % 4)
+ return;
+ spin_lock(&hw_mgt->reg_lock);
+ for (i = 0; i < size; i++)
+ wr32(hw_mgt->hw_addr, reg + i * sizeof(u32), data[i]);
+ spin_unlock(&hw_mgt->reg_lock);
+}
+
+static void nbl_hw_update_mailbox_queue_tail_ptr(struct nbl_hw_mgt *hw_mgt,
+ u16 tail_ptr, u8 txrx)
+{
+ /* local_qid 0 and 1 denote rx and tx queue respectively */
+ u32 local_qid = txrx;
+ u32 value = ((u32)tail_ptr << 16) | local_qid;
+
+ /* wmb for doorbell */
+ wmb();
+ nbl_mbx_wr32(hw_mgt, NBL_MAILBOX_NOTIFY_ADDR, value);
+}
+
+static void nbl_hw_config_mailbox_rxq(struct nbl_hw_mgt *hw_mgt,
+ dma_addr_t dma_addr, int size_bwid)
+{
+ struct nbl_mailbox_qinfo_cfg_table cfg_tbl;
+
+ memset(&cfg_tbl, 0, sizeof(cfg_tbl));
+ cfg_tbl.data[3] = FIELD_PREP(NBL_MAILBOX_QINFO_CFG_QUEUE_RST_MASK, 1);
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR,
+ cfg_tbl.data, sizeof(cfg_tbl));
+
+ cfg_tbl.data[0] = lower_32_bits(dma_addr);
+ cfg_tbl.data[1] = upper_32_bits(dma_addr);
+ cfg_tbl.data[2] = FIELD_PREP(NBL_MAILBOX_QINFO_CFG_QUEUE_SIZE_BWID_MASK,
+ size_bwid);
+ cfg_tbl.data[3] = FIELD_PREP(NBL_MAILBOX_QINFO_CFG_QUEUE_RST_MASK, 0) |
+ FIELD_PREP(NBL_MAILBOX_QINFO_CFG_QUEUE_EN_MASK, 1);
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR,
+ cfg_tbl.data, sizeof(cfg_tbl));
+}
+
+static void nbl_hw_config_mailbox_txq(struct nbl_hw_mgt *hw_mgt,
+ dma_addr_t dma_addr, int size_bwid)
+{
+ struct nbl_mailbox_qinfo_cfg_table cfg_tbl;
+
+ memset(&cfg_tbl, 0, sizeof(cfg_tbl));
+ cfg_tbl.data[3] = FIELD_PREP(NBL_MAILBOX_QINFO_CFG_QUEUE_RST_MASK, 1);
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR,
+ cfg_tbl.data, sizeof(cfg_tbl));
+
+ cfg_tbl.data[0] = lower_32_bits(dma_addr);
+ cfg_tbl.data[1] = upper_32_bits(dma_addr);
+ cfg_tbl.data[2] = FIELD_PREP(NBL_MAILBOX_QINFO_CFG_QUEUE_SIZE_BWID_MASK,
+ size_bwid);
+ cfg_tbl.data[3] = FIELD_PREP(NBL_MAILBOX_QINFO_CFG_QUEUE_RST_MASK, 0) |
+ FIELD_PREP(NBL_MAILBOX_QINFO_CFG_QUEUE_EN_MASK, 1);
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR,
+ cfg_tbl.data, sizeof(cfg_tbl));
+}
+
+static void nbl_hw_stop_mailbox_rxq(struct nbl_hw_mgt *hw_mgt)
+{
+ struct nbl_mailbox_qinfo_cfg_table cfg_tbl;
+
+ memset(&cfg_tbl, 0, sizeof(cfg_tbl));
+ cfg_tbl.data[3] = FIELD_PREP(NBL_MAILBOX_QINFO_CFG_QUEUE_RST_MASK, 1);
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR,
+ cfg_tbl.data, sizeof(cfg_tbl));
+}
+
+static void nbl_hw_stop_mailbox_txq(struct nbl_hw_mgt *hw_mgt)
+{
+ struct nbl_mailbox_qinfo_cfg_table cfg_tbl;
+
+ memset(&cfg_tbl, 0, sizeof(cfg_tbl));
+ cfg_tbl.data[3] = FIELD_PREP(NBL_MAILBOX_QINFO_CFG_QUEUE_RST_MASK, 1);
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR,
+ cfg_tbl.data, sizeof(cfg_tbl));
+}
+
+static u32 nbl_hw_get_host_pf_mask(struct nbl_hw_mgt *hw_mgt)
+{
+ u32 data;
+
+ nbl_hw_rd_regs(hw_mgt, NBL_PCIE_HOST_K_PF_MASK_REG, &data,
+ sizeof(data));
+ return data;
+}
+
+static void nbl_hw_cfg_mailbox_qinfo(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ u8 bus, u8 devid, u8 function)
+{
+ u32 data = 0;
+
+ data = FIELD_PREP(NBL_MAILBOX_QINFO_MAP_FUNCTION_MASK, function) |
+ FIELD_PREP(NBL_MAILBOX_QINFO_MAP_DEVID_MASK, devid) |
+ FIELD_PREP(NBL_MAILBOX_QINFO_MAP_BUS_MASK, bus);
+ nbl_hw_wr_regs(hw_mgt, NBL_MAILBOX_QINFO_MAP_REG_ARR(func_id), &data,
+ sizeof(data));
+}
+
static struct nbl_hw_ops hw_ops = {
+ .update_mailbox_queue_tail_ptr = nbl_hw_update_mailbox_queue_tail_ptr,
+ .config_mailbox_rxq = nbl_hw_config_mailbox_rxq,
+ .config_mailbox_txq = nbl_hw_config_mailbox_txq,
+ .stop_mailbox_rxq = nbl_hw_stop_mailbox_rxq,
+ .stop_mailbox_txq = nbl_hw_stop_mailbox_txq,
+ .get_host_pf_mask = nbl_hw_get_host_pf_mask,
+ .cfg_mailbox_qinfo = nbl_hw_cfg_mailbox_qinfo,
+
};
/* Structure starts here, adding an op should not modify anything below */
@@ -105,6 +249,8 @@ int nbl_hw_init_leonis(struct nbl_adapter *adapter)
goto mailbox_ioremap_err;
}
+ spin_lock_init(&hw_mgt->reg_lock);
+
hw_ops_tbl = nbl_hw_setup_ops(common, hw_mgt);
if (IS_ERR(hw_ops_tbl)) {
ret = PTR_ERR(hw_ops_tbl);
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
index a554900d9ca6..d2c85175554d 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
@@ -12,4 +12,61 @@
#include "../nbl_hw_reg.h"
#define NBL_BYTES_IN_REG 4
+
+/* ---------- REG BASE ADDR ---------- */
+/* Interface modules base addr */
+#define NBL_INTF_HOST_PCOMPLETER_BASE 0x00f08000
+#define NBL_INTF_HOST_PADPT_BASE 0x00f4c000
+#define NBL_INTF_HOST_MAILBOX_BASE 0x00fb0000
+#define NBL_INTF_HOST_PCIE_BASE 0X01504000
+/* DP modules base addr */
+#define NBL_DP_USTORE_BASE 0x00104000
+#define NBL_DP_UQM_BASE 0x00114000
+#define NBL_DP_UPED_BASE 0x0015c000
+#define NBL_DP_UVN_BASE 0x00244000
+#define NBL_DP_DSCH_BASE 0x00404000
+#define NBL_DP_SHAPING_BASE 0x00504000
+#define NBL_DP_DVN_BASE 0x00514000
+#define NBL_DP_DSTORE_BASE 0x00704000
+#define NBL_DP_DQM_BASE 0x00714000
+#define NBL_DP_DPED_BASE 0x0075c000
+#define NBL_DP_DDMUX_BASE 0x00984000
+/* -------- MAILBOX BAR2 ----- */
+#define NBL_MAILBOX_NOTIFY_ADDR 0x00000000
+#define NBL_MAILBOX_BAR_REG 0x00000000
+#define NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR 0x10
+#define NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR 0x20
+#define NBL_MAILBOX_QINFO_CFG_DBG_TABLE_ADDR 0x30
+
+/* -------- MAILBOX -------- */
+
+/* mailbox BAR qinfo_cfg_table */
+#define MAILBOX_QINFO_CFG_TABLE_DWLEN 4
+/* data[2] */
+#define NBL_MAILBOX_QINFO_CFG_QUEUE_SIZE_BWID_MASK GENMASK(3, 0)
+/* data[3] */
+#define NBL_MAILBOX_QINFO_CFG_QUEUE_RST_MASK BIT(0)
+#define NBL_MAILBOX_QINFO_CFG_QUEUE_EN_MASK BIT(1)
+#define NBL_MAILBOX_QINFO_CFG_DIF_ERR_MASK BIT(2)
+#define NBL_MAILBOX_QINFO_CFG_PTR_ERR_MASK BIT(3)
+struct nbl_mailbox_qinfo_cfg_table {
+ u32 data[MAILBOX_QINFO_CFG_TABLE_DWLEN];
+};
+
+/* -------- MAILBOX BAR0 ----- */
+/* mailbox qinfo_map_table */
+#define NBL_MAILBOX_QINFO_MAP_REG_ARR(func_id) \
+ (NBL_INTF_HOST_MAILBOX_BASE + 0x00001000 + (func_id) * sizeof(u32))
+
+/* MAILBOX qinfo_map_table */
+#define NBL_MAILBOX_QINFO_MAP_FUNCTION_MASK GENMASK(2, 0)
+#define NBL_MAILBOX_QINFO_MAP_DEVID_MASK GENMASK(7, 3)
+#define NBL_MAILBOX_QINFO_MAP_BUS_MASK GENMASK(15, 8)
+#define NBL_MAILBOX_QINFO_MAP_MSIX_IDX_MASK GENMASK(28, 16)
+#define NBL_MAILBOX_QINFO_MAP_MSIX_IDX_VALID_MASK BIT(29)
+
+/* -------- HOST_PCIE -------- */
+#define NBL_PCIE_HOST_K_PF_MASK_REG (NBL_INTF_HOST_PCIE_BASE + 0x00001004)
+#define NBL_PCIE_HOST_TL_CFG_BUSDEV (NBL_INTF_HOST_PCIE_BASE + 0x11040)
+
#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h
index 1828251e8c2a..18f3fa078758 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h
@@ -26,6 +26,7 @@ struct nbl_hw_mgt {
u8 __iomem *mailbox_bar_hw_addr;
u64 notify_offset;
resource_size_t hw_size;
+ spinlock_t reg_lock; /* Protect reg access */
};
static inline u32 rd32(u8 __iomem *addr, u64 reg)
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
index 32e870ad2554..1300dc7500d6 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
@@ -10,6 +10,38 @@
struct nbl_channel_mgt;
struct nbl_adapter;
+#define NBL_CHAN_SEND(chan_send, dst_id, mesg_type, argument, arg_length,\
+ response, resp_length, need_ack) \
+do { \
+ typeof(chan_send) *__chan_send = &(chan_send); \
+ __chan_send->dstid = (dst_id); \
+ __chan_send->msg_type = (mesg_type); \
+ __chan_send->arg = (argument); \
+ __chan_send->arg_len = (arg_length); \
+ __chan_send->resp = (response); \
+ __chan_send->resp_len = (resp_length); \
+ __chan_send->ack = (need_ack); \
+} while (0)
+
+#define NBL_CHAN_ACK(chan_ack, dst_id, mesg_type, msg_id, err_code, ack_data, \
+ data_length) \
+do { \
+ typeof(chan_ack) *__chan_ack = &(chan_ack); \
+ __chan_ack->dstid = (dst_id); \
+ __chan_ack->msg_type = (mesg_type); \
+ __chan_ack->msgid = (msg_id); \
+ __chan_ack->err = (err_code); \
+ __chan_ack->data = (ack_data); \
+ __chan_ack->data_len = (data_length); \
+} while (0)
+
+typedef void (*nbl_chan_resp)(void *, u16, u16, void *, u32);
+
+enum {
+ NBL_CHAN_RESP_OK = 0,
+ NBL_CHAN_RESP_ERR = -1,
+};
+
enum nbl_chan_msg_type {
NBL_CHAN_MSG_ACK,
NBL_CHAN_MSG_ADD_MACVLAN,
@@ -233,12 +265,63 @@ enum nbl_chan_msg_type {
NBL_CHAN_MSG_MAILBOX_MAX,
};
+enum nbl_chan_state {
+ NBL_CHAN_INTERRUPT_READY,
+ NBL_CHAN_ABNORMAL,
+ NBL_CHAN_STATE_NBITS
+};
+
+struct nbl_board_port_info {
+ u8 eth_num;
+ u8 eth_speed;
+ u8 p4_version;
+ u8 rsv[5];
+};
+
+struct nbl_chan_send_info {
+ void *arg;
+ size_t arg_len;
+ void *resp;
+ size_t resp_len;
+ u16 dstid;
+ u16 msg_type;
+ u16 ack;
+ u16 ack_len;
+};
+
+struct nbl_chan_ack_info {
+ void *data;
+ int err;
+ u32 data_len;
+ u16 dstid;
+ u16 msg_type;
+ u16 msgid;
+};
+
enum nbl_channel_type {
NBL_CHAN_TYPE_MAILBOX,
NBL_CHAN_TYPE_MAX
};
struct nbl_channel_ops {
+ int (*send_msg)(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_send_info *chan_send);
+ int (*send_ack)(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_ack_info *chan_ack);
+ int (*register_msg)(struct nbl_channel_mgt *chan_mgt, u16 msg_type,
+ nbl_chan_resp func, void *callback_priv);
+ void (*cfg_chan_qinfo_map_table)(struct nbl_channel_mgt *chan_mgt);
+ bool (*check_queue_exist)(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type);
+ int (*setup_queue)(struct nbl_channel_mgt *chan_mgt, u8 chan_type);
+ int (*teardown_queue)(struct nbl_channel_mgt *chan_mgt, u8 chan_type);
+ void (*clean_queue_subtask)(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type);
+ void (*register_chan_task)(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type, struct work_struct *task);
+ void (*set_queue_state)(struct nbl_channel_mgt *chan_mgt,
+ enum nbl_chan_state state, u8 chan_type,
+ u8 set);
};
struct nbl_channel_ops_tbl {
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
index 03c19e1c8c3c..633f7100beb0 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
@@ -11,6 +11,8 @@
#include <linux/device.h>
#include "nbl_include.h"
+struct nbl_hash_tbl_mgt;
+
struct nbl_common_info {
struct pci_dev *pdev;
struct device *dev;
@@ -31,4 +33,28 @@ struct nbl_common_info {
u8 has_net;
};
+struct nbl_hash_tbl_key {
+ struct device *dev;
+ u16 key_size;
+ u16 data_size; /* no include key or node member */
+ u16 bucket_size;
+ u16 resv;
+};
+
+struct nbl_hash_tbl_del_key {
+ void *action_priv;
+ void (*action_func)(void *priv, void *key, void *data);
+};
+
+u32 nbl_common_pf_id_subtraction_mgtpf_id(struct nbl_common_info *common,
+ u32 pf_id);
+
+struct nbl_hash_tbl_mgt *
+nbl_common_init_hash_table(struct nbl_hash_tbl_key *key);
+void nbl_common_remove_hash_table(struct nbl_hash_tbl_mgt *tbl_mgt,
+ struct nbl_hash_tbl_del_key *key);
+int nbl_common_alloc_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key,
+ void *data, void **out_data);
+void *nbl_common_get_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key);
+
#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h
index 168504b30973..db737157b603 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h
@@ -6,9 +6,36 @@
#ifndef _NBL_DEF_HW_H_
#define _NBL_DEF_HW_H_
+#include <linux/types.h>
+
struct nbl_hw_mgt;
struct nbl_adapter;
struct nbl_hw_ops {
+ void (*configure_msix_map)(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ bool valid, dma_addr_t dma_addr, u8 bus,
+ u8 devid, u8 function);
+ void (*configure_msix_info)(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ bool valid, u16 interrupt_id, u8 bus,
+ u8 devid, u8 function,
+ bool net_msix_mask_en);
+ void (*update_mailbox_queue_tail_ptr)(struct nbl_hw_mgt *hw_mgt,
+ u16 tail_ptr, u8 txrx);
+ void (*config_mailbox_rxq)(struct nbl_hw_mgt *hw_mgt,
+ dma_addr_t dma_addr, int size_bwid);
+ void (*config_mailbox_txq)(struct nbl_hw_mgt *hw_mgt,
+ dma_addr_t dma_addr, int size_bwid);
+ void (*stop_mailbox_rxq)(struct nbl_hw_mgt *hw_mgt);
+ void (*stop_mailbox_txq)(struct nbl_hw_mgt *hw_mgt);
+ u32 (*get_host_pf_mask)(struct nbl_hw_mgt *hw_mgt);
+ u8 (*get_real_bus)(struct nbl_hw_mgt *hw_mgt);
+
+ void (*cfg_mailbox_qinfo)(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ u8 bus, u8 devid, u8 function);
+ void (*set_mailbox_irq)(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ bool enable_msix, u16 global_vec_id);
+ u32 (*get_fw_eth_map)(struct nbl_hw_mgt *hw_mgt);
+ void (*get_board_info)(struct nbl_hw_mgt *hw_mgt,
+ struct nbl_board_port_info *board);
};
struct nbl_hw_ops_tbl {
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
index 3f7d4c24c29c..fcd26cf898b0 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
@@ -10,6 +10,12 @@
/* ------ Basic definitions ------- */
#define NBL_DRIVER_NAME "nbl"
+#define NBL_MAX_PF 8
+#define NBL_NEXT_ID(id, max) \
+ ({ \
+ typeof(id) _id = (id); \
+ ((_id) == (max) ? 0 : (_id) + 1); \
+ })
enum nbl_product_type {
NBL_LEONIS_TYPE,
--
2.47.3
^ permalink raw reply related
* [PATCH v19 net-next 06/11] net/nebula-matrix: add common resource implementation
From: illusion.wang @ 2026-06-17 4:46 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, horms, linux-doc, pabeni,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
In-Reply-To: <20260617044702.2439-1-illusion.wang@nebula-matrix.com>
The Resource layer processes the entries/data of various modules within
the processing chip to accomplish specific entry management operations,
this describes the module business capabilities of the chip and the data
it manages.
The resource layer comprises the following sub-modules: common,
interrupt, and vsi(txrx,queue not contained this time)
This patch provides the common part, including the conversion
relationships among vsi_id, func_id, eth_id, and pf_id. These
relationships may be utilized in the upper layer or the resource layer.
Key Assumptions:
- nbl_res_start() initializes VSI/Eth/PF data structures **only for
control devices** (`common->has_ctrl == true`).
- APIs like nbl_res_func_id_to_vsi_id() **are guaranteed to be called
only on control devices** by the framework's dispatch layer.
Signed-off-by: illusion.wang <illusion.wang@nebula-matrix.com>
---
.../net/ethernet/nebula-matrix/nbl/Makefile | 1 +
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 47 +++++
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h | 14 ++
.../nbl_hw_leonis/nbl_resource_leonis.c | 190 ++++++++++++++++++
.../nebula-matrix/nbl/nbl_hw/nbl_resource.c | 143 +++++++++++++
.../nebula-matrix/nbl/nbl_hw/nbl_resource.h | 49 ++++-
.../nbl/nbl_include/nbl_def_common.h | 15 ++
.../nbl/nbl_include/nbl_def_resource.h | 16 ++
.../nbl/nbl_include/nbl_include.h | 8 +
9 files changed, 482 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
index c9bc060732e7..b03c20f9988e 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile
+++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
@@ -8,6 +8,7 @@ nbl-objs += nbl_common/nbl_common.o \
nbl_hw/nbl_hw_leonis/nbl_hw_leonis.o \
nbl_hw/nbl_hw_leonis/nbl_resource_leonis.o \
nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.o \
+ nbl_hw/nbl_resource.o \
nbl_core/nbl_dispatch.o \
nbl_core/nbl_dev.o \
nbl_main.o
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
index 1d25d7770d8d..f31f54d1f4f7 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
@@ -10,6 +10,18 @@
#include <linux/bitfield.h>
#include "nbl_hw_leonis.h"
+static void nbl_hw_read_mbx_regs(struct nbl_hw_mgt *hw_mgt, u64 reg, u32 *data,
+ u32 len)
+{
+ u32 i;
+
+ if (len % 4)
+ return;
+
+ for (i = 0; i < len / 4; i++)
+ data[i] = nbl_mbx_rd32(hw_mgt, reg + i * sizeof(u32));
+}
+
static void nbl_hw_write_mbx_regs(struct nbl_hw_mgt *hw_mgt, u64 reg,
const u32 *data, u32 len)
{
@@ -52,6 +64,15 @@ static void nbl_hw_wr_regs(struct nbl_hw_mgt *hw_mgt, u64 reg, const u32 *data,
spin_unlock(&hw_mgt->reg_lock);
}
+static u32 nbl_hw_get_fw_eth_map(struct nbl_hw_mgt *hw_mgt)
+{
+ u32 data;
+
+ nbl_hw_read_mbx_regs(hw_mgt, NBL_FW_BOARD_DW6_OFFSET, &data,
+ sizeof(data));
+ return FIELD_GET(NBL_FW_BOARD_DW6_ETH_BITMAP_MASK, data);
+}
+
static void nbl_hw_update_mailbox_queue_tail_ptr(struct nbl_hw_mgt *hw_mgt,
u16 tail_ptr, u8 txrx)
{
@@ -133,6 +154,14 @@ static u32 nbl_hw_get_host_pf_mask(struct nbl_hw_mgt *hw_mgt)
return data;
}
+static u8 nbl_hw_get_real_bus(struct nbl_hw_mgt *hw_mgt)
+{
+ u32 data;
+
+ data = nbl_hw_rd32(hw_mgt, NBL_PCIE_HOST_TL_CFG_BUSDEV);
+ return FIELD_GET(NBL_PCIE_BUS_MASK, data);
+}
+
static void nbl_hw_cfg_mailbox_qinfo(struct nbl_hw_mgt *hw_mgt, u16 func_id,
u8 bus, u8 devid, u8 function)
{
@@ -145,6 +174,20 @@ static void nbl_hw_cfg_mailbox_qinfo(struct nbl_hw_mgt *hw_mgt, u16 func_id,
sizeof(data));
}
+static void nbl_hw_get_board_info(struct nbl_hw_mgt *hw_mgt,
+ struct nbl_board_port_info *board_info)
+{
+ u32 data = 0;
+
+ nbl_hw_read_mbx_regs(hw_mgt, NBL_FW_BOARD_DW3_OFFSET, &data,
+ sizeof(data));
+ board_info->eth_num = FIELD_GET(NBL_FW_BOARD_DW3_PORT_NUM_MASK, data);
+ board_info->eth_speed =
+ FIELD_GET(NBL_FW_BOARD_DW3_PORT_SPEED_MASK, data);
+ board_info->p4_version =
+ FIELD_GET(NBL_FW_BOARD_DW3_P4_VERSION_MASK, data);
+}
+
static struct nbl_hw_ops hw_ops = {
.update_mailbox_queue_tail_ptr = nbl_hw_update_mailbox_queue_tail_ptr,
.config_mailbox_rxq = nbl_hw_config_mailbox_rxq,
@@ -152,8 +195,12 @@ static struct nbl_hw_ops hw_ops = {
.stop_mailbox_rxq = nbl_hw_stop_mailbox_rxq,
.stop_mailbox_txq = nbl_hw_stop_mailbox_txq,
.get_host_pf_mask = nbl_hw_get_host_pf_mask,
+ .get_real_bus = nbl_hw_get_real_bus,
+
.cfg_mailbox_qinfo = nbl_hw_cfg_mailbox_qinfo,
+ .get_fw_eth_map = nbl_hw_get_fw_eth_map,
+ .get_board_info = nbl_hw_get_board_info,
};
/* Structure starts here, adding an op should not modify anything below */
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
index d2c85175554d..e32f740d8d3f 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
@@ -69,4 +69,18 @@ struct nbl_mailbox_qinfo_cfg_table {
#define NBL_PCIE_HOST_K_PF_MASK_REG (NBL_INTF_HOST_PCIE_BASE + 0x00001004)
#define NBL_PCIE_HOST_TL_CFG_BUSDEV (NBL_INTF_HOST_PCIE_BASE + 0x11040)
+#define NBL_PCIE_BUS_MASK GENMASK(12, 5)
+#define NBL_FW_BOARD_CONFIG 0x200
+#define NBL_FW_BOARD_DW3_OFFSET (NBL_FW_BOARD_CONFIG + 12)
+#define NBL_FW_BOARD_DW6_OFFSET (NBL_FW_BOARD_CONFIG + 24)
+
+#define NBL_FW_BOARD_DW3_PORT_TYPE_MASK BIT(0)
+#define NBL_FW_BOARD_DW3_PORT_NUM_MASK GENMASK(7, 1)
+#define NBL_FW_BOARD_DW3_PORT_SPEED_MASK GENMASK(9, 8)
+#define NBL_FW_BOARD_DW3_GPIO_TYPE_MASK GENMASK(12, 10)
+#define NBL_FW_BOARD_DW3_P4_VERSION_MASK GENMASK(13, 13)
+
+#define NBL_FW_BOARD_DW6_LANE_BITMAP_MASK GENMASK(7, 0)
+#define NBL_FW_BOARD_DW6_ETH_BITMAP_MASK GENMASK(15, 8)
+
#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c
index 4b4f8e2e7fe7..47e4b6d70cbd 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c
@@ -4,9 +4,12 @@
*/
#include <linux/device.h>
#include <linux/pci.h>
+#include <linux/bits.h>
#include "nbl_resource_leonis.h"
static struct nbl_resource_ops res_ops = {
+ .get_vsi_id = nbl_res_func_id_to_vsi_id,
+ .get_eth_id = nbl_res_get_eth_id,
};
static struct nbl_resource_mgt *
@@ -45,8 +48,195 @@ nbl_res_setup_ops(struct device *dev, struct nbl_resource_mgt *res_mgt)
return res_ops_tbl;
}
+static int nbl_res_ctrl_dev_setup_eth_info(struct nbl_resource_mgt *res_mgt)
+{
+ struct nbl_hw_ops *hw_ops = res_mgt->hw_ops_tbl->ops;
+ struct device *dev = res_mgt->common->dev;
+ struct nbl_eth_info *eth_info;
+ u32 eth_bitmap, eth_id;
+ u32 eth_num = 0;
+ u32 fw_port_num;
+ int i;
+
+ eth_info = devm_kzalloc(dev, sizeof(*eth_info), GFP_KERNEL);
+ if (!eth_info)
+ return -ENOMEM;
+
+ res_mgt->resource_info->eth_info = eth_info;
+
+ fw_port_num = res_mgt->resource_info->board_info.eth_num;
+ eth_bitmap = hw_ops->get_fw_eth_map(res_mgt->hw_ops_tbl->priv);
+ if (eth_bitmap & ~((1 << NBL_MAX_ETHERNET) - 1)) {
+ dev_err(dev, "FW reported invalid eth_bitmap 0x%x\n",
+ eth_bitmap);
+ return -EINVAL;
+ }
+ if (fw_port_num != hweight32(eth_bitmap)) {
+ dev_err(dev, "FW inconsistency: port_num=%u, bitmap=0x%x\n",
+ fw_port_num, eth_bitmap);
+ return -EINVAL;
+ }
+
+ if (fw_port_num > NBL_MAX_ETHERNET || fw_port_num == 3) {
+ dev_warn(dev, "FW reports %u Ethernet ports, not supported\n",
+ fw_port_num);
+ return -EINVAL;
+ }
+ eth_info->eth_num = fw_port_num;
+ /* Intentional design constraint: each PF maps to exactly one
+ * Ethernet port. This couples PF identity to port identity
+ * and is required by nbl_res_get_eth_id() which indexes
+ * eth_info->eth_id[] by relative PF id.
+ */
+ if (res_mgt->resource_info->max_pf != eth_info->eth_num) {
+ dev_err(dev, "Invalid PF-to-port topology: max_pf=%u, eth_num=%u\n",
+ res_mgt->resource_info->max_pf, eth_info->eth_num);
+ return -EINVAL;
+ }
+
+ /* for 2 eth port board, the eth_id is 0, 2 */
+ for (i = 0; i < NBL_MAX_ETHERNET; i++) {
+ if ((1 << i) & eth_bitmap) {
+ set_bit(i, eth_info->eth_bitmap);
+ eth_info->eth_id[eth_num] = i;
+ eth_info->logic_eth_id[i] = eth_num;
+ eth_num++;
+ }
+ }
+
+ for (i = 0; i < res_mgt->resource_info->max_pf; i++) {
+ eth_id = eth_info->eth_id[i];
+ eth_info->pf_bitmap[eth_id] |= BIT(i);
+ }
+
+ return 0;
+}
+
+static int nbl_res_ctrl_dev_sriov_info_init(struct nbl_resource_mgt *res_mgt)
+{
+ struct nbl_hw_ops *hw_ops = res_mgt->hw_ops_tbl->ops;
+ struct nbl_hw_mgt *p = res_mgt->hw_ops_tbl->priv;
+ struct nbl_common_info *common = res_mgt->common;
+ struct nbl_sriov_info *sriov_info;
+ struct device *dev = common->dev;
+ u16 function;
+ u16 func_id;
+
+ sriov_info = devm_kcalloc(dev, res_mgt->resource_info->max_pf,
+ sizeof(*sriov_info), GFP_KERNEL);
+ if (!sriov_info)
+ return -ENOMEM;
+
+ res_mgt->resource_info->sriov_info = sriov_info;
+ common->hw_bus = hw_ops->get_real_bus(p);
+ if (common->function + res_mgt->resource_info->max_pf > NBL_MAX_PF) {
+ dev_err(dev, "PF count exceeds available function space\n");
+ return -EINVAL;
+ }
+ for (func_id = 0; func_id < res_mgt->resource_info->max_pf; func_id++) {
+ sriov_info = res_mgt->resource_info->sriov_info + func_id;
+ function = common->function + func_id;
+ sriov_info->bdf = PCI_DEVID(common->hw_bus,
+ PCI_DEVFN(common->devid, function));
+ }
+
+ return 0;
+}
+
+static int nbl_res_ctrl_dev_vsi_info_init(struct nbl_resource_mgt *res_mgt)
+{
+ struct nbl_eth_info *eth_info = res_mgt->resource_info->eth_info;
+ struct nbl_common_info *common = res_mgt->common;
+ struct device *dev = common->dev;
+ struct nbl_vsi_info *vsi_info;
+ int i;
+
+ vsi_info = devm_kzalloc(dev, sizeof(*vsi_info), GFP_KERNEL);
+ if (!vsi_info)
+ return -ENOMEM;
+
+ res_mgt->resource_info->vsi_info = vsi_info;
+ /*
+ * case 1 one port(1pf)
+ * pf0 (NBL_VSI_SERV_PF_DATA_TYPE) vsi is 0
+ * case 2 two port(2pf)
+ * pf0,pf1(NBL_VSI_SERV_PF_DATA_TYPE) vsi is 0,512
+ * case 3 four port(4pf)
+ * pf0,pf1,pf2,pf3(NBL_VSI_SERV_PF_DATA_TYPE) vsi is 0,256,512,768
+
+ */
+
+ vsi_info->num = eth_info->eth_num;
+ /* eth_num is guaranteed to be 1/2/4 here, so NBL_VSI_ID_GAP()
+ * will always hit one of the explicit branches.
+ */
+ for (i = 0; i < vsi_info->num; i++) {
+ vsi_info->serv_info[i][NBL_VSI_SERV_PF_DATA_TYPE].base_id =
+ i * NBL_VSI_ID_GAP(vsi_info->num);
+ vsi_info->serv_info[i][NBL_VSI_SERV_PF_DATA_TYPE].num = 1;
+ }
+
+ return 0;
+}
+
+static int nbl_res_init_pf_num(struct nbl_resource_mgt *res_mgt)
+{
+ struct nbl_hw_ops *hw_ops = res_mgt->hw_ops_tbl->ops;
+ u32 pf_num = 0;
+ u32 pf_mask;
+ int i;
+
+ pf_mask = hw_ops->get_host_pf_mask(res_mgt->hw_ops_tbl->priv);
+ /*
+ * Hardware guarantees pf_mask has contiguous cleared bits
+ * starting from bit 0 (e.g., 0b11111100, not 0b01010101).
+ * This allows us to stop at the first set bit.
+ */
+ for (i = 0; i < NBL_MAX_PF; i++) {
+ if (!(pf_mask & (1 << i)))
+ pf_num++;
+ else
+ break;
+ }
+ if (pf_num == 0 || pf_num > NBL_MAX_ETHERNET || pf_num == 3)
+ return -EINVAL;
+ res_mgt->resource_info->max_pf = pf_num;
+
+ return 0;
+}
+
+static void nbl_res_init_board_info(struct nbl_resource_mgt *res_mgt)
+{
+ struct nbl_hw_ops *hw_ops = res_mgt->hw_ops_tbl->ops;
+
+ hw_ops->get_board_info(res_mgt->hw_ops_tbl->priv,
+ &res_mgt->resource_info->board_info);
+}
+
static int nbl_res_start(struct nbl_resource_mgt *res_mgt)
{
+ struct nbl_common_info *common = res_mgt->common;
+ int ret = 0;
+
+ if (common->has_ctrl) {
+ nbl_res_init_board_info(res_mgt);
+
+ ret = nbl_res_init_pf_num(res_mgt);
+ if (ret)
+ return ret;
+
+ ret = nbl_res_ctrl_dev_sriov_info_init(res_mgt);
+ if (ret)
+ return ret;
+
+ ret = nbl_res_ctrl_dev_setup_eth_info(res_mgt);
+ if (ret)
+ return ret;
+
+ ret = nbl_res_ctrl_dev_vsi_info_init(res_mgt);
+ if (ret)
+ return ret;
+ }
return 0;
}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c
new file mode 100644
index 000000000000..6742da7c6637
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#include <linux/pci.h>
+#include "nbl_resource.h"
+
+int nbl_res_func_id_to_vsi_id(struct nbl_resource_mgt *res_mgt, u16 func_id,
+ u16 type, u16 *vsi_id)
+{
+ struct nbl_vsi_info *vsi_info = res_mgt->resource_info->vsi_info;
+ enum nbl_vsi_serv_type dst_type = NBL_VSI_SERV_PF_DATA_TYPE;
+ struct nbl_common_info *common = res_mgt->common;
+ struct device *dev = res_mgt->common->dev;
+ int pfid = func_id;
+ u32 diff;
+
+ if (!common->has_ctrl) {
+ dev_dbg(dev, "No control plane available\n");
+ return -EINVAL;
+ }
+ diff = nbl_common_pf_id_subtraction_mgtpf_id(common, pfid);
+ if (diff == U32_MAX) {
+ dev_dbg(dev, "Invalid PF ID subtraction result\n");
+ return -EINVAL;
+ }
+ if (diff >= vsi_info->num) {
+ dev_err(dev, "PF %d (diff=%u) exceeds vsi_info->num (%u)\n",
+ pfid, diff, vsi_info->num);
+ return -EINVAL;
+ }
+
+ nbl_res_pf_dev_vsi_type_to_hw_vsi_type(type, &dst_type);
+ *vsi_id = vsi_info->serv_info[diff][dst_type].base_id;
+ return 0;
+}
+
+int nbl_res_vsi_id_to_pf_id(struct nbl_resource_mgt *res_mgt, u16 vsi_id)
+{
+ struct nbl_vsi_info *vsi_info = res_mgt->resource_info->vsi_info;
+ struct nbl_common_info *common = res_mgt->common;
+ struct device *dev = res_mgt->common->dev;
+ int j = NBL_VSI_SERV_PF_DATA_TYPE;
+ int pf_id, i;
+
+ if (!common->has_ctrl) {
+ dev_dbg(dev, "No control plane available\n");
+ return -EINVAL;
+ }
+ for (i = 0; i < vsi_info->num; i++) {
+ if (vsi_id >= vsi_info->serv_info[i][j].base_id &&
+ (vsi_id < vsi_info->serv_info[i][j].base_id +
+ vsi_info->serv_info[i][j].num)) {
+ pf_id = i + common->mgt_pf;
+ if (pf_id >= NBL_MAX_PF) {
+ dev_err(dev, "PF ID overflow\n");
+ return -ERANGE;
+ }
+ return pf_id;
+ }
+ }
+
+ dev_dbg(dev, "VSI ID %u not found\n", vsi_id);
+ return -ENOENT;
+}
+
+int nbl_res_func_id_to_bdf(struct nbl_resource_mgt *res_mgt, u16 func_id,
+ u8 *bus, u8 *dev, u8 *function)
+{
+ struct nbl_common_info *common = res_mgt->common;
+ struct nbl_sriov_info *sriov_info;
+ int pfid = func_id;
+ u8 pf_bus, devfn;
+ u32 diff;
+
+ if (!common->has_ctrl || !bus || !dev || !function)
+ return -EINVAL;
+ diff = nbl_common_pf_id_subtraction_mgtpf_id(common, pfid);
+ if (diff == U32_MAX)
+ return -EINVAL;
+ if (diff >= res_mgt->resource_info->max_pf) {
+ dev_err(common->dev, "PF ID %u exceeds maximum supported PF count %u\n",
+ pfid, res_mgt->resource_info->max_pf);
+ return -ERANGE;
+ }
+ sriov_info = res_mgt->resource_info->sriov_info + diff;
+ pf_bus = PCI_BUS_NUM(sriov_info->bdf);
+ devfn = sriov_info->bdf & 0xff;
+ *bus = pf_bus;
+ *dev = PCI_SLOT(devfn);
+ *function = PCI_FUNC(devfn);
+
+ return 0;
+}
+
+int nbl_res_get_eth_id(struct nbl_resource_mgt *res_mgt, u16 func_id,
+ u16 vsi_id, u8 *eth_num, u8 *eth_id, u8 *logic_eth_id)
+{
+ struct nbl_eth_info *eth_info = res_mgt->resource_info->eth_info;
+ struct nbl_common_info *common = res_mgt->common;
+ struct device *dev = res_mgt->common->dev;
+ int pfid = func_id;
+ int rel_pf_id;
+ int abs_pf_id;
+
+ if (!common->has_ctrl || !eth_num || !eth_id || !logic_eth_id)
+ return -EINVAL;
+ abs_pf_id = nbl_res_vsi_id_to_pf_id(res_mgt, vsi_id);
+ if (abs_pf_id < 0) {
+ dev_err(dev, "Failed to get PF ID from VSI ID %u\n", vsi_id);
+ return -EINVAL;
+ }
+ if (abs_pf_id != pfid) {
+ dev_err(dev, "invalid pf id %u\n", pfid);
+ return -EINVAL;
+ }
+ rel_pf_id = abs_pf_id - common->mgt_pf;
+
+ if (rel_pf_id >= eth_info->eth_num) {
+ dev_err(dev, "rel_pf_id %d out of range [0, %u)\n",
+ rel_pf_id, eth_info->eth_num);
+ return -ERANGE;
+ }
+
+ *eth_num = eth_info->eth_num;
+ *eth_id = eth_info->eth_id[rel_pf_id];
+ *logic_eth_id = rel_pf_id;
+ return 0;
+}
+
+void nbl_res_pf_dev_vsi_type_to_hw_vsi_type(u16 src_type,
+ enum nbl_vsi_serv_type *dst_type)
+{
+ switch (src_type) {
+ case NBL_VSI_DATA:
+ *dst_type = NBL_VSI_SERV_PF_DATA_TYPE;
+ break;
+ default:
+ WARN_ON_ONCE(1);
+ break;
+ }
+}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h
index 5bfd0ddd1cec..daa3aa5fb265 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h
@@ -16,8 +16,46 @@
#include "../nbl_include/nbl_def_common.h"
#include "../nbl_core.h"
+struct nbl_resource_mgt;
+
+/* --------- INFO ---------- */
+struct nbl_sriov_info {
+ unsigned int bdf;
+};
+
+struct nbl_eth_info {
+ DECLARE_BITMAP(eth_bitmap, NBL_MAX_ETHERNET);
+ u8 pf_bitmap[NBL_MAX_ETHERNET];
+ u8 eth_num;
+ u8 resv[3];
+ u8 eth_id[NBL_MAX_PF];
+ u8 logic_eth_id[NBL_MAX_PF];
+};
+
+enum nbl_vsi_serv_type {
+ NBL_VSI_SERV_PF_DATA_TYPE,
+ NBL_VSI_SERV_MAX_TYPE,
+};
+
+struct nbl_vsi_serv_info {
+ u16 base_id;
+ u16 num;
+};
+
+struct nbl_vsi_info {
+ u16 num;
+ struct nbl_vsi_serv_info serv_info[NBL_MAX_ETHERNET]
+ [NBL_VSI_SERV_MAX_TYPE];
+};
+
struct nbl_resource_info {
- void *reserved; /* placeholder to be replaced in the future*/
+ /* ctrl-dev owned pfs */
+ DECLARE_BITMAP(func_bitmap, NBL_MAX_FUNC);
+ struct nbl_sriov_info *sriov_info;
+ struct nbl_eth_info *eth_info;
+ struct nbl_vsi_info *vsi_info;
+ u8 max_pf;
+ struct nbl_board_port_info board_info;
};
struct nbl_resource_mgt {
@@ -28,4 +66,13 @@ struct nbl_resource_mgt {
struct nbl_interrupt_mgt *intr_mgt;
};
+int nbl_res_vsi_id_to_pf_id(struct nbl_resource_mgt *res_mgt, u16 vsi_id);
+int nbl_res_func_id_to_vsi_id(struct nbl_resource_mgt *res_mgt, u16 func_id,
+ u16 type, u16 *vsi_id);
+int nbl_res_func_id_to_bdf(struct nbl_resource_mgt *res_mgt, u16 func_id,
+ u8 *bus, u8 *dev, u8 *function);
+int nbl_res_get_eth_id(struct nbl_resource_mgt *res_mgt, u16 func_id,
+ u16 vsi_id, u8 *eth_num, u8 *eth_id, u8 *logic_eth_id);
+void nbl_res_pf_dev_vsi_type_to_hw_vsi_type(u16 src_type,
+ enum nbl_vsi_serv_type *dst_type);
#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
index 633f7100beb0..bc741b7df7b9 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
@@ -12,6 +12,21 @@
#include "nbl_include.h"
struct nbl_hash_tbl_mgt;
+#define NBL_TWO_ETHERNET_PORT 2
+#define NBL_FOUR_ETHERNET_PORT 4
+#define NBL_DEFAULT_VSI_ID_GAP 1024
+#define NBL_TWO_ETHERNET_VSI_ID_GAP 512
+#define NBL_FOUR_ETHERNET_VSI_ID_GAP 256
+
+#define NBL_VSI_ID_GAP(m) \
+ ({ \
+ typeof(m) _m = (m); \
+ _m == NBL_FOUR_ETHERNET_PORT ? \
+ NBL_FOUR_ETHERNET_VSI_ID_GAP : \
+ (_m == NBL_TWO_ETHERNET_PORT ? \
+ NBL_TWO_ETHERNET_VSI_ID_GAP : \
+ NBL_DEFAULT_VSI_ID_GAP); \
+ })
struct nbl_common_info {
struct pci_dev *pdev;
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h
index d55934af5a9a..bbcd06806899 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h
@@ -6,10 +6,26 @@
#ifndef _NBL_DEF_RESOURCE_H_
#define _NBL_DEF_RESOURCE_H_
+#include <linux/types.h>
+
struct nbl_resource_mgt;
struct nbl_adapter;
struct nbl_resource_ops {
+ int (*init_chip_module)(struct nbl_resource_mgt *res_mgt);
+ void (*deinit_chip_module)(struct nbl_resource_mgt *res_mgt);
+
+ int (*configure_msix_map)(struct nbl_resource_mgt *res_mgt, u16 func_id,
+ u16 num_net_msix, u16 num_others_msix,
+ bool net_msix_mask_en);
+ int (*destroy_msix_map)(struct nbl_resource_mgt *res_mgt, u16 func_id);
+ int (*set_mailbox_irq)(struct nbl_resource_mgt *res_mgt, u16 func_id,
+ u16 vector_id, bool enable_msix);
+ int (*get_vsi_id)(struct nbl_resource_mgt *res_mgt, u16 func_id,
+ u16 type, u16 *vsi_id);
+ int (*get_eth_id)(struct nbl_resource_mgt *res_mgt, u16 func_id,
+ u16 vsi_id, u8 *eth_num, u8 *eth_id,
+ u8 *logic_eth_id);
};
struct nbl_resource_ops_tbl {
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
index fcd26cf898b0..be72bc100adb 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
@@ -17,11 +17,19 @@
((_id) == (max) ? 0 : (_id) + 1); \
})
+#define NBL_MAX_FUNC 520
+#define NBL_MAX_ETHERNET 4
+
enum nbl_product_type {
NBL_LEONIS_TYPE,
NBL_PRODUCT_MAX,
};
+enum {
+ NBL_VSI_DATA = 0,
+ NBL_VSI_MAX,
+};
+
struct nbl_func_caps {
u32 has_ctrl:1;
u32 has_net:1;
--
2.47.3
^ permalink raw reply related
* [PATCH v19 net-next 09/11] net/nebula-matrix: add Dispatch layer implementation
From: illusion.wang @ 2026-06-17 4:46 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, horms, linux-doc, pabeni,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
In-Reply-To: <20260617044702.2439-1-illusion.wang@nebula-matrix.com>
This patch introduces a control-level routing mechanism for the Dispatch layer,
supporting direct and channel routing paths based on declared control levels.
Routing is controlled by two components:
1. Interface-declared control levels (per operation)
Each operation interface declares its required control level:
- NBL_DISP_CTRL_LVL_MGT: management operations
- NBL_DISP_CTRL_LVL_NET: network operations
2. Upper-layer configured control levels (per PF driver)
The PF driver configures which control levels use the direct path
via nbl_disp_init().
Current state:
- Regular PF: configures NET_LVL at Dispatch layer.
NBL_DISP_CTRL_LVL_NET is wired in nbl_disp_init() but not yet used
by any operation. All operations declare ctrl=NBL_DISP_CTRL_LVL_MGT,
so they all fall through to the CTRL_LVL_MGT branch and use the
channel path. The direct path for NET_LVL is reserved for future
high-performance network operations.
- Management PF: configures both NET_LVL and CTRL_LVL.
Since every operation declares ctrl=NBL_DISP_CTRL_LVL_MGT,
test_bit(MGT, ctrl_lvl) is true for every op, so all ops resolve
to func (direct path), not msg_req (channel path).
Future work:
Update NBL_DISP_OPS_TBL to declare ctrl=NBL_DISP_CTRL_LVL_NET for
network operations, enabling direct path routing.
Message Handling Framework:
Message structs follow strict compatibility rules: fields can only be
appended on new DWs, never removed; array member lengths are fixed.
When extending request structs, the response handler declares a new
stack variable of the updated struct, initializes new fields to invalid
values, and performs min-copy. This is intentional per our compatibility
design (see nbl_def_channel.h). The responder may run an older version
than the requestor, so data_len < sizeof(param) is expected and handled
by min-copy + zero-fill. Rejecting short responses would break
cross-version interop.
The Channel path is used by all current operations. This design
allows the framework to be extended later to support direct HW
access for high-performance network operations without changing
the channel layer or existing control-plane operations.
Resource Layer Locking Strategy (related to this patch):
Mutex protection in nbl_dispatch_mgt:
- configure_msix_map(): LOCKED (via NBL_OPS_CALL_LOCK_RET)
- destroy_msix_map(): LOCKED
- set_mailbox_irq(): LOCKED
- init_chip_module(): UNLOCKED
- deinit_chip_module(): UNLOCKED
- get_vsi_id(): UNLOCKED
- get_eth_id(): UNLOCKED
Design rationale for unlocked call sites:
1. init_chip_module() / deinit_chip_module():
- Called ONLY from control path (PF0)
- These are init/teardown functions that run sequentially
- No concurrent access possible because:
a) Called during driver probe/remove
b) Only one control device exists
- Safe to call without mutex
2. get_vsi_id() / get_eth_id():
- These are READ-ONLY operations
- They only query existing state, never modify it
- Even if called concurrently with locked operations:
a) Reading shared state without lock is safe on most
architectures (torn reads are acceptable for IDs)
b) The locked operations that MODIFY state are:
- configure_msix_map (allocates resources)
- destroy_msix_map (frees resources)
- set_mailbox_irq (modifies hw state)
c) Reading while writing is safe if:
- Writer holds lock (prevents concurrent writes)
- Reader doesn't care about torn reads (IDs are atomic)
Mutex purpose:
The ops_mutex_lock protects MODIFY operations on shared
resource state (MSI-X map allocation, hardware configuration).
It does NOT protect read-only queries or ctrl-path init/teardown.
This is a deliberate design choice: locking only the
critical sections minimizes contention while maintaining
safety for the common case (concurrent reads).
Signed-off-by: illusion.wang <illusion.wang@nebula-matrix.com>
---
.../nbl/nbl_channel/nbl_channel.c | 5 +
.../nebula-matrix/nbl/nbl_core/nbl_dispatch.c | 447 ++++++++++++++++++
.../nebula-matrix/nbl/nbl_core/nbl_dispatch.h | 18 +
.../nbl/nbl_include/nbl_def_channel.h | 26 +
.../nbl/nbl_include/nbl_def_dispatch.h | 15 +-
.../nbl/nbl_include/nbl_include.h | 19 +
6 files changed, 529 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
index 6839972324b0..0cfa8e4e0161 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
@@ -1037,6 +1037,11 @@ int nbl_chan_init_common(struct nbl_adapter *adap)
struct nbl_channel_mgt *chan_mgt;
int ret;
+ BUILD_BUG_ON(sizeof(struct nbl_chan_param_cfg_msix_map) != 8);
+ BUILD_BUG_ON(sizeof(struct nbl_chan_param_set_mailbox_irq) != 4);
+ BUILD_BUG_ON(sizeof(struct nbl_chan_param_get_vsi_id) != 4);
+ BUILD_BUG_ON(sizeof(struct nbl_chan_param_get_eth_id) != 8);
+ BUILD_BUG_ON(sizeof(struct nbl_board_port_info) != 8);
chan_mgt = nbl_chan_setup_chan_mgt(adap);
if (IS_ERR(chan_mgt)) {
ret = PTR_ERR(chan_mgt);
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c
index f0b4406ca560..495ef3be05df 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c
@@ -6,6 +6,437 @@
#include <linux/pci.h>
#include "nbl_dispatch.h"
+static int nbl_disp_chan_get_vsi_id_req(struct nbl_dispatch_mgt *disp_mgt,
+ u16 type, u16 *vsi_id)
+{
+ struct nbl_channel_ops *chan_ops = disp_mgt->chan_ops_tbl->ops;
+ struct nbl_common_info *common = disp_mgt->common;
+ struct nbl_chan_param_get_vsi_id result = { 0 };
+ struct nbl_chan_param_get_vsi_id param = { 0 };
+ struct nbl_chan_send_info chan_send;
+ int ret;
+
+ param.type = cpu_to_le16(type);
+
+ NBL_CHAN_SEND(chan_send, common->mgt_pf, NBL_CHAN_MSG_GET_VSI_ID,
+ ¶m, sizeof(param), &result, sizeof(result), 1);
+ ret = chan_ops->send_msg(disp_mgt->chan_ops_tbl->priv, &chan_send);
+ if (ret)
+ return ret;
+
+ *vsi_id = le16_to_cpu(result.vsi_id);
+ return 0;
+}
+
+static void nbl_disp_chan_get_vsi_id_resp(void *priv, u16 src_id, u16 msg_id,
+ void *data, u32 data_len)
+{
+ struct nbl_dispatch_mgt *disp_mgt = (struct nbl_dispatch_mgt *)priv;
+ struct nbl_channel_ops *chan_ops = disp_mgt->chan_ops_tbl->ops;
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+ struct device *dev = disp_mgt->common->dev;
+ struct nbl_chan_param_get_vsi_id result = { 0 };
+ struct nbl_chan_param_get_vsi_id param = { 0 };
+ struct nbl_chan_ack_info chan_ack;
+ int err = NBL_CHAN_RESP_OK;
+ int copy_len;
+ u16 vsi_id;
+ int ret;
+
+ copy_len = data_len < sizeof(param) ? data_len : sizeof(param);
+ memcpy(¶m, data, copy_len);
+ ret = NBL_OPS_CALL_RET(res_ops->get_vsi_id,
+ (p, src_id, le16_to_cpu(param.type), &vsi_id));
+ if (ret)
+ err = NBL_CHAN_RESP_ERR;
+ result.vsi_id = cpu_to_le16(vsi_id);
+ NBL_CHAN_ACK(chan_ack, src_id, NBL_CHAN_MSG_GET_VSI_ID, msg_id, err,
+ &result, sizeof(result));
+ ret = chan_ops->send_ack(disp_mgt->chan_ops_tbl->priv, &chan_ack);
+ if (ret)
+ dev_err(dev,
+ "channel send ack failed with ret: %d, msg_type: %d\n",
+ ret, NBL_CHAN_MSG_GET_VSI_ID);
+}
+
+static int nbl_disp_chan_get_eth_id_req(struct nbl_dispatch_mgt *disp_mgt,
+ u16 vsi_id, u8 *eth_num, u8 *eth_id,
+ u8 *logic_eth_id)
+{
+ struct nbl_channel_ops *chan_ops = disp_mgt->chan_ops_tbl->ops;
+ struct nbl_common_info *common = disp_mgt->common;
+ struct nbl_chan_param_get_eth_id result = { 0 };
+ struct nbl_chan_param_get_eth_id param = { 0 };
+ struct nbl_chan_send_info chan_send;
+ int ret;
+
+ param.vsi_id = cpu_to_le16(vsi_id);
+
+ NBL_CHAN_SEND(chan_send, common->mgt_pf, NBL_CHAN_MSG_GET_ETH_ID,
+ ¶m, sizeof(param), &result, sizeof(result), 1);
+ ret = chan_ops->send_msg(disp_mgt->chan_ops_tbl->priv, &chan_send);
+ if (ret)
+ return ret;
+ *eth_num = result.eth_num;
+ *eth_id = result.eth_id;
+ *logic_eth_id = result.logic_eth_id;
+
+ return 0;
+}
+
+static void nbl_disp_chan_get_eth_id_resp(void *priv, u16 src_id, u16 msg_id,
+ void *data, u32 data_len)
+{
+ struct nbl_dispatch_mgt *disp_mgt = (struct nbl_dispatch_mgt *)priv;
+ struct nbl_channel_ops *chan_ops = disp_mgt->chan_ops_tbl->ops;
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+ struct nbl_chan_param_get_eth_id result = { 0 };
+ struct nbl_chan_param_get_eth_id param = { 0 };
+ struct device *dev = disp_mgt->common->dev;
+ struct nbl_chan_ack_info chan_ack;
+ int err = NBL_CHAN_RESP_OK;
+ int copy_len;
+ int ret;
+
+ /*
+ * The responder may run an older version than the requestor, so
+ * data_len < sizeof(param) is expected and handled by min-copy +
+ * zero-fill. Rejecting short responses would break cross-version
+ * interop
+ */
+ copy_len = data_len < sizeof(param) ? data_len : sizeof(param);
+ memcpy(¶m, data, copy_len);
+
+ ret = NBL_OPS_CALL_RET(res_ops->get_eth_id,
+ (p, src_id, le16_to_cpu(param.vsi_id),
+ &result.eth_num, &result.eth_id,
+ &result.logic_eth_id));
+ if (ret)
+ err = NBL_CHAN_RESP_ERR;
+
+ NBL_CHAN_ACK(chan_ack, src_id, NBL_CHAN_MSG_GET_ETH_ID, msg_id, err,
+ &result, sizeof(result));
+ ret = chan_ops->send_ack(disp_mgt->chan_ops_tbl->priv, &chan_ack);
+ if (ret)
+ dev_err(dev,
+ "channel send ack failed with ret: %d, msg_type: %d\n",
+ ret, NBL_CHAN_MSG_GET_ETH_ID);
+}
+
+static void nbl_disp_deinit_chip_module(struct nbl_dispatch_mgt *disp_mgt)
+{
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+
+ NBL_OPS_CALL(res_ops->deinit_chip_module, (p));
+}
+
+static int nbl_disp_init_chip_module(struct nbl_dispatch_mgt *disp_mgt)
+{
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+
+ return NBL_OPS_CALL_RET(res_ops->init_chip_module, (p));
+}
+
+static int nbl_disp_configure_msix_map(struct nbl_dispatch_mgt *disp_mgt,
+ u16 num_net_msix, u16 num_others_msix,
+ bool net_msix_mask_en)
+{
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+ struct nbl_common_info *common = disp_mgt->common;
+
+ return NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->configure_msix_map, p,
+ common->mgt_pf, num_net_msix,
+ num_others_msix, net_msix_mask_en);
+}
+
+static int
+nbl_disp_chan_configure_msix_map_req(struct nbl_dispatch_mgt *disp_mgt,
+ u16 num_net_msix, u16 num_others_msix,
+ bool net_msix_mask_en)
+{
+ struct nbl_channel_ops *chan_ops = disp_mgt->chan_ops_tbl->ops;
+ struct nbl_common_info *common = disp_mgt->common;
+ struct nbl_chan_param_cfg_msix_map param = { 0 };
+ struct nbl_chan_send_info chan_send;
+
+ param.num_net_msix = cpu_to_le16(num_net_msix);
+ param.num_others_msix = cpu_to_le16(num_others_msix);
+ param.msix_mask_en = cpu_to_le16(!!net_msix_mask_en);
+
+ NBL_CHAN_SEND(chan_send, common->mgt_pf,
+ NBL_CHAN_MSG_CONFIGURE_MSIX_MAP, ¶m, sizeof(param),
+ NULL, 0, 1);
+ return chan_ops->send_msg(disp_mgt->chan_ops_tbl->priv, &chan_send);
+}
+
+static void nbl_disp_chan_configure_msix_map_resp(void *priv, u16 src_id,
+ u16 msg_id, void *data,
+ u32 data_len)
+{
+ struct nbl_dispatch_mgt *disp_mgt = (struct nbl_dispatch_mgt *)priv;
+ struct nbl_channel_ops *chan_ops = disp_mgt->chan_ops_tbl->ops;
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+ struct device *dev = disp_mgt->common->dev;
+ struct nbl_chan_param_cfg_msix_map param = { 0 };
+ struct nbl_chan_ack_info chan_ack;
+ int err = NBL_CHAN_RESP_OK;
+ int copy_len;
+ int ret;
+
+ copy_len = data_len < sizeof(param) ? data_len : sizeof(param);
+ memcpy(¶m, data, copy_len);
+ ret = NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->configure_msix_map, p,
+ src_id, le16_to_cpu(param.num_net_msix),
+ le16_to_cpu(param.num_others_msix),
+ le16_to_cpu(param.msix_mask_en));
+ if (ret)
+ err = NBL_CHAN_RESP_ERR;
+
+ NBL_CHAN_ACK(chan_ack, src_id, NBL_CHAN_MSG_CONFIGURE_MSIX_MAP, msg_id,
+ err, NULL, 0);
+ ret = chan_ops->send_ack(disp_mgt->chan_ops_tbl->priv, &chan_ack);
+ if (ret)
+ dev_err(dev,
+ "channel send ack failed with ret: %d, msg_type: %d\n",
+ ret, NBL_CHAN_MSG_CONFIGURE_MSIX_MAP);
+}
+
+static int nbl_disp_chan_destroy_msix_map_req(struct nbl_dispatch_mgt *disp_mgt)
+{
+ struct nbl_channel_ops *chan_ops = disp_mgt->chan_ops_tbl->ops;
+ struct nbl_common_info *common = disp_mgt->common;
+ struct nbl_chan_send_info chan_send;
+
+ NBL_CHAN_SEND(chan_send, common->mgt_pf, NBL_CHAN_MSG_DESTROY_MSIX_MAP,
+ NULL, 0, NULL, 0, 1);
+ return chan_ops->send_msg(disp_mgt->chan_ops_tbl->priv, &chan_send);
+}
+
+static void nbl_disp_chan_destroy_msix_map_resp(void *priv, u16 src_id,
+ u16 msg_id, void *data,
+ u32 data_len)
+{
+ struct nbl_dispatch_mgt *disp_mgt = (struct nbl_dispatch_mgt *)priv;
+ struct nbl_channel_ops *chan_ops = disp_mgt->chan_ops_tbl->ops;
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+ struct device *dev = disp_mgt->common->dev;
+ struct nbl_chan_ack_info chan_ack;
+ int err = NBL_CHAN_RESP_OK;
+ int ret;
+
+ ret = NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->destroy_msix_map, p,
+ src_id);
+ if (ret)
+ err = NBL_CHAN_RESP_ERR;
+
+ NBL_CHAN_ACK(chan_ack, src_id, NBL_CHAN_MSG_DESTROY_MSIX_MAP, msg_id,
+ err, NULL, 0);
+ ret = chan_ops->send_ack(disp_mgt->chan_ops_tbl->priv, &chan_ack);
+ if (ret)
+ dev_err(dev,
+ "channel send ack failed with ret: %d, msg_type: %d\n",
+ ret, NBL_CHAN_MSG_DESTROY_MSIX_MAP);
+}
+
+static int nbl_disp_chan_set_mailbox_irq_req(struct nbl_dispatch_mgt *disp_mgt,
+ u16 vector_id, bool enable_msix)
+{
+ struct nbl_channel_ops *chan_ops = disp_mgt->chan_ops_tbl->ops;
+ struct nbl_chan_param_set_mailbox_irq param = { 0 };
+ struct nbl_common_info *common = disp_mgt->common;
+ struct nbl_chan_send_info chan_send;
+
+ param.vector_id = cpu_to_le16(vector_id);
+ param.enable_msix = enable_msix;
+
+ NBL_CHAN_SEND(chan_send, common->mgt_pf, NBL_CHAN_MSG_MAILBOX_SET_IRQ,
+ ¶m, sizeof(param), NULL, 0, 1);
+ return chan_ops->send_msg(disp_mgt->chan_ops_tbl->priv, &chan_send);
+}
+
+static void nbl_disp_chan_set_mailbox_irq_resp(void *priv, u16 src_id,
+ u16 msg_id, void *data,
+ u32 data_len)
+{
+ struct nbl_dispatch_mgt *disp_mgt = (struct nbl_dispatch_mgt *)priv;
+ struct nbl_channel_ops *chan_ops = disp_mgt->chan_ops_tbl->ops;
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+ struct nbl_chan_param_set_mailbox_irq param = { 0 };
+ struct device *dev = disp_mgt->common->dev;
+ struct nbl_chan_ack_info chan_ack;
+ int err = NBL_CHAN_RESP_OK;
+ bool enable_msix;
+ u16 vector_id;
+ int copy_len;
+ int ret;
+
+ copy_len = data_len < sizeof(param) ? data_len : sizeof(param);
+ memcpy(¶m, data, copy_len);
+ vector_id = le16_to_cpu(param.vector_id);
+ enable_msix = !!param.enable_msix;
+ ret = NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->set_mailbox_irq, p,
+ src_id, vector_id, enable_msix);
+ if (ret)
+ err = NBL_CHAN_RESP_ERR;
+
+ NBL_CHAN_ACK(chan_ack, src_id, NBL_CHAN_MSG_MAILBOX_SET_IRQ, msg_id,
+ err, NULL, 0);
+ ret = chan_ops->send_ack(disp_mgt->chan_ops_tbl->priv, &chan_ack);
+ if (ret)
+ dev_err(dev,
+ "channel send ack failed with ret: %d, msg_type: %d\n",
+ ret, NBL_CHAN_MSG_MAILBOX_SET_IRQ);
+}
+
+static int nbl_disp_destroy_msix_map(struct nbl_dispatch_mgt *disp_mgt)
+{
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+ struct nbl_common_info *common = disp_mgt->common;
+
+ return NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->destroy_msix_map, p,
+ common->mgt_pf);
+}
+
+static int nbl_disp_set_mailbox_irq(struct nbl_dispatch_mgt *disp_mgt,
+ u16 vector_id, bool enable_msix)
+{
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+ struct nbl_common_info *common = disp_mgt->common;
+
+ return NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->set_mailbox_irq, p,
+ common->mgt_pf, vector_id, enable_msix);
+}
+
+static int nbl_disp_get_vsi_id(struct nbl_dispatch_mgt *disp_mgt, u16 type,
+ u16 *vsi_id)
+{
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+ struct nbl_common_info *common = disp_mgt->common;
+
+ return NBL_OPS_CALL_RET(res_ops->get_vsi_id,
+ (p, common->mgt_pf, type, vsi_id));
+}
+
+static int nbl_disp_get_eth_id(struct nbl_dispatch_mgt *disp_mgt, u16 vsi_id,
+ u8 *eth_num, u8 *eth_id, u8 *logic_eth_id)
+{
+ struct nbl_resource_ops *res_ops = disp_mgt->res_ops_tbl->ops;
+ struct nbl_resource_mgt *p = disp_mgt->res_ops_tbl->priv;
+ struct nbl_common_info *common = disp_mgt->common;
+
+ return NBL_OPS_CALL_RET(res_ops->get_eth_id,
+ (p, common->mgt_pf, vsi_id, eth_num, eth_id,
+ logic_eth_id));
+}
+
+/* NBL_DISP_SET_OPS(disp_op_name, func, ctrl_lvl, msg_type, msg_req, msg_resp)
+ * ctrl_lvl is to define when this disp_op should go directly to res_op,
+ * not sending a channel msg.
+ * Use X Macros to reduce codes in channel_op and disp_op setup/remove
+ */
+#define NBL_DISP_OPS_TBL \
+do { \
+ NBL_DISP_SET_OPS(init_chip_module, nbl_disp_init_chip_module, \
+ NBL_DISP_CTRL_LVL_MGT, -1, NULL, NULL); \
+ NBL_DISP_SET_OPS(deinit_chip_module, \
+ nbl_disp_deinit_chip_module, \
+ NBL_DISP_CTRL_LVL_MGT, -1, NULL, NULL); \
+ NBL_DISP_SET_OPS(configure_msix_map, \
+ nbl_disp_configure_msix_map, \
+ NBL_DISP_CTRL_LVL_MGT, \
+ NBL_CHAN_MSG_CONFIGURE_MSIX_MAP, \
+ nbl_disp_chan_configure_msix_map_req, \
+ nbl_disp_chan_configure_msix_map_resp); \
+ NBL_DISP_SET_OPS(destroy_msix_map, nbl_disp_destroy_msix_map, \
+ NBL_DISP_CTRL_LVL_MGT, \
+ NBL_CHAN_MSG_DESTROY_MSIX_MAP, \
+ nbl_disp_chan_destroy_msix_map_req, \
+ nbl_disp_chan_destroy_msix_map_resp); \
+ NBL_DISP_SET_OPS(set_mailbox_irq, \
+ nbl_disp_set_mailbox_irq, \
+ NBL_DISP_CTRL_LVL_MGT, \
+ NBL_CHAN_MSG_MAILBOX_SET_IRQ, \
+ nbl_disp_chan_set_mailbox_irq_req, \
+ nbl_disp_chan_set_mailbox_irq_resp); \
+ NBL_DISP_SET_OPS(get_vsi_id, nbl_disp_get_vsi_id, \
+ NBL_DISP_CTRL_LVL_MGT, NBL_CHAN_MSG_GET_VSI_ID,\
+ nbl_disp_chan_get_vsi_id_req, \
+ nbl_disp_chan_get_vsi_id_resp); \
+ NBL_DISP_SET_OPS(get_eth_id, nbl_disp_get_eth_id, \
+ NBL_DISP_CTRL_LVL_MGT, NBL_CHAN_MSG_GET_ETH_ID,\
+ nbl_disp_chan_get_eth_id_req, \
+ nbl_disp_chan_get_eth_id_resp); \
+} while (0)
+
+/* Structure starts here, adding an op should not modify anything below */
+static int nbl_disp_setup_msg(struct nbl_dispatch_mgt *disp_mgt)
+{
+ struct nbl_dispatch_ops *disp_ops = disp_mgt->disp_ops_tbl->ops;
+ struct nbl_channel_ops *chan_ops = disp_mgt->chan_ops_tbl->ops;
+ struct nbl_channel_mgt *p = disp_mgt->chan_ops_tbl->priv;
+ int ret = 0;
+ int _ret;
+
+ mutex_init(&disp_mgt->ops_mutex_lock);
+
+#define NBL_DISP_SET_OPS(disp_op, func, ctrl, msg_type, msg_req, resp) \
+do { \
+ typeof(msg_type) _msg_type = (msg_type); \
+ typeof(ctrl) _ctrl_lvl = (ctrl); \
+ (void)(disp_ops->NBL_NAME(disp_op)); \
+ (void)(func); \
+ (void)(msg_req); \
+ (void)_ctrl_lvl; \
+ if (_msg_type >= 0) { \
+ _ret = chan_ops->register_msg(p, _msg_type, resp, disp_mgt);\
+ if (_ret < 0 && !ret) \
+ ret = _ret; \
+ } \
+} while (0)
+ NBL_DISP_OPS_TBL;
+#undef NBL_DISP_SET_OPS
+ /* On failure, mutex cleanup is done locally here.
+ * Message unregistration is handled in nbl_chan_remove_common().
+ * Since the dev layer is not up yet, no channel messages can arrive.
+ */
+ if (ret)
+ mutex_destroy(&disp_mgt->ops_mutex_lock);
+ return ret;
+}
+
+/* Ctrl lvl means that if a certain level is set, then all disp_ops that
+ * declared this lvl will go directly to res_ops, rather than send a
+ * channel msg, and vice versa.
+ */
+static void nbl_disp_setup_ctrl_lvl(struct nbl_dispatch_mgt *disp_mgt, u32 lvl)
+{
+ struct nbl_dispatch_ops *disp_ops = disp_mgt->disp_ops_tbl->ops;
+
+ set_bit(lvl, disp_mgt->ctrl_lvl);
+
+#define NBL_DISP_SET_OPS(disp_op, func, ctrl, msg_type, msg_req, msg_resp) \
+do { \
+ typeof(msg_type) _msg_type = (msg_type); \
+ (void)(_msg_type); \
+ (void)(msg_resp); \
+ disp_ops->NBL_NAME(disp_op) = \
+ test_bit(ctrl, disp_mgt->ctrl_lvl) ? func : msg_req; \
+} while (0)
+ NBL_DISP_OPS_TBL;
+#undef NBL_DISP_SET_OPS
+}
+
static struct nbl_dispatch_mgt *
nbl_disp_setup_disp_mgt(struct nbl_common_info *common)
{
@@ -70,9 +501,25 @@ int nbl_disp_init(struct nbl_adapter *adapter)
adapter->core.disp_mgt = disp_mgt;
adapter->intf.dispatch_ops_tbl = disp_ops_tbl;
+ ret = nbl_disp_setup_msg(disp_mgt);
+ if (ret)
+ return ret;
+
+ if (common->has_ctrl)
+ nbl_disp_setup_ctrl_lvl(disp_mgt, NBL_DISP_CTRL_LVL_MGT);
+
+ if (common->has_net)
+ nbl_disp_setup_ctrl_lvl(disp_mgt, NBL_DISP_CTRL_LVL_NET);
+
return 0;
}
void nbl_disp_remove(struct nbl_adapter *adapter)
{
+ struct nbl_dispatch_mgt *disp_mgt = adapter->core.disp_mgt;
+
+ /* dev layer has been stopped and removed, no channel messages
+ * can arrive at this point, so it is safe to destroy the mutex.
+ */
+ mutex_destroy(&disp_mgt->ops_mutex_lock);
}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h
index fa7f4597febe..c74657681f89 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h
@@ -14,12 +14,30 @@
#include "../nbl_include/nbl_def_common.h"
#include "../nbl_core.h"
+#define NBL_OPS_CALL_LOCK_RET(disp_mgt, func, ...) \
+({ \
+ typeof(disp_mgt) _disp_mgt = (disp_mgt); \
+ typeof(func) _func = (func); \
+ typeof(_func(__VA_ARGS__)) _ret = 0; \
+ \
+ mutex_lock(&_disp_mgt->ops_mutex_lock); \
+ \
+ if (_func) \
+ _ret = _func(__VA_ARGS__); \
+ \
+ mutex_unlock(&_disp_mgt->ops_mutex_lock); \
+ \
+ _ret; \
+})
+
struct nbl_dispatch_mgt {
struct nbl_common_info *common;
struct nbl_resource_ops_tbl *res_ops_tbl;
struct nbl_channel_ops_tbl *chan_ops_tbl;
struct nbl_dispatch_ops_tbl *disp_ops_tbl;
DECLARE_BITMAP(ctrl_lvl, NBL_DISP_CTRL_LVL_MAX);
+ /* use for the caller not in interrupt */
+ struct mutex ops_mutex_lock;
};
#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
index 1300dc7500d6..a4312f1ef745 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
@@ -271,6 +271,32 @@ enum nbl_chan_state {
NBL_CHAN_STATE_NBITS
};
+struct nbl_chan_param_cfg_msix_map {
+ __le16 num_net_msix;
+ __le16 num_others_msix;
+ __le16 msix_mask_en;
+ __le16 rsvd;
+};
+
+struct nbl_chan_param_set_mailbox_irq {
+ __le16 vector_id;
+ u8 enable_msix;
+ u8 rsvd;
+};
+
+struct nbl_chan_param_get_vsi_id {
+ __le16 vsi_id;
+ __le16 type;
+};
+
+struct nbl_chan_param_get_eth_id {
+ __le16 vsi_id;
+ u8 eth_num;
+ u8 eth_id;
+ u8 logic_eth_id;
+ u8 rsvd[3];
+};
+
struct nbl_board_port_info {
u8 eth_num;
u8 eth_speed;
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h
index 53492b044f79..e62ee934efa0 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h
@@ -6,6 +6,8 @@
#ifndef _NBL_DEF_DISPATCH_H_
#define _NBL_DEF_DISPATCH_H_
+#include <linux/types.h>
+
struct nbl_dispatch_mgt;
struct nbl_adapter;
enum {
@@ -16,7 +18,18 @@ enum {
};
struct nbl_dispatch_ops {
- void *reserved; /* placeholder to be replaced in the future*/
+ int (*init_chip_module)(struct nbl_dispatch_mgt *disp_mgt);
+ void (*deinit_chip_module)(struct nbl_dispatch_mgt *disp_mgt);
+ int (*configure_msix_map)(struct nbl_dispatch_mgt *disp_mgt,
+ u16 num_net_msix, u16 num_others_msix,
+ bool net_msix_mask_en);
+ int (*destroy_msix_map)(struct nbl_dispatch_mgt *disp_mgt);
+ int (*set_mailbox_irq)(struct nbl_dispatch_mgt *disp_mgt,
+ u16 vector_id, bool enable_msix);
+ int (*get_vsi_id)(struct nbl_dispatch_mgt *disp_mgt, u16 type,
+ u16 *vsi_id);
+ int (*get_eth_id)(struct nbl_dispatch_mgt *disp_mgt, u16 vsi_id,
+ u8 *eth_num, u8 *eth_id, u8 *logic_eth_id);
};
struct nbl_dispatch_ops_tbl {
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
index 5f3bcd48e9cd..e1f7148b7c7e 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
@@ -50,6 +50,25 @@ enum nbl_fw_port_speed {
NBL_FW_PORT_SPEED_100G,
};
+#define NBL_OPS_CALL(func, para) \
+do { \
+ typeof(func) _func = (func); \
+ if (_func) \
+ _func para; \
+} while (0)
+
+#define NBL_OPS_CALL_RET(func, para) \
+({ \
+ typeof(func) _func = (func); \
+ _func ? _func para : 0; \
+})
+
+#define NBL_OPS_CALL_RET_PTR(func, para) \
+({ \
+ typeof(func) _func = (func); \
+ _func ? _func para : NULL; \
+})
+
enum nbl_performance_mode {
NBL_QUIRKS_NO_TOE,
NBL_QUIRKS_UVN_PREFETCH_ALIGN,
--
2.47.3
^ permalink raw reply related
* [PATCH v19 net-next 04/11] net/nebula-matrix: channel msg value and msg struct
From: illusion.wang @ 2026-06-17 4:46 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, horms, linux-doc, pabeni,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
In-Reply-To: <20260617044702.2439-1-illusion.wang@nebula-matrix.com>
The msg ID values are derived from enum ordinal and serve as wire
opcodes. The set is stable and must not be reordered or extended
without a wire-format change.
Signed-off-by: illusion.wang <illusion.wang@nebula-matrix.com>
---
.../nbl/nbl_include/nbl_def_channel.h | 225 ++++++++++++++++++
1 file changed, 225 insertions(+)
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
index ff03a53b9f5d..32e870ad2554 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
@@ -6,8 +6,233 @@
#ifndef _NBL_DEF_CHANNEL_H_
#define _NBL_DEF_CHANNEL_H_
+#include <linux/types.h>
+
struct nbl_channel_mgt;
struct nbl_adapter;
+enum nbl_chan_msg_type {
+ NBL_CHAN_MSG_ACK,
+ NBL_CHAN_MSG_ADD_MACVLAN,
+ NBL_CHAN_MSG_DEL_MACVLAN,
+ NBL_CHAN_MSG_ADD_MULTI_RULE,
+ NBL_CHAN_MSG_DEL_MULTI_RULE,
+ NBL_CHAN_MSG_SETUP_MULTI_GROUP,
+ NBL_CHAN_MSG_REMOVE_MULTI_GROUP,
+ NBL_CHAN_MSG_REGISTER_NET,
+ NBL_CHAN_MSG_UNREGISTER_NET,
+ NBL_CHAN_MSG_ALLOC_TXRX_QUEUES,
+ NBL_CHAN_MSG_FREE_TXRX_QUEUES,
+ NBL_CHAN_MSG_SETUP_QUEUE,
+ NBL_CHAN_MSG_REMOVE_ALL_QUEUES,
+ NBL_CHAN_MSG_CFG_DSCH,
+ NBL_CHAN_MSG_SETUP_CQS,
+ NBL_CHAN_MSG_REMOVE_CQS,
+ NBL_CHAN_MSG_CFG_QDISC_MQPRIO,
+ NBL_CHAN_MSG_CONFIGURE_MSIX_MAP,
+ NBL_CHAN_MSG_DESTROY_MSIX_MAP,
+ NBL_CHAN_MSG_MAILBOX_SET_IRQ,
+ NBL_CHAN_MSG_GET_GLOBAL_VECTOR,
+ NBL_CHAN_MSG_GET_VSI_ID,
+ NBL_CHAN_MSG_SET_PROMISC_MODE,
+ NBL_CHAN_MSG_GET_FIRMWARE_VERSION,
+ NBL_CHAN_MSG_GET_QUEUE_ERR_STATS,
+ NBL_CHAN_MSG_GET_COALESCE,
+ NBL_CHAN_MSG_SET_COALESCE,
+ NBL_CHAN_MSG_SET_SPOOF_CHECK_ADDR,
+ NBL_CHAN_MSG_SET_VF_SPOOF_CHECK,
+ NBL_CHAN_MSG_GET_RXFH_INDIR_SIZE,
+ NBL_CHAN_MSG_GET_RXFH_INDIR,
+ NBL_CHAN_MSG_GET_RXFH_RSS_KEY,
+ NBL_CHAN_MSG_GET_RXFH_RSS_ALG_SEL,
+ NBL_CHAN_MSG_GET_HW_CAPS,
+ NBL_CHAN_MSG_GET_HW_STATE,
+ NBL_CHAN_MSG_REGISTER_RDMA,
+ NBL_CHAN_MSG_UNREGISTER_RDMA,
+ NBL_CHAN_MSG_GET_REAL_HW_ADDR,
+ NBL_CHAN_MSG_GET_REAL_BDF,
+ NBL_CHAN_MSG_GRC_PROCESS,
+ NBL_CHAN_MSG_SET_SFP_STATE,
+ NBL_CHAN_MSG_SET_ETH_LOOPBACK,
+ NBL_CHAN_MSG_CHECK_ACTIVE_VF,
+ NBL_CHAN_MSG_GET_PRODUCT_FLEX_CAP,
+ NBL_CHAN_MSG_ALLOC_KTLS_TX_INDEX,
+ NBL_CHAN_MSG_FREE_KTLS_TX_INDEX,
+ NBL_CHAN_MSG_CFG_KTLS_TX_KEYMAT,
+ NBL_CHAN_MSG_ALLOC_KTLS_RX_INDEX,
+ NBL_CHAN_MSG_FREE_KTLS_RX_INDEX,
+ NBL_CHAN_MSG_CFG_KTLS_RX_KEYMAT,
+ NBL_CHAN_MSG_CFG_KTLS_RX_RECORD,
+ NBL_CHAN_MSG_ADD_KTLS_RX_FLOW,
+ NBL_CHAN_MSG_DEL_KTLS_RX_FLOW,
+ NBL_CHAN_MSG_ALLOC_IPSEC_TX_INDEX,
+ NBL_CHAN_MSG_FREE_IPSEC_TX_INDEX,
+ NBL_CHAN_MSG_ALLOC_IPSEC_RX_INDEX,
+ NBL_CHAN_MSG_FREE_IPSEC_RX_INDEX,
+ NBL_CHAN_MSG_CFG_IPSEC_TX_SAD,
+ NBL_CHAN_MSG_CFG_IPSEC_RX_SAD,
+ NBL_CHAN_MSG_ADD_IPSEC_TX_FLOW,
+ NBL_CHAN_MSG_DEL_IPSEC_TX_FLOW,
+ NBL_CHAN_MSG_ADD_IPSEC_RX_FLOW,
+ NBL_CHAN_MSG_DEL_IPSEC_RX_FLOW,
+ NBL_CHAN_MSG_NOTIFY_IPSEC_HARD_EXPIRE,
+ NBL_CHAN_MSG_GET_MBX_IRQ_NUM,
+ NBL_CHAN_MSG_CLEAR_FLOW,
+ NBL_CHAN_MSG_CLEAR_QUEUE,
+ NBL_CHAN_MSG_GET_ETH_ID,
+ NBL_CHAN_MSG_SET_OFFLOAD_STATUS,
+ NBL_CHAN_MSG_INIT_OFLD,
+ NBL_CHAN_MSG_INIT_CMDQ,
+ NBL_CHAN_MSG_DESTROY_CMDQ,
+ NBL_CHAN_MSG_RESET_CMDQ,
+ NBL_CHAN_MSG_INIT_FLOW,
+ NBL_CHAN_MSG_DEINIT_FLOW,
+ NBL_CHAN_MSG_OFFLOAD_FLOW_RULE,
+ NBL_CHAN_MSG_GET_ACL_SWITCH,
+ NBL_CHAN_MSG_GET_VSI_GLOBAL_QUEUE_ID,
+ NBL_CHAN_MSG_INIT_REP,
+ NBL_CHAN_MSG_GET_LINE_RATE_INFO,
+ NBL_CHAN_MSG_REGISTER_NET_REP,
+ NBL_CHAN_MSG_UNREGISTER_NET_REP,
+ NBL_CHAN_MSG_REGISTER_ETH_REP,
+ NBL_CHAN_MSG_UNREGISTER_ETH_REP,
+ NBL_CHAN_MSG_REGISTER_UPCALL_PORT,
+ NBL_CHAN_MSG_UNREGISTER_UPCALL_PORT,
+ NBL_CHAN_MSG_GET_PORT_STATE,
+ NBL_CHAN_MSG_SET_PORT_ADVERTISING,
+ NBL_CHAN_MSG_GET_MODULE_INFO,
+ NBL_CHAN_MSG_GET_MODULE_EEPROM,
+ NBL_CHAN_MSG_GET_LINK_STATE,
+ NBL_CHAN_MSG_NOTIFY_LINK_STATE,
+ NBL_CHAN_MSG_GET_QUEUE_CXT,
+ NBL_CHAN_MSG_CFG_LOG,
+ NBL_CHAN_MSG_INIT_VDPAQ,
+ NBL_CHAN_MSG_DESTROY_VDPAQ,
+ NBL_CHAN_MSG_GET_UPCALL_PORT,
+ NBL_CHAN_MSG_NOTIFY_ETH_REP_LINK_STATE,
+ NBL_CHAN_MSG_SET_ETH_MAC_ADDR,
+ NBL_CHAN_MSG_GET_FUNCTION_ID,
+ NBL_CHAN_MSG_GET_CHIP_TEMPERATURE,
+ NBL_CHAN_MSG_DISABLE_HW_FLOW,
+ NBL_CHAN_MSG_ENABLE_HW_FLOW,
+ NBL_CHAN_MSG_SET_UPCALL_RULE,
+ NBL_CHAN_MSG_UNSET_UPCALL_RULE,
+ NBL_CHAN_MSG_GET_REG_DUMP,
+ NBL_CHAN_MSG_GET_REG_DUMP_LEN,
+ NBL_CHAN_MSG_CFG_LAG_HASH_ALGORITHM,
+ NBL_CHAN_MSG_CFG_LAG_MEMBER_FWD,
+ NBL_CHAN_MSG_CFG_LAG_MEMBER_LIST,
+ NBL_CHAN_MSG_CFG_LAG_MEMBER_UP_ATTR,
+ NBL_CHAN_MSG_ADD_LAG_FLOW,
+ NBL_CHAN_MSG_DEL_LAG_FLOW,
+ NBL_CHAN_MSG_SWITCHDEV_INIT_CMDQ,
+ NBL_CHAN_MSG_SWITCHDEV_DEINIT_CMDQ,
+ NBL_CHAN_MSG_SET_TC_FLOW_INFO,
+ NBL_CHAN_MSG_UNSET_TC_FLOW_INFO,
+ NBL_CHAN_MSG_INIT_ACL,
+ NBL_CHAN_MSG_UNINIT_ACL,
+ NBL_CHAN_MSG_CFG_LAG_MCC,
+ NBL_CHAN_MSG_REGISTER_VSI2Q,
+ NBL_CHAN_MSG_SETUP_Q2VSI,
+ NBL_CHAN_MSG_REMOVE_Q2VSI,
+ NBL_CHAN_MSG_SETUP_RSS,
+ NBL_CHAN_MSG_REMOVE_RSS,
+ NBL_CHAN_MSG_GET_REP_QUEUE_INFO,
+ NBL_CHAN_MSG_CTRL_PORT_LED,
+ NBL_CHAN_MSG_NWAY_RESET,
+ NBL_CHAN_MSG_SET_INTL_SUPPRESS_LEVEL,
+ NBL_CHAN_MSG_GET_ETH_STATS,
+ NBL_CHAN_MSG_GET_MODULE_TEMPERATURE,
+ NBL_CHAN_MSG_GET_BOARD_INFO,
+ NBL_CHAN_MSG_GET_P4_USED,
+ NBL_CHAN_MSG_GET_VF_BASE_VSI_ID,
+ NBL_CHAN_MSG_ADD_LLDP_FLOW,
+ NBL_CHAN_MSG_DEL_LLDP_FLOW,
+ NBL_CHAN_MSG_CFG_ETH_BOND_INFO,
+ NBL_CHAN_MSG_CFG_DUPPKT_MCC,
+ NBL_CHAN_MSG_ADD_ND_UPCALL_FLOW,
+ NBL_CHAN_MSG_DEL_ND_UPCALL_FLOW,
+ NBL_CHAN_MSG_GET_BOARD_ID,
+ NBL_CHAN_MSG_SET_SHAPING_DPORT_VLD,
+ NBL_CHAN_MSG_SET_DPORT_FC_TH_VLD,
+ NBL_CHAN_MSG_REGISTER_RDMA_BOND,
+ NBL_CHAN_MSG_UNREGISTER_RDMA_BOND,
+ NBL_CHAN_MSG_RESTORE_NETDEV_QUEUE,
+ NBL_CHAN_MSG_RESTART_NETDEV_QUEUE,
+ NBL_CHAN_MSG_RESTORE_HW_QUEUE,
+ NBL_CHAN_MSG_KEEP_ALIVE,
+ NBL_CHAN_MSG_GET_BASE_MAC_ADDR,
+ NBL_CHAN_MSG_CFG_BOND_SHAPING,
+ NBL_CHAN_MSG_CFG_BGID_BACK_PRESSURE,
+ NBL_CHAN_MSG_ALLOC_KT_BLOCK,
+ NBL_CHAN_MSG_FREE_KT_BLOCK,
+ NBL_CHAN_MSG_GET_USER_QUEUE_INFO,
+ NBL_CHAN_MSG_GET_ETH_BOND_INFO,
+ NBL_CHAN_MSG_CLEAR_ACCEL_FLOW,
+ NBL_CHAN_MSG_SET_BRIDGE_MODE,
+ NBL_CHAN_MSG_GET_VF_FUNCTION_ID,
+ NBL_CHAN_MSG_NOTIFY_LINK_FORCED,
+ NBL_CHAN_MSG_SET_PMD_DEBUG,
+ NBL_CHAN_MSG_REGISTER_FUNC_MAC,
+ NBL_CHAN_MSG_SET_TX_RATE,
+ NBL_CHAN_MSG_REGISTER_FUNC_LINK_FORCED,
+ NBL_CHAN_MSG_GET_LINK_FORCED,
+ NBL_CHAN_MSG_REGISTER_FUNC_VLAN,
+ NBL_CHAN_MSG_GET_FD_FLOW,
+ NBL_CHAN_MSG_GET_FD_FLOW_CNT,
+ NBL_CHAN_MSG_GET_FD_FLOW_ALL,
+ NBL_CHAN_MSG_GET_FD_FLOW_MAX,
+ NBL_CHAN_MSG_REPLACE_FD_FLOW,
+ NBL_CHAN_MSG_REMOVE_FD_FLOW,
+ NBL_CHAN_MSG_CFG_FD_FLOW_STATE,
+ NBL_CHAN_MSG_REGISTER_FUNC_RATE,
+ NBL_CHAN_MSG_NOTIFY_VLAN,
+ NBL_CHAN_MSG_GET_XDP_QUEUE_INFO,
+ NBL_CHAN_MSG_STOP_ABNORMAL_SW_QUEUE,
+ NBL_CHAN_MSG_STOP_ABNORMAL_HW_QUEUE,
+ NBL_CHAN_MSG_NOTIFY_RESET_EVENT,
+ NBL_CHAN_MSG_ACK_RESET_EVENT,
+ NBL_CHAN_MSG_GET_VF_VSI_ID,
+ NBL_CHAN_MSG_CONFIGURE_QOS,
+ NBL_CHAN_MSG_GET_PFC_BUFFER_SIZE,
+ NBL_CHAN_MSG_SET_PFC_BUFFER_SIZE,
+ NBL_CHAN_MSG_GET_VF_STATS,
+ NBL_CHAN_MSG_REGISTER_FUNC_TRUST,
+ NBL_CHAN_MSG_NOTIFY_TRUST,
+ NBL_CHAN_MSG_CHECK_VF_IS_ACTIVE,
+ NBL_CHAN_MSG_GET_ETH_ABNORMAL_STATS,
+ NBL_CHAN_MSG_GET_ETH_CTRL_STATS,
+ NBL_CHAN_MSG_GET_PAUSE_STATS,
+ NBL_CHAN_MSG_GET_ETH_MAC_STATS,
+ NBL_CHAN_MSG_GET_FEC_STATS,
+ NBL_CHAN_MSG_CFG_MULTI_MCAST_RULE,
+ NBL_CHAN_MSG_GET_LINK_DOWN_COUNT,
+ NBL_CHAN_MSG_GET_LINK_STATUS_OPCODE,
+ NBL_CHAN_MSG_GET_RMON_STATS,
+ NBL_CHAN_MSG_REGISTER_PF_NAME,
+ NBL_CHAN_MSG_GET_PF_NAME,
+ NBL_CHAN_MSG_CONFIGURE_RDMA_BW,
+ NBL_CHAN_MSG_SET_RATE_LIMIT,
+ NBL_CHAN_MSG_SET_TC_WGT,
+ NBL_CHAN_MSG_REMOVE_QUEUE,
+ NBL_CHAN_MSG_GET_MIRROR_TABLE_ID,
+ NBL_CHAN_MSG_CONFIGURE_MIRROR,
+ NBL_CHAN_MSG_CONFIGURE_MIRROR_TABLE,
+ NBL_CHAN_MSG_CLEAR_MIRROR_CFG,
+ NBL_CHAN_MSG_MIRROR_OUTPUTPORT_NOTIFY,
+ NBL_CHAN_MSG_CHECK_FLOWTABLE_SPEC,
+ NBL_CHAN_MSG_CHECK_VF_IS_VDPA,
+ NBL_CHAN_MSG_GET_VDPA_VF_STATS,
+ NBL_CHAN_MSG_SET_RX_RATE,
+ NBL_CHAN_MSG_GET_UVN_PKT_DROP_STATS,
+ NBL_CHAN_MSG_GET_USTORE_PKT_DROP_STATS,
+ NBL_CHAN_MSG_GET_USTORE_TOTAL_PKT_DROP_STATS,
+ NBL_CHAN_MSG_SET_WOL,
+ NBL_CHAN_MSG_INIT_VF_MSIX_MAP,
+ NBL_CHAN_MSG_GET_ST_NAME,
+ /* mailbox msg end */
+ NBL_CHAN_MSG_MAILBOX_MAX,
+};
+
enum nbl_channel_type {
NBL_CHAN_TYPE_MAILBOX,
NBL_CHAN_TYPE_MAX
--
2.47.3
^ permalink raw reply related
* [PATCH v19 net-next 00/11] nbl driver for Nebulamatrix NICs
From: illusion.wang @ 2026-06-17 4:46 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, horms, linux-doc, pabeni,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
From: illusion wang <illusion.wang@nebula-matrix.com>
This patch series represents the first phase. We plan to integrate it in
two phases: the first phase covers mailbox and chip configuration,
while the second phase involves net dev configuration.
Together, they will provide basic PF-based Ethernet port transmission and
reception capabilities.
After that, we will consider other features, such as ethtool support,
flow management, adminq messaging, VF support, debugfs support, etc.
changes v18->v19
Link to v18:https://lore.kernel.org/netdev/20260611044916.2383-1-illusion.wang@nebula-matrix.com/
changes v17->v18
Link to v17:https://lore.kernel.org/netdev/20260601093149.25905-1-illusion.wang@nebula-matrix.com/
changes v16->v17
Link to v16:https://lore.kernel.org/netdev/20260526035453.2359-1-illusion.wang@nebula-matrix.com/
AI review issues
changes v15->v16
Link to v15:https://lore.kernel.org/netdev/20260520032950.4874-1-illusion.wang@nebula-matrix.com/
AI review issues
changes v14->v15
Link to v14:https://lore.kernel.org/netdev/20260513011649.4404-1-illusion.wang@nebula-matrix.com/
AI review issues
changes v13->v14
Link to v13:https://lore.kernel.org/netdev/20260428114910.2616-1-illusion.wang@nebula-matrix.com/
AI review issues
changes v12->v13
Link to v12:https://lore.kernel.org/netdev/20260415033608.2438-1-illusion.wang@nebula-matrix.com/
AI review issues
changes v11->v12
Link to v11:https://lore.kernel.org/netdev/20260408093739.56001-1-illusion.wang@nebula-matrix.com/
AI review issues
changes v10->v11
Link to v10:https://lore.kernel.org/netdev/20260401022318.28550-1-illusion.wang@nebula-matrix.com/
1.Issues found by Mohsin
2.AI review issues
changes v9->v10
Link to v9:https://lore.kernel.org/netdev/20260325040048.2313-1-illusion.wang@nebula-matrix.com/
1.Issues found by Jakub
2.AI review issue
changes v8->v9
Link to v8:https://lore.kernel.org/netdev/20260317034533.5600-1-illusion.wang@nebula-matrix.com/
1.Issues found by Jakub
2.AI review issue
Changes v7→v8
Link to v7:https://lore.kernel.org/netdev/20260310120959.22015-1-illusion.wang@nebula-matrix.com/
1.Issues found by Paolo
Changes v6->v7
Link to v6:https://lore.kernel.org/netdev/20260306033451.5196-1-illusion.wang@nebula-matrix.com/
1.Issue found by Jakub
2.AI review issue
Changes v5->v6
Link to V5:https://lore.kernel.org/netdev/20260226073840.3222-1-illusion.wang@nebula-matrix.com/
1.put all standard linux includes files the .c file which needs it & others
--Andrew
2.AI review issue
Changes v4->v5
Link to V4:https://lore.kernel.org/netdev/20260206021608.85381-1-illusion.wang@nebula-matrix.com/
1.change nbl_core to nbl & change ** pointers to *pointers & others
--Andrew
2.AI review issue
Changes v3->v4
Link to v3: https://lore.kernel.org/netdev/20260123011804.31263-1-illusion.wang@nebula-matrix.com
1.cut down to part of a mini driver(mailbox and chip init)
--Jakub Kicinski Simon Horman(some sort of staged approached)
2.modify issues found by ai.
3. Reverse Christmas tree/nbl_err/devm_kfree/remove some macros/
void type to real type/others
--Andrew Lunn
4.change deprecated pci_enable_msix_range to pci_alloc_irq_vectors
5.delete service layer
6.the style of kconfig---Randy Dunlap
7.add to Documentation/networking/device_drivers/ethernet/index.rst
--Simon Horman
Changes v2 →v3
Link to v2: https://lore.kernel.org/netdev/20260109100146.63569-1-illusion.wang@nebula-matrix.com/
1.cut down to a mini driver:
delete vf support
use promisc mode to cut down flow management
drop patch15 in v2
delete adminq msg
delete abnormal handling
delete some unimportant interfaces
2.modify issues found by ai review
Changes v1->v2
Link to v1: https://lore.kernel.org/netdev/20251223035113.31122-1-illusion.wang@nebula-matrix.com/
1.Format Issues and Compilation Issues
- Paolo Abeni
2.add sysfs patch and drop coexisting patch
- Andrew Lunn
3.delete some unimportant ndo operations
4.add machine generated headers patch
5.Modify the issues found in patch1-2 and apply the same fixes to other
patches
6.modify issues found by nipa
illusion.wang (11):
net/nebula-matrix: add minimum nbl build framework
net/nebula-matrix: add our driver architecture
net/nebula-matrix: P4 configuration invoked during chip initialization
net/nebula-matrix: channel msg value and msg struct
net/nebula-matrix: add channel layer
net/nebula-matrix: add common resource implementation
net/nebula-matrix: add intr resource implementation
net/nebula-matrix: add vsi resource implementation
net/nebula-matrix: add Dispatch layer implementation
net/nebula-matrix: add common/ctrl dev init/remove operation
net/nebula-matrix: add common dev start/stop operation
.../device_drivers/ethernet/index.rst | 1 +
.../ethernet/nebula-matrix/nbl.rst | 28 +
MAINTAINERS | 10 +
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
drivers/net/ethernet/nebula-matrix/Kconfig | 34 +
drivers/net/ethernet/nebula-matrix/Makefile | 6 +
.../net/ethernet/nebula-matrix/nbl/Makefile | 16 +
.../nbl/nbl_channel/nbl_channel.c | 1083 +++++++
.../nbl/nbl_channel/nbl_channel.h | 166 +
.../nebula-matrix/nbl/nbl_common/nbl_common.c | 217 ++
.../nebula-matrix/nbl/nbl_common/nbl_common.h | 33 +
.../net/ethernet/nebula-matrix/nbl/nbl_core.h | 58 +
.../nebula-matrix/nbl/nbl_core/nbl_dev.c | 474 +++
.../nebula-matrix/nbl/nbl_core/nbl_dev.h | 58 +
.../nebula-matrix/nbl/nbl_core/nbl_dispatch.c | 525 +++
.../nebula-matrix/nbl/nbl_core/nbl_dispatch.h | 43 +
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 918 ++++++
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h | 370 +++
.../nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.c | 2887 +++++++++++++++++
.../nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.h | 11 +
.../nbl_hw_leonis/nbl_resource_leonis.c | 287 ++
.../nbl_hw_leonis/nbl_resource_leonis.h | 12 +
.../nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h | 74 +
.../nebula-matrix/nbl/nbl_hw/nbl_interrupt.c | 267 ++
.../nebula-matrix/nbl/nbl_hw/nbl_interrupt.h | 21 +
.../nebula-matrix/nbl/nbl_hw/nbl_resource.c | 143 +
.../nebula-matrix/nbl/nbl_hw/nbl_resource.h | 111 +
.../nebula-matrix/nbl/nbl_hw/nbl_vsi.c | 26 +
.../nebula-matrix/nbl/nbl_hw/nbl_vsi.h | 12 +
.../nbl/nbl_include/nbl_def_channel.h | 360 ++
.../nbl/nbl_include/nbl_def_common.h | 81 +
.../nbl/nbl_include/nbl_def_dev.h | 16 +
.../nbl/nbl_include/nbl_def_dispatch.h | 42 +
.../nbl/nbl_include/nbl_def_hw.h | 54 +
.../nbl/nbl_include/nbl_def_resource.h | 38 +
.../nbl/nbl_include/nbl_include.h | 77 +
.../nbl/nbl_include/nbl_product_base.h | 19 +
.../net/ethernet/nebula-matrix/nbl/nbl_main.c | 304 ++
39 files changed, 8884 insertions(+)
create mode 100644 Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst
create mode 100644 drivers/net/ethernet/nebula-matrix/Kconfig
create mode 100644 drivers/net/ethernet/nebula-matrix/Makefile
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/Makefile
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dev.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_product_base.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c
--
2.47.3
^ permalink raw reply
* [PATCH v19 net-next 02/11] net/nebula-matrix: add our driver architecture
From: illusion.wang @ 2026-06-17 4:46 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, horms, linux-doc, pabeni,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
In-Reply-To: <20260617044702.2439-1-illusion.wang@nebula-matrix.com>
This commit introduces the baseline driver architecture for the
nebula-matrix networking device. It establishes the Hardware, Channel,
Resource, Dispatch, and Device layers for device management.
our driver architecture:
Hardware (HW), Channel, Resource, Dispatch, and Device Layer
Struct Initialization/Deinitialization, and Operation Set Registration/
Unregistration
Our driver architecture is relatively complex because the code is highly
reusable and designed to support multiple features. Additionally, the
codebase supports multiple chip variants, each with distinct
hardware-software interactions.
To ensure compatibility, our architecture is divided into the following
layers:
1. Dev Layer (Device Layer)
The top-level business logic layer where all operations are
device-centric. Every operation is performed relative to the device
context. The intergration of base functions encompasses:
management(ctrl only for leonis pf0), network(net_dev,this time not
contained),common.
2. Dispatch Layer
The distribution from services to specific data operations is mainly
divided into two types: direct pass-through and handling by the
management PF. It shields the upper layer from the differences in
specific underlying locations.
It describes the processing locations and paths of the services.
3. Resource Layer
Handles tasks dispatched from Dispatch Layer. These tasks fall into two
categories:
3.1 Hardware control
The Resource Layer further invokes the HW Layer when hardware access is
needed, as only the HW Layer has OS-level privileges.
3.2 Software resource management
Operations like packet statistics collection that don't require hardware
access.
4. HW Layer (Hardware Layer)
Serves the Resource Layer by interacting with different hardware
chipsets.Writes to hardware registers to drive the hardware based on
Resource Layer directives.
5. Channel Layer
Handle communication between PF0(has ctrl func) and other PF,and provide
basic interaction channels.
6. Common Layer
Provides fundamental services
Signed-off-by: illusion.wang <illusion.wang@nebula-matrix.com>
---
.../net/ethernet/nebula-matrix/nbl/Makefile | 7 +-
.../nbl/nbl_channel/nbl_channel.c | 78 +++++++
.../nbl/nbl_channel/nbl_channel.h | 29 +++
.../net/ethernet/nebula-matrix/nbl/nbl_core.h | 43 ++++
.../nebula-matrix/nbl/nbl_core/nbl_dev.c | 56 +++++
.../nebula-matrix/nbl/nbl_core/nbl_dev.h | 27 +++
.../nebula-matrix/nbl/nbl_core/nbl_dispatch.c | 78 +++++++
.../nebula-matrix/nbl/nbl_core/nbl_dispatch.h | 25 +++
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 144 +++++++++++++
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h | 14 ++
.../nbl_hw_leonis/nbl_resource_leonis.c | 87 ++++++++
.../nbl_hw_leonis/nbl_resource_leonis.h | 10 +
.../nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h | 73 +++++++
.../nebula-matrix/nbl/nbl_hw/nbl_resource.h | 31 +++
.../nbl/nbl_include/nbl_def_channel.h | 26 +++
.../nbl/nbl_include/nbl_def_common.h | 34 ++++
.../nbl/nbl_include/nbl_def_dev.h | 16 ++
.../nbl/nbl_include/nbl_def_dispatch.h | 29 +++
.../nbl/nbl_include/nbl_def_hw.h | 22 ++
.../nbl/nbl_include/nbl_def_resource.h | 22 ++
.../nbl/nbl_include/nbl_include.h | 16 ++
.../nbl/nbl_include/nbl_product_base.h | 19 ++
.../net/ethernet/nebula-matrix/nbl/nbl_main.c | 192 +++++++++++++++++-
23 files changed, 1076 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dev.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_product_base.h
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
index b90fba239401..271605920396 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile
+++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
@@ -3,4 +3,9 @@
obj-$(CONFIG_NBL) := nbl.o
-nbl-objs += nbl_main.o
+nbl-objs += nbl_channel/nbl_channel.o \
+ nbl_hw/nbl_hw_leonis/nbl_hw_leonis.o \
+ nbl_hw/nbl_hw_leonis/nbl_resource_leonis.o \
+ nbl_core/nbl_dispatch.o \
+ nbl_core/nbl_dev.o \
+ nbl_main.o
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
new file mode 100644
index 000000000000..c7689f0e4029
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#include <linux/device.h>
+#include <linux/pci.h>
+#include "nbl_channel.h"
+
+static struct nbl_channel_ops chan_ops = {
+};
+
+static struct nbl_channel_mgt *
+nbl_chan_setup_chan_mgt(struct nbl_adapter *adapter)
+{
+ struct nbl_hw_ops_tbl *hw_ops_tbl = adapter->intf.hw_ops_tbl;
+ struct nbl_common_info *common = &adapter->common;
+ struct device *dev = &adapter->pdev->dev;
+ struct nbl_channel_mgt *chan_mgt;
+ struct nbl_chan_info *mailbox;
+
+ chan_mgt = devm_kzalloc(dev, sizeof(*chan_mgt), GFP_KERNEL);
+ if (!chan_mgt)
+ return ERR_PTR(-ENOMEM);
+
+ chan_mgt->common = common;
+ chan_mgt->hw_ops_tbl = hw_ops_tbl;
+
+ mailbox = devm_kzalloc(dev, sizeof(*mailbox), GFP_KERNEL);
+ if (!mailbox)
+ return ERR_PTR(-ENOMEM);
+ mailbox->chan_type = NBL_CHAN_TYPE_MAILBOX;
+ chan_mgt->chan_info[NBL_CHAN_TYPE_MAILBOX] = mailbox;
+
+ return chan_mgt;
+}
+
+static struct nbl_channel_ops_tbl *
+nbl_chan_setup_ops(struct device *dev, struct nbl_channel_mgt *chan_mgt)
+{
+ struct nbl_channel_ops_tbl *chan_ops_tbl;
+
+ chan_ops_tbl = devm_kzalloc(dev, sizeof(*chan_ops_tbl), GFP_KERNEL);
+ if (!chan_ops_tbl)
+ return ERR_PTR(-ENOMEM);
+
+ chan_ops_tbl->ops = &chan_ops;
+ chan_ops_tbl->priv = chan_mgt;
+
+ return chan_ops_tbl;
+}
+
+int nbl_chan_init_common(struct nbl_adapter *adap)
+{
+ struct nbl_channel_ops_tbl *chan_ops_tbl;
+ struct device *dev = &adap->pdev->dev;
+ struct nbl_channel_mgt *chan_mgt;
+ int ret;
+
+ chan_mgt = nbl_chan_setup_chan_mgt(adap);
+ if (IS_ERR(chan_mgt)) {
+ ret = PTR_ERR(chan_mgt);
+ return ret;
+ }
+
+ chan_ops_tbl = nbl_chan_setup_ops(dev, chan_mgt);
+ if (IS_ERR(chan_ops_tbl)) {
+ ret = PTR_ERR(chan_ops_tbl);
+ return ret;
+ }
+ adap->intf.channel_ops_tbl = chan_ops_tbl;
+ adap->core.chan_mgt = chan_mgt;
+ return 0;
+}
+
+void nbl_chan_remove_common(struct nbl_adapter *adap)
+{
+}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h
new file mode 100644
index 000000000000..637912d1e806
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_CHANNEL_H_
+#define _NBL_CHANNEL_H_
+
+#include <linux/types.h>
+
+#include "../nbl_include/nbl_include.h"
+#include "../nbl_include/nbl_product_base.h"
+#include "../nbl_include/nbl_def_channel.h"
+#include "../nbl_include/nbl_def_hw.h"
+#include "../nbl_include/nbl_def_common.h"
+#include "../nbl_core.h"
+
+struct nbl_chan_info {
+ u8 chan_type;
+};
+
+struct nbl_channel_mgt {
+ struct nbl_common_info *common;
+ struct nbl_hw_ops_tbl *hw_ops_tbl;
+ struct nbl_chan_info *chan_info[NBL_CHAN_TYPE_MAX];
+ struct nbl_hash_tbl_mgt *handle_hash_tbl;
+};
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h
index d5136b13c490..628d5b15f19f 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h
@@ -6,10 +6,53 @@
#ifndef _NBL_CORE_H_
#define _NBL_CORE_H_
+#include <linux/pci.h>
+#include "nbl_include/nbl_include.h"
+#include "nbl_include/nbl_def_common.h"
+
+struct nbl_hw_mgt;
+struct nbl_hw_ops_tbl;
+struct nbl_resource_mgt;
+struct nbl_resource_ops_tbl;
+struct nbl_dispatch_mgt;
+struct nbl_dispatch_ops_tbl;
+struct nbl_channel_ops_tbl;
+struct nbl_channel_mgt;
+struct nbl_dev_mgt;
+
enum {
NBL_CAP_HAS_CTRL_BIT,
NBL_CAP_HAS_NET_BIT,
NBL_CAP_IS_LEONIS_BIT,
};
+struct nbl_interface {
+ struct nbl_hw_ops_tbl *hw_ops_tbl;
+ struct nbl_resource_ops_tbl *resource_ops_tbl;
+ struct nbl_dispatch_ops_tbl *dispatch_ops_tbl;
+ struct nbl_channel_ops_tbl *channel_ops_tbl;
+};
+
+struct nbl_core {
+ struct nbl_hw_mgt *hw_mgt;
+ struct nbl_resource_mgt *res_mgt;
+ struct nbl_dispatch_mgt *disp_mgt;
+ struct nbl_dev_mgt *dev_mgt;
+ struct nbl_channel_mgt *chan_mgt;
+};
+
+struct nbl_adapter {
+ struct pci_dev *pdev;
+ struct nbl_core core;
+ struct nbl_interface intf;
+ struct nbl_common_info common;
+ struct nbl_product_base_ops *product_base_ops;
+};
+
+struct nbl_adapter *nbl_core_init(struct pci_dev *pdev,
+ struct nbl_init_param *param);
+void nbl_core_remove(struct nbl_adapter *adapter);
+int nbl_core_start(struct nbl_adapter *adapter);
+void nbl_core_stop(struct nbl_adapter *adapter);
+
#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c
new file mode 100644
index 000000000000..5deb21e35f8e
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+#include <linux/device.h>
+#include <linux/pci.h>
+#include "nbl_dev.h"
+
+static struct nbl_dev_mgt *nbl_dev_setup_dev_mgt(struct nbl_common_info *common)
+{
+ struct nbl_dev_mgt *dev_mgt;
+
+ dev_mgt = devm_kzalloc(common->dev, sizeof(*dev_mgt), GFP_KERNEL);
+ if (!dev_mgt)
+ return ERR_PTR(-ENOMEM);
+
+ dev_mgt->common = common;
+ return dev_mgt;
+}
+
+int nbl_dev_init(struct nbl_adapter *adapter)
+{
+ struct nbl_common_info *common = &adapter->common;
+ struct nbl_dispatch_ops_tbl *disp_ops_tbl =
+ adapter->intf.dispatch_ops_tbl;
+ struct nbl_channel_ops_tbl *chan_ops_tbl =
+ adapter->intf.channel_ops_tbl;
+ struct nbl_dev_mgt *dev_mgt;
+ int ret;
+
+ dev_mgt = nbl_dev_setup_dev_mgt(common);
+ if (IS_ERR(dev_mgt)) {
+ ret = PTR_ERR(dev_mgt);
+ return ret;
+ }
+
+ dev_mgt->disp_ops_tbl = disp_ops_tbl;
+ dev_mgt->chan_ops_tbl = chan_ops_tbl;
+ adapter->core.dev_mgt = dev_mgt;
+
+ return 0;
+}
+
+void nbl_dev_remove(struct nbl_adapter *adapter)
+{
+}
+
+/* ---------- Dev start process ---------- */
+int nbl_dev_start(struct nbl_adapter *adapter)
+{
+ return 0;
+}
+
+void nbl_dev_stop(struct nbl_adapter *adapter)
+{
+}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h
new file mode 100644
index 000000000000..9b71092b99a0
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_DEV_H_
+#define _NBL_DEV_H_
+
+#include <linux/types.h>
+
+#include "../nbl_include/nbl_include.h"
+#include "../nbl_include/nbl_product_base.h"
+#include "../nbl_include/nbl_def_channel.h"
+#include "../nbl_include/nbl_def_hw.h"
+#include "../nbl_include/nbl_def_resource.h"
+#include "../nbl_include/nbl_def_dispatch.h"
+#include "../nbl_include/nbl_def_dev.h"
+#include "../nbl_include/nbl_def_common.h"
+#include "../nbl_core.h"
+
+struct nbl_dev_mgt {
+ struct nbl_common_info *common;
+ struct nbl_dispatch_ops_tbl *disp_ops_tbl;
+ struct nbl_channel_ops_tbl *chan_ops_tbl;
+};
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c
new file mode 100644
index 000000000000..f0b4406ca560
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+#include <linux/device.h>
+#include <linux/pci.h>
+#include "nbl_dispatch.h"
+
+static struct nbl_dispatch_mgt *
+nbl_disp_setup_disp_mgt(struct nbl_common_info *common)
+{
+ struct nbl_dispatch_mgt *disp_mgt;
+ struct device *dev = common->dev;
+
+ disp_mgt = devm_kzalloc(dev, sizeof(*disp_mgt), GFP_KERNEL);
+ if (!disp_mgt)
+ return ERR_PTR(-ENOMEM);
+
+ disp_mgt->common = common;
+ return disp_mgt;
+}
+
+static struct nbl_dispatch_ops_tbl *
+nbl_disp_setup_ops(struct device *dev, struct nbl_dispatch_mgt *disp_mgt)
+{
+ struct nbl_dispatch_ops_tbl *disp_ops_tbl;
+ struct nbl_dispatch_ops *disp_ops;
+
+ disp_ops_tbl = devm_kzalloc(dev, sizeof(*disp_ops_tbl), GFP_KERNEL);
+ if (!disp_ops_tbl)
+ return ERR_PTR(-ENOMEM);
+
+ disp_ops = devm_kzalloc(dev, sizeof(*disp_ops), GFP_KERNEL);
+ if (!disp_ops)
+ return ERR_PTR(-ENOMEM);
+
+ disp_ops_tbl->ops = disp_ops;
+ disp_ops_tbl->priv = disp_mgt;
+
+ return disp_ops_tbl;
+}
+
+int nbl_disp_init(struct nbl_adapter *adapter)
+{
+ struct nbl_common_info *common = &adapter->common;
+ struct nbl_dispatch_ops_tbl *disp_ops_tbl;
+ struct nbl_resource_ops_tbl *res_ops_tbl =
+ adapter->intf.resource_ops_tbl;
+ struct nbl_channel_ops_tbl *chan_ops_tbl =
+ adapter->intf.channel_ops_tbl;
+ struct device *dev = &adapter->pdev->dev;
+ struct nbl_dispatch_mgt *disp_mgt;
+ int ret;
+
+ disp_mgt = nbl_disp_setup_disp_mgt(common);
+ if (IS_ERR(disp_mgt)) {
+ ret = PTR_ERR(disp_mgt);
+ return ret;
+ }
+
+ disp_ops_tbl = nbl_disp_setup_ops(dev, disp_mgt);
+ if (IS_ERR(disp_ops_tbl)) {
+ ret = PTR_ERR(disp_ops_tbl);
+ return ret;
+ }
+
+ disp_mgt->res_ops_tbl = res_ops_tbl;
+ disp_mgt->chan_ops_tbl = chan_ops_tbl;
+ disp_mgt->disp_ops_tbl = disp_ops_tbl;
+ adapter->core.disp_mgt = disp_mgt;
+ adapter->intf.dispatch_ops_tbl = disp_ops_tbl;
+
+ return 0;
+}
+
+void nbl_disp_remove(struct nbl_adapter *adapter)
+{
+}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h
new file mode 100644
index 000000000000..fa7f4597febe
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_DISPATCH_H_
+#define _NBL_DISPATCH_H_
+#include "../nbl_include/nbl_include.h"
+#include "../nbl_include/nbl_product_base.h"
+#include "../nbl_include/nbl_def_channel.h"
+#include "../nbl_include/nbl_def_hw.h"
+#include "../nbl_include/nbl_def_resource.h"
+#include "../nbl_include/nbl_def_dispatch.h"
+#include "../nbl_include/nbl_def_common.h"
+#include "../nbl_core.h"
+
+struct nbl_dispatch_mgt {
+ struct nbl_common_info *common;
+ struct nbl_resource_ops_tbl *res_ops_tbl;
+ struct nbl_channel_ops_tbl *chan_ops_tbl;
+ struct nbl_dispatch_ops_tbl *disp_ops_tbl;
+ DECLARE_BITMAP(ctrl_lvl, NBL_DISP_CTRL_LVL_MAX);
+};
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
new file mode 100644
index 000000000000..08ddbf5b0eb2
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+#include <linux/device.h>
+#include <linux/pci.h>
+#include <linux/bits.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include "nbl_hw_leonis.h"
+
+static struct nbl_hw_ops hw_ops = {
+};
+
+/* Structure starts here, adding an op should not modify anything below */
+static struct nbl_hw_mgt *nbl_hw_setup_hw_mgt(struct nbl_common_info *common)
+{
+ struct device *dev = common->dev;
+ struct nbl_hw_mgt *hw_mgt;
+
+ hw_mgt = devm_kzalloc(dev, sizeof(*hw_mgt), GFP_KERNEL);
+ if (!hw_mgt)
+ return ERR_PTR(-ENOMEM);
+
+ hw_mgt->common = common;
+
+ return hw_mgt;
+}
+
+static struct nbl_hw_ops_tbl *nbl_hw_setup_ops(struct nbl_common_info *common,
+ struct nbl_hw_mgt *hw_mgt)
+{
+ struct nbl_hw_ops_tbl *hw_ops_tbl;
+ struct device *dev;
+
+ dev = common->dev;
+ hw_ops_tbl = devm_kzalloc(dev, sizeof(*hw_ops_tbl), GFP_KERNEL);
+ if (!hw_ops_tbl)
+ return ERR_PTR(-ENOMEM);
+
+ hw_ops_tbl->ops = &hw_ops;
+ hw_ops_tbl->priv = hw_mgt;
+
+ return hw_ops_tbl;
+}
+
+int nbl_hw_init_leonis(struct nbl_adapter *adapter)
+{
+ struct nbl_common_info *common = &adapter->common;
+ struct pci_dev *pdev = common->pdev;
+ struct nbl_hw_ops_tbl *hw_ops_tbl;
+ struct nbl_hw_mgt *hw_mgt;
+ resource_size_t bar_start;
+ resource_size_t bar_len;
+ int bar_mask;
+ int ret;
+
+ hw_mgt = nbl_hw_setup_hw_mgt(common);
+ if (IS_ERR(hw_mgt)) {
+ ret = PTR_ERR(hw_mgt);
+ goto setup_mgt_fail;
+ }
+ bar_mask = BIT(NBL_MEMORY_BAR) | BIT(NBL_MAILBOX_BAR);
+ ret = pci_request_selected_regions(pdev, bar_mask, NBL_DRIVER_NAME);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Request memory bar and mailbox bar failed, err = %d\n",
+ ret);
+ goto request_bar_region_fail;
+ }
+
+ bar_len = pci_resource_len(pdev, NBL_MEMORY_BAR);
+ bar_start = pci_resource_start(pdev, NBL_MEMORY_BAR);
+ if (!(pci_resource_flags(pdev, NBL_MEMORY_BAR) & IORESOURCE_MEM) ||
+ bar_len < NBL_RDMA_NOTIFY_OFF) {
+ dev_err(&pdev->dev,
+ "Invalid BAR: unassigned or length too small\n");
+ ret = -EINVAL;
+ goto ioremap_err;
+ }
+ if (common->has_ctrl) {
+ if (bar_len < NBL_HW_REG_SPACE_SIZE) {
+ dev_err(&pdev->dev,
+ "Invalid BAR: unassigned or length too small\n");
+ ret = -EINVAL;
+ goto ioremap_err;
+ }
+ hw_mgt->hw_addr =
+ ioremap(bar_start, bar_len - NBL_RDMA_NOTIFY_OFF);
+ hw_mgt->hw_size = bar_len - NBL_RDMA_NOTIFY_OFF;
+ } else {
+ hw_mgt->hw_addr = ioremap(bar_start, NBL_RDMA_NOTIFY_OFF);
+ hw_mgt->hw_size = NBL_RDMA_NOTIFY_OFF;
+ }
+ if (!hw_mgt->hw_addr) {
+ dev_err(&pdev->dev, "Memory bar ioremap failed\n");
+ ret = -EIO;
+ goto ioremap_err;
+ }
+
+ hw_mgt->mailbox_bar_hw_addr = pci_ioremap_bar(pdev, NBL_MAILBOX_BAR);
+ if (!hw_mgt->mailbox_bar_hw_addr) {
+ dev_err(&pdev->dev, "Mailbox bar ioremap failed\n");
+ ret = -EIO;
+ goto mailbox_ioremap_err;
+ }
+
+ hw_ops_tbl = nbl_hw_setup_ops(common, hw_mgt);
+ if (IS_ERR(hw_ops_tbl)) {
+ ret = PTR_ERR(hw_ops_tbl);
+ goto setup_ops_fail;
+ }
+ hw_mgt->notify_offset = 0;
+ adapter->intf.hw_ops_tbl = hw_ops_tbl;
+ adapter->core.hw_mgt = hw_mgt;
+
+ return 0;
+
+setup_ops_fail:
+ iounmap(hw_mgt->mailbox_bar_hw_addr);
+mailbox_ioremap_err:
+ iounmap(hw_mgt->hw_addr);
+ioremap_err:
+ pci_release_selected_regions(pdev, bar_mask);
+request_bar_region_fail:
+setup_mgt_fail:
+ return ret;
+}
+
+void nbl_hw_remove_leonis(struct nbl_adapter *adapter)
+{
+ int bar_mask = BIT(NBL_MEMORY_BAR) | BIT(NBL_MAILBOX_BAR);
+ struct nbl_common_info *common = &adapter->common;
+ struct nbl_hw_mgt *hw_mgt = adapter->core.hw_mgt;
+ u8 __iomem *hw_addr = hw_mgt->hw_addr;
+ struct pci_dev *pdev = common->pdev;
+ u8 __iomem *mailbox_bar_hw_addr;
+
+ mailbox_bar_hw_addr = hw_mgt->mailbox_bar_hw_addr;
+
+ iounmap(mailbox_bar_hw_addr);
+ iounmap(hw_addr);
+ pci_release_selected_regions(pdev, bar_mask);
+}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
new file mode 100644
index 000000000000..77c67b67ba31
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_HW_LEONIS_H_
+#define _NBL_HW_LEONIS_H_
+
+#include <linux/types.h>
+
+#include "../../nbl_include/nbl_include.h"
+#include "../nbl_hw_reg.h"
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c
new file mode 100644
index 000000000000..4b4f8e2e7fe7
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+#include <linux/device.h>
+#include <linux/pci.h>
+#include "nbl_resource_leonis.h"
+
+static struct nbl_resource_ops res_ops = {
+};
+
+static struct nbl_resource_mgt *
+nbl_res_setup_res_mgt(struct nbl_common_info *common)
+{
+ struct nbl_resource_info *resource_info;
+ struct nbl_resource_mgt *res_mgt;
+ struct device *dev = common->dev;
+
+ res_mgt = devm_kzalloc(dev, sizeof(*res_mgt), GFP_KERNEL);
+ if (!res_mgt)
+ return ERR_PTR(-ENOMEM);
+ res_mgt->common = common;
+
+ resource_info =
+ devm_kzalloc(dev, sizeof(*resource_info), GFP_KERNEL);
+ if (!resource_info)
+ return ERR_PTR(-ENOMEM);
+ res_mgt->resource_info = resource_info;
+
+ return res_mgt;
+}
+
+static struct nbl_resource_ops_tbl *
+nbl_res_setup_ops(struct device *dev, struct nbl_resource_mgt *res_mgt)
+{
+ struct nbl_resource_ops_tbl *res_ops_tbl;
+
+ res_ops_tbl = devm_kzalloc(dev, sizeof(*res_ops_tbl), GFP_KERNEL);
+ if (!res_ops_tbl)
+ return ERR_PTR(-ENOMEM);
+
+ res_ops_tbl->ops = &res_ops;
+ res_ops_tbl->priv = res_mgt;
+
+ return res_ops_tbl;
+}
+
+static int nbl_res_start(struct nbl_resource_mgt *res_mgt)
+{
+ return 0;
+}
+
+int nbl_res_init_leonis(struct nbl_adapter *adap)
+{
+ struct nbl_channel_ops_tbl *chan_ops_tbl = adap->intf.channel_ops_tbl;
+ struct nbl_hw_ops_tbl *hw_ops_tbl = adap->intf.hw_ops_tbl;
+ struct nbl_common_info *common = &adap->common;
+ struct nbl_resource_ops_tbl *res_ops_tbl;
+ struct device *dev = &adap->pdev->dev;
+ struct nbl_resource_mgt *res_mgt;
+ int ret;
+
+ res_mgt = nbl_res_setup_res_mgt(common);
+ if (IS_ERR(res_mgt)) {
+ ret = PTR_ERR(res_mgt);
+ return ret;
+ }
+ res_mgt->chan_ops_tbl = chan_ops_tbl;
+ res_mgt->hw_ops_tbl = hw_ops_tbl;
+
+ ret = nbl_res_start(res_mgt);
+ if (ret)
+ return ret;
+
+ res_ops_tbl = nbl_res_setup_ops(dev, res_mgt);
+ if (IS_ERR(res_ops_tbl)) {
+ ret = PTR_ERR(res_ops_tbl);
+ return ret;
+ }
+ adap->intf.resource_ops_tbl = res_ops_tbl;
+ adap->core.res_mgt = res_mgt;
+ return 0;
+}
+
+void nbl_res_remove_leonis(struct nbl_adapter *adap)
+{
+}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.h
new file mode 100644
index 000000000000..4e61a5c141e5
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_RESOURCE_LEONIS_H_
+#define _NBL_RESOURCE_LEONIS_H_
+
+#include "../nbl_resource.h"
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h
new file mode 100644
index 000000000000..1828251e8c2a
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_HW_REG_H_
+#define _NBL_HW_REG_H_
+
+#include <linux/types.h>
+
+#include "../nbl_include/nbl_product_base.h"
+#include "../nbl_include/nbl_def_channel.h"
+#include "../nbl_include/nbl_def_hw.h"
+#include "../nbl_include/nbl_def_common.h"
+#include "../nbl_core.h"
+
+#define NBL_MEMORY_BAR 0
+#define NBL_MAILBOX_BAR 2
+#define NBL_RDMA_NOTIFY_OFF 8192
+#define NBL_HW_DUMMY_REG 0x1300904
+#define NBL_HW_REG_SPACE_SIZE (32 * 1024 * 1024)
+
+struct nbl_hw_mgt {
+ struct nbl_common_info *common;
+ u8 __iomem *hw_addr;
+ u8 __iomem *mailbox_bar_hw_addr;
+ u64 notify_offset;
+ resource_size_t hw_size;
+};
+
+static inline u32 rd32(u8 __iomem *addr, u64 reg)
+{
+ return readl(addr + reg);
+}
+
+static inline void wr32(u8 __iomem *addr, u64 reg, u32 value)
+{
+ writel(value, addr + reg);
+}
+
+static inline void nbl_hw_wr32(struct nbl_hw_mgt *hw_mgt, u64 reg, u32 value)
+{
+ /* Used for emu, make sure that we won't write too frequently */
+ wr32(hw_mgt->hw_addr, reg, value);
+}
+
+static inline u32 nbl_hw_rd32(struct nbl_hw_mgt *hw_mgt, u64 reg)
+{
+ return rd32(hw_mgt->hw_addr, reg);
+}
+
+static inline void nbl_mbx_wr32(struct nbl_hw_mgt *hw_mgt, u64 reg, u32 value)
+{
+ writel(value, hw_mgt->mailbox_bar_hw_addr + reg);
+}
+
+/*
+ * Only call this when has_ctrl=true, which maps enough space
+ * (bar_len - 8192) to cover NBL_HW_DUMMY_REG (0x1300904).
+ * The flow/design guarantees this is only called in the
+ * has_ctrl path.
+ */
+static inline void nbl_flush_writes(struct nbl_hw_mgt *hw_mgt)
+{
+ nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG);
+}
+
+static inline u32 nbl_mbx_rd32(struct nbl_hw_mgt *hw_mgt, u64 reg)
+{
+ return readl(hw_mgt->mailbox_bar_hw_addr + reg);
+}
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h
new file mode 100644
index 000000000000..5bfd0ddd1cec
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_RESOURCE_H_
+#define _NBL_RESOURCE_H_
+
+#include <linux/types.h>
+
+#include "../nbl_include/nbl_include.h"
+#include "../nbl_include/nbl_product_base.h"
+#include "../nbl_include/nbl_def_channel.h"
+#include "../nbl_include/nbl_def_hw.h"
+#include "../nbl_include/nbl_def_resource.h"
+#include "../nbl_include/nbl_def_common.h"
+#include "../nbl_core.h"
+
+struct nbl_resource_info {
+ void *reserved; /* placeholder to be replaced in the future*/
+};
+
+struct nbl_resource_mgt {
+ struct nbl_common_info *common;
+ struct nbl_resource_info *resource_info;
+ struct nbl_channel_ops_tbl *chan_ops_tbl;
+ struct nbl_hw_ops_tbl *hw_ops_tbl;
+ struct nbl_interrupt_mgt *intr_mgt;
+};
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
new file mode 100644
index 000000000000..ff03a53b9f5d
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_DEF_CHANNEL_H_
+#define _NBL_DEF_CHANNEL_H_
+
+struct nbl_channel_mgt;
+struct nbl_adapter;
+enum nbl_channel_type {
+ NBL_CHAN_TYPE_MAILBOX,
+ NBL_CHAN_TYPE_MAX
+};
+
+struct nbl_channel_ops {
+};
+
+struct nbl_channel_ops_tbl {
+ struct nbl_channel_ops *ops;
+ struct nbl_channel_mgt *priv;
+};
+
+int nbl_chan_init_common(struct nbl_adapter *adapter);
+void nbl_chan_remove_common(struct nbl_adapter *adapter);
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
new file mode 100644
index 000000000000..03c19e1c8c3c
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_DEF_COMMON_H_
+#define _NBL_DEF_COMMON_H_
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/device.h>
+#include "nbl_include.h"
+
+struct nbl_common_info {
+ struct pci_dev *pdev;
+ struct device *dev;
+ u32 msg_enable;
+ u16 vsi_id;
+ u8 eth_id;
+ u8 logic_eth_id;
+ u8 eth_num;
+
+ u8 function;
+ u8 devid;
+ u8 bus;
+ u8 hw_bus;
+ u16 mgt_pf;
+
+ enum nbl_product_type product_type;
+ u8 has_ctrl;
+ u8 has_net;
+};
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dev.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dev.h
new file mode 100644
index 000000000000..32e6cce38d39
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dev.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_DEF_DEV_H_
+#define _NBL_DEF_DEV_H_
+
+struct nbl_adapter;
+
+int nbl_dev_init(struct nbl_adapter *adapter);
+void nbl_dev_remove(struct nbl_adapter *adapter);
+int nbl_dev_start(struct nbl_adapter *adapter);
+void nbl_dev_stop(struct nbl_adapter *adapter);
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h
new file mode 100644
index 000000000000..53492b044f79
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_DEF_DISPATCH_H_
+#define _NBL_DEF_DISPATCH_H_
+
+struct nbl_dispatch_mgt;
+struct nbl_adapter;
+enum {
+ NBL_DISP_CTRL_LVL_NEVER = 0,
+ NBL_DISP_CTRL_LVL_MGT,
+ NBL_DISP_CTRL_LVL_NET,
+ NBL_DISP_CTRL_LVL_MAX,
+};
+
+struct nbl_dispatch_ops {
+ void *reserved; /* placeholder to be replaced in the future*/
+};
+
+struct nbl_dispatch_ops_tbl {
+ struct nbl_dispatch_ops *ops;
+ struct nbl_dispatch_mgt *priv;
+};
+
+int nbl_disp_init(struct nbl_adapter *adapter);
+void nbl_disp_remove(struct nbl_adapter *adapter);
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h
new file mode 100644
index 000000000000..168504b30973
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_DEF_HW_H_
+#define _NBL_DEF_HW_H_
+
+struct nbl_hw_mgt;
+struct nbl_adapter;
+struct nbl_hw_ops {
+};
+
+struct nbl_hw_ops_tbl {
+ struct nbl_hw_ops *ops;
+ struct nbl_hw_mgt *priv;
+};
+
+int nbl_hw_init_leonis(struct nbl_adapter *adapter);
+void nbl_hw_remove_leonis(struct nbl_adapter *adapter);
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h
new file mode 100644
index 000000000000..d55934af5a9a
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_DEF_RESOURCE_H_
+#define _NBL_DEF_RESOURCE_H_
+
+struct nbl_resource_mgt;
+struct nbl_adapter;
+
+struct nbl_resource_ops {
+};
+
+struct nbl_resource_ops_tbl {
+ struct nbl_resource_ops *ops;
+ struct nbl_resource_mgt *priv;
+};
+
+int nbl_res_init_leonis(struct nbl_adapter *adapter);
+void nbl_res_remove_leonis(struct nbl_adapter *adapter);
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
index cd99f96e1568..3f7d4c24c29c 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
@@ -11,4 +11,20 @@
/* ------ Basic definitions ------- */
#define NBL_DRIVER_NAME "nbl"
+enum nbl_product_type {
+ NBL_LEONIS_TYPE,
+ NBL_PRODUCT_MAX,
+};
+
+struct nbl_func_caps {
+ u32 has_ctrl:1;
+ u32 has_net:1;
+ u32 rsv:30;
+};
+
+struct nbl_init_param {
+ struct nbl_func_caps caps;
+ enum nbl_product_type product_type;
+};
+
#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_product_base.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_product_base.h
new file mode 100644
index 000000000000..fe4245d0ca99
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_product_base.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_DEF_PRODUCT_BASE_H_
+#define _NBL_DEF_PRODUCT_BASE_H_
+
+struct nbl_adapter;
+struct nbl_product_base_ops {
+ int (*hw_init)(struct nbl_adapter *p);
+ void (*hw_remove)(struct nbl_adapter *p);
+ int (*res_init)(struct nbl_adapter *p);
+ void (*res_remove)(struct nbl_adapter *p);
+ int (*chan_init)(struct nbl_adapter *p);
+ void (*chan_remove)(struct nbl_adapter *p);
+};
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c
index d931c6a40e6c..dc963e805c66 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c
@@ -6,17 +6,207 @@
#include <linux/device.h>
#include <linux/pci.h>
#include <linux/module.h>
+#include <linux/bits.h>
#include "nbl_include/nbl_include.h"
+#include "nbl_include/nbl_product_base.h"
+#include "nbl_include/nbl_def_channel.h"
+#include "nbl_include/nbl_def_hw.h"
+#include "nbl_include/nbl_def_resource.h"
+#include "nbl_include/nbl_def_dispatch.h"
+#include "nbl_include/nbl_def_dev.h"
+#include "nbl_include/nbl_def_common.h"
#include "nbl_core.h"
+static struct nbl_product_base_ops nbl_product_base_ops[NBL_PRODUCT_MAX] = {
+ {
+ .hw_init = nbl_hw_init_leonis,
+ .hw_remove = nbl_hw_remove_leonis,
+ .res_init = nbl_res_init_leonis,
+ .res_remove = nbl_res_remove_leonis,
+ .chan_init = nbl_chan_init_common,
+ .chan_remove = nbl_chan_remove_common,
+ },
+};
+
+int nbl_core_start(struct nbl_adapter *adapter)
+{
+ return nbl_dev_start(adapter);
+}
+
+void nbl_core_stop(struct nbl_adapter *adapter)
+{
+ nbl_dev_stop(adapter);
+}
+
+static struct nbl_product_base_ops *
+nbl_core_setup_product_ops(struct nbl_adapter *adapter,
+ struct nbl_init_param *param)
+{
+ if (param->product_type >= NBL_PRODUCT_MAX) {
+ dev_err(&adapter->pdev->dev, "Unsupported product type\n");
+ return NULL;
+ }
+ adapter->product_base_ops = &nbl_product_base_ops[param->product_type];
+ return adapter->product_base_ops;
+}
+
+struct nbl_adapter *nbl_core_init(struct pci_dev *pdev,
+ struct nbl_init_param *param)
+{
+ struct nbl_product_base_ops *product_base_ops;
+ struct nbl_common_info *common;
+ struct nbl_adapter *adapter;
+ int ret;
+
+ adapter = devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL);
+ if (!adapter)
+ return ERR_PTR(-ENOMEM);
+
+ adapter->pdev = pdev;
+ common = &adapter->common;
+
+ common->pdev = pdev;
+ common->dev = &pdev->dev;
+ common->has_ctrl = param->caps.has_ctrl;
+ common->has_net = param->caps.has_net;
+ common->function = PCI_FUNC(pdev->devfn);
+ common->devid = PCI_SLOT(pdev->devfn);
+ common->bus = pdev->bus->number;
+ common->product_type = param->product_type;
+
+ product_base_ops = nbl_core_setup_product_ops(adapter, param);
+ if (!product_base_ops)
+ return ERR_PTR(-ENOENT);
+ /*
+ *every product's hw/chan/res layer has a great difference,
+ *so call their own init ops
+ */
+ ret = product_base_ops->hw_init(adapter);
+ if (ret)
+ goto hw_init_fail;
+
+ ret = product_base_ops->chan_init(adapter);
+ if (ret)
+ goto chan_init_fail;
+
+ ret = product_base_ops->res_init(adapter);
+ if (ret)
+ goto res_init_fail;
+
+ ret = nbl_disp_init(adapter);
+ if (ret)
+ goto disp_init_fail;
+
+ ret = nbl_dev_init(adapter);
+ if (ret)
+ goto dev_init_fail;
+ return adapter;
+
+dev_init_fail:
+ nbl_disp_remove(adapter);
+disp_init_fail:
+ product_base_ops->res_remove(adapter);
+res_init_fail:
+ product_base_ops->chan_remove(adapter);
+chan_init_fail:
+ product_base_ops->hw_remove(adapter);
+hw_init_fail:
+ return ERR_PTR(ret);
+}
+
+void nbl_core_remove(struct nbl_adapter *adapter)
+{
+ struct nbl_product_base_ops *product_base_ops;
+
+ product_base_ops = adapter->product_base_ops;
+ nbl_dev_remove(adapter);
+ nbl_disp_remove(adapter);
+ product_base_ops->res_remove(adapter);
+ product_base_ops->chan_remove(adapter);
+ product_base_ops->hw_remove(adapter);
+}
+
+static void nbl_get_func_param(struct pci_dev *pdev, kernel_ulong_t driver_data,
+ struct nbl_init_param *param)
+{
+ param->caps.has_ctrl = !!(driver_data & BIT(NBL_CAP_HAS_CTRL_BIT));
+ param->caps.has_net = !!(driver_data & BIT(NBL_CAP_HAS_NET_BIT));
+
+ if (!!(driver_data & BIT(NBL_CAP_IS_LEONIS_BIT)))
+ param->product_type = NBL_LEONIS_TYPE;
+ else
+ param->product_type = NBL_PRODUCT_MAX;
+
+ /*
+ * Leonis only PF0 has ctrl capability, but PF0's pcie device_id
+ * is same with other PF.So handle it special.
+ */
+ if (param->product_type == NBL_LEONIS_TYPE &&
+ (PCI_FUNC(pdev->devfn) == 0) && !pdev->is_virtfn)
+ param->caps.has_ctrl = 1;
+}
+
static int nbl_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
- return -ENODEV;
+ struct nbl_init_param param = { { 0 } };
+ struct device *dev = &pdev->dev;
+ struct nbl_adapter *adapter;
+ int err;
+
+ err = pci_enable_device(pdev);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to enable PCI dev, err=%d\n", err);
+ return err;
+ }
+
+ nbl_get_func_param(pdev, id->driver_data, ¶m);
+
+ err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
+ if (err) {
+ dev_dbg(dev, "Configure DMA 64 bit mask failed, err = %d\n",
+ err);
+ err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
+ if (err) {
+ dev_err(dev,
+ "Configure DMA 32 bit mask failed, err = %d\n",
+ err);
+ goto configure_dma_err;
+ }
+ }
+ pci_set_master(pdev);
+
+ adapter = nbl_core_init(pdev, ¶m);
+ if (IS_ERR(adapter)) {
+ dev_err(dev, "Nbl adapter init fail: %pe\n", adapter);
+ err = PTR_ERR(adapter);
+ goto adapter_init_err;
+ }
+ pci_set_drvdata(pdev, adapter);
+ err = nbl_core_start(adapter);
+ if (err)
+ goto core_start_err;
+
+ return 0;
+core_start_err:
+ pci_set_drvdata(pdev, NULL);
+ nbl_core_remove(adapter);
+adapter_init_err:
+ pci_clear_master(pdev);
+configure_dma_err:
+ pci_disable_device(pdev);
+ return err;
}
static void nbl_remove(struct pci_dev *pdev)
{
+ struct nbl_adapter *adapter = pci_get_drvdata(pdev);
+
+ nbl_core_stop(adapter);
+ nbl_core_remove(adapter);
+
+ pci_clear_master(pdev);
+ pci_disable_device(pdev);
}
/*
--
2.47.3
^ permalink raw reply related
* [PATCH v19 net-next 01/11] net/nebula-matrix: add minimum nbl build framework
From: illusion.wang @ 2026-06-17 4:46 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, horms, linux-doc, pabeni,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
In-Reply-To: <20260617044702.2439-1-illusion.wang@nebula-matrix.com>
1.Add nbl min build infrastructure for nbl driver.
2.Add PCI driver skeleton with empty stubs for nbl driver.
Signed-off-by: illusion.wang <illusion.wang@nebula-matrix.com>
---
.../device_drivers/ethernet/index.rst | 1 +
.../ethernet/nebula-matrix/nbl.rst | 28 +++++
MAINTAINERS | 10 ++
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
drivers/net/ethernet/nebula-matrix/Kconfig | 34 ++++++
drivers/net/ethernet/nebula-matrix/Makefile | 6 +
.../net/ethernet/nebula-matrix/nbl/Makefile | 6 +
.../net/ethernet/nebula-matrix/nbl/nbl_core.h | 15 +++
.../nbl/nbl_include/nbl_include.h | 14 +++
.../net/ethernet/nebula-matrix/nbl/nbl_main.c | 114 ++++++++++++++++++
11 files changed, 230 insertions(+)
create mode 100644 Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst
create mode 100644 drivers/net/ethernet/nebula-matrix/Kconfig
create mode 100644 drivers/net/ethernet/nebula-matrix/Makefile
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/Makefile
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c
diff --git a/Documentation/networking/device_drivers/ethernet/index.rst b/Documentation/networking/device_drivers/ethernet/index.rst
index 786a23c84b90..4d74b954b0ba 100644
--- a/Documentation/networking/device_drivers/ethernet/index.rst
+++ b/Documentation/networking/device_drivers/ethernet/index.rst
@@ -47,6 +47,7 @@ Contents:
meta/fbnic
microsoft/netvsc
mucse/rnpgbe
+ nebula-matrix/nbl
netronome/nfp
pensando/ionic
pensando/ionic_rdma
diff --git a/Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst b/Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst
new file mode 100644
index 000000000000..95b7ef4ee6dc
--- /dev/null
+++ b/Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst
@@ -0,0 +1,28 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+================================================================
+Linux Base Driver for Nebula-matrix m18110-NIC/m18000-NIC family
+================================================================
+
+Overview:
+=========
+The m18110-NIC/m18000-NIC is a series of network interface cards for the Data
+Center Area.
+
+The driver supports link-speed 100GbE/25GE/10GE.
+
+m18110-NIC/m18000-NIC devices support MSI-X interrupt vector for each Tx/Rx
+queue and interrupt moderation.
+
+m18110-NIC/m18000-NIC devices support also various offload features such as
+checksum offload, Receive-Side Scaling(RSS).
+
+Support
+=======
+
+For more information about m18110-NIC/m18000-NIC, please visit the following URL:
+https://www.nebula-matrix.com/
+
+If an issue is identified with the released source code on the supported kernel
+with a supported adapter, email the specific information related to the issue to
+open@nebula-matrix.com.
diff --git a/MAINTAINERS b/MAINTAINERS
index cc1dde0c9067..8e2d477af72d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18389,6 +18389,16 @@ F: Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.yaml
F: Documentation/hwmon/nct7363.rst
F: drivers/hwmon/nct7363.c
+NEBULA-MATRIX ETHERNET DRIVER (nebula-matrix)
+M: Illusion Wang <illusion.wang@nebula-matrix.com>
+M: Dimon Zhao <dimon.zhao@nebula-matrix.com>
+M: Alvin Wang <alvin.wang@nebula-matrix.com>
+M: Sam Chen <sam.chen@nebula-matrix.com>
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/networking/device_drivers/ethernet/nebula-matrix/
+F: drivers/net/ethernet/nebula-matrix/
+
NETCONSOLE
M: Breno Leitao <leitao@debian.org>
S: Maintained
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index 78c79ad7bba5..5c21d02c4e11 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -130,6 +130,7 @@ config FEALNX
source "drivers/net/ethernet/ni/Kconfig"
source "drivers/net/ethernet/natsemi/Kconfig"
+source "drivers/net/ethernet/nebula-matrix/Kconfig"
source "drivers/net/ethernet/netronome/Kconfig"
source "drivers/net/ethernet/8390/Kconfig"
source "drivers/net/ethernet/nvidia/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index bba55d9af387..accce62a79a6 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_NET_VENDOR_MUCSE) += mucse/
obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/
obj-$(CONFIG_FEALNX) += fealnx.o
obj-$(CONFIG_NET_VENDOR_NATSEMI) += natsemi/
+obj-$(CONFIG_NET_VENDOR_NEBULA_MATRIX) += nebula-matrix/
obj-$(CONFIG_NET_VENDOR_NETRONOME) += netronome/
obj-$(CONFIG_NET_VENDOR_NI) += ni/
obj-$(CONFIG_NET_VENDOR_NVIDIA) += nvidia/
diff --git a/drivers/net/ethernet/nebula-matrix/Kconfig b/drivers/net/ethernet/nebula-matrix/Kconfig
new file mode 100644
index 000000000000..99cd53fcc52e
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/Kconfig
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Nebula-matrix network device configuration
+#
+
+config NET_VENDOR_NEBULA_MATRIX
+ bool "Nebula-matrix devices"
+ default y
+ help
+ If you have a network (Ethernet) card belonging to this class, say Y.
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Nebula-matrix cards. If you say Y, you will be asked
+ for your specific card in the following questions.
+
+if NET_VENDOR_NEBULA_MATRIX
+
+config NBL
+ tristate "Nebula-matrix Ethernet Controller m18110/m18000 support"
+ depends on PCI && (64BIT || COMPILE_TEST) && !CPU_BIG_ENDIAN
+ help
+ This driver supports Nebula-matrix Ethernet Controller m18110/m18000
+ Family of devices. For more information about this product, go to
+ the product description with smart NIC:
+
+ <http://www.nebula-matrix.com>
+
+ More specific information on configuring the driver is in
+ <file:Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst>.
+
+ To compile this driver as a module, choose M here. The module
+ will be called nbl.
+
+endif # NET_VENDOR_NEBULA_MATRIX
diff --git a/drivers/net/ethernet/nebula-matrix/Makefile b/drivers/net/ethernet/nebula-matrix/Makefile
new file mode 100644
index 000000000000..42cdf2db8f0c
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the Nebula-matrix network device drivers.
+#
+
+obj-$(CONFIG_NBL) += nbl/
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
new file mode 100644
index 000000000000..b90fba239401
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2025 Nebula Matrix Limited.
+
+obj-$(CONFIG_NBL) := nbl.o
+
+nbl-objs += nbl_main.o
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h
new file mode 100644
index 000000000000..d5136b13c490
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_CORE_H_
+#define _NBL_CORE_H_
+
+enum {
+ NBL_CAP_HAS_CTRL_BIT,
+ NBL_CAP_HAS_NET_BIT,
+ NBL_CAP_IS_LEONIS_BIT,
+};
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
new file mode 100644
index 000000000000..cd99f96e1568
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_INCLUDE_H_
+#define _NBL_INCLUDE_H_
+
+#include <linux/types.h>
+
+/* ------ Basic definitions ------- */
+#define NBL_DRIVER_NAME "nbl"
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c
new file mode 100644
index 000000000000..d931c6a40e6c
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#include <linux/device.h>
+#include <linux/pci.h>
+#include <linux/module.h>
+#include "nbl_include/nbl_include.h"
+#include "nbl_core.h"
+
+static int nbl_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ return -ENODEV;
+}
+
+static void nbl_remove(struct pci_dev *pdev)
+{
+}
+
+/*
+ * PCI Device IDs for Leonis/NBL Network Controllers
+ *
+ * Vendor ID: 0x1F0F
+ * SNIC v3r1 product Device IDs range: 0x3403-0x3412
+ */
+#define NBL_VENDOR_ID 0x1F0F
+
+#define NBL_DEVICE_ID_M18110 0x3403
+#define NBL_DEVICE_ID_M18110_LX 0x3404
+#define NBL_DEVICE_ID_M18110_BASE_T 0x3405
+#define NBL_DEVICE_ID_M18110_LX_BASE_T 0x3406
+#define NBL_DEVICE_ID_M18110_OCP 0x3407
+#define NBL_DEVICE_ID_M18110_LX_OCP 0x3408
+#define NBL_DEVICE_ID_M18110_BASE_T_OCP 0x3409
+#define NBL_DEVICE_ID_M18110_LX_BASE_T_OCP 0x340a
+#define NBL_DEVICE_ID_M18000 0x340b
+#define NBL_DEVICE_ID_M18000_LX 0x340c
+#define NBL_DEVICE_ID_M18000_BASE_T 0x340d
+#define NBL_DEVICE_ID_M18000_LX_BASE_T 0x340e
+#define NBL_DEVICE_ID_M18000_OCP 0x340f
+#define NBL_DEVICE_ID_M18000_LX_OCP 0x3410
+#define NBL_DEVICE_ID_M18000_BASE_T_OCP 0x3411
+#define NBL_DEVICE_ID_M18000_LX_BASE_T_OCP 0x3412
+
+static const struct pci_device_id nbl_id_table[] = {
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_BASE_T),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX_BASE_T),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_BASE_T_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX_BASE_T_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_BASE_T),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX_BASE_T),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_BASE_T_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX_BASE_T_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ /* required as sentinel */
+ {
+ 0,
+ }
+};
+MODULE_DEVICE_TABLE(pci, nbl_id_table);
+
+static struct pci_driver nbl_driver = {
+ .name = NBL_DRIVER_NAME,
+ .id_table = nbl_id_table,
+ .probe = nbl_probe,
+ .remove = nbl_remove,
+};
+
+module_pci_driver(nbl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Nebula Matrix Network Driver");
+MODULE_AUTHOR("Illusion Wang <illusion.wang@nebula-matrix.com>");
--
2.47.3
^ permalink raw reply related
* Re: [PATCH] nfc: fdp: reject an oversized device-reported packet length
From: Bryam Vargas @ 2026-06-17 4:41 UTC (permalink / raw)
To: Simon Horman
Cc: David Heidelberg, Robert Dolca, Samuel Ortiz, Kang Chen,
oe-linux-nfc, netdev, linux-kernel
In-Reply-To: <20260616090035.GS712698@horms.kernel.org>
> So I wonder if the check you are adding below should also guard
> against phy->next_read_size < FDP_NCI_I2C_MIN_PAYLOAD.
Agreed. Both routes are reachable: a length packet with tmp[2] == 0 &&
tmp[3] < 2 gives 3 or 4 directly, and the + 3 can carry the u16 store
past 65535 (tmp[2] == tmp[3] == 0xff -> 65538, truncated to 2).
next_read_size then drops below the 2-byte header + 1-byte LRC that
fdp_nci_i2c_remove_len_lrc() strips, and the short read also leaves
tmp[2]/tmp[3] unrefreshed when the next packet is parsed as a length
packet, so the following length comes from stale buffer bytes. It is not
a second overflow -- skb_pull()/skb_trim() are self-guarding, so the
frame is malformed rather than out of bounds -- but the desync is real
and bounding it is correct.
v2 folds both ends into one range check on the stored value, so the
truncation case is covered too. It also carries a fix for an skb leak in
the same function (a device that sends two data packets in one call
leaks the first skb); I am happy to split that into its own patch if you
would prefer.
I will add your Suggested-by.
Bryam
^ permalink raw reply
* [PATCH v2] nfc: fdp: bound the device-reported read length and fix an skb leak
From: Bryam Vargas via B4 Relay @ 2026-06-17 4:33 UTC (permalink / raw)
To: David Heidelberg
Cc: linux-kernel, netdev, Samuel Ortiz, Robert Dolca, oe-linux-nfc,
Simon Horman, Kang Chen
From: Bryam Vargas <hexlabsecurity@proton.me>
fdp_nci_i2c_read() takes the next packet length from two device-supplied
bytes and never validates it. The value is a u16 used as the
i2c_master_recv() count into a 261-byte on-stack buffer: a malicious,
counterfeit or malfunctioning controller (or an i2c bus interposer) can
drive it far past the buffer for a stack out-of-bounds write that
clobbers the canary and return address, or below the minimum frame size
(directly, or by truncating the computed sum) so the header/LRC strip
and the next length read run past a short receive. Reject a length
outside [FDP_NCI_I2C_MIN_PAYLOAD, FDP_NCI_I2C_MAX_PAYLOAD], as a
corrupted packet already is, and force resynchronization.
The same loop allocates one data skb per iteration and assumes a length
packet followed by a data packet; a device that sends two data packets
in one call leaks the first skb when the second allocation overwrites
it. Free a previously allocated skb before allocating the next.
Fixes: a06347c04c13 ("NFC: Add Intel Fields Peak NFC solution driver")
Cc: stable@vger.kernel.org
Suggested-by: Simon Horman <horms@kernel.org>
Signed-off-by: Bryam Vargas <hexlabsecurity@proton.me>
---
v2:
- Also reject next_read_size < FDP_NCI_I2C_MIN_PAYLOAD, not just
> FDP_NCI_I2C_MAX_PAYLOAD (Simon Horman). The small value is reachable
both directly (tmp[2] == 0 && tmp[3] < 2) and through the u16
truncation of the computed sum (e.g. 0xff,0xff -> 65538 -> 2); a single
range check on the stored value covers both, and also keeps the next
length-field read from running on stale buffer bytes.
- Fold in a fix for an skb leak in the same function (two data packets
in one call overwrite and leak the first skb).
v1: https://lore.kernel.org/all/20260615-b4-disp-f42dce2d-v1-1-186ff3dcbf37@proton.me
Reproduced in-kernel on x86-64 (Linux 7.1.0-rc5, CONFIG_KASAN_STACK=y)
with a faithful port of the read loop, and at full device magnitude with
a userspace AddressSanitizer model:
Stack OOB write
A no bound, next_read_size 281 -> 20 B past tmp[261]:
BUG: KASAN: stack-out-of-bounds in i2c_master_recv...
Write of size 281 ... This frame has 1 object: [48, 309) 'tmp'
B bounded to <= FDP_NCI_I2C_MAX_PAYLOAD: no KASAN report
C well-formed (len 5): no KASAN report
ASan model, full u16 next_read_size = 65535 -> 65274-byte
stack-buffer-overflow WRITE on both -m32 and -m64; bounded build clean.
skb leak (slabinfo active-object delta over 20000 reads, two data
packets each, measured after a slab shrink)
without the fix: skbuff_head_cache +20047, skbuff_small_head +20057
(one orphaned skb per call, unreclaimable)
with the fix: ~0
---
drivers/nfc/fdp/i2c.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/nfc/fdp/i2c.c b/drivers/nfc/fdp/i2c.c
index c1896a1d978c..f292e7f37456 100644
--- a/drivers/nfc/fdp/i2c.c
+++ b/drivers/nfc/fdp/i2c.c
@@ -166,9 +166,36 @@ static int fdp_nci_i2c_read(struct fdp_i2c_phy *phy, struct sk_buff **skb)
/* Packet that contains a length */
if (tmp[0] == 0 && tmp[1] == 0) {
phy->next_read_size = (tmp[2] << 8) + tmp[3] + 3;
+
+ /*
+ * next_read_size is taken from the device and is used
+ * as the i2c_master_recv() count for the next packet
+ * and as the data skb size. A value above the receive
+ * buffer overflows tmp[]; one below the minimum frame
+ * size runs the header/LRC strip and the length-field
+ * read past a short receive. Either way the packet is
+ * corrupt: drop it and force resynchronization.
+ */
+ if (phy->next_read_size < FDP_NCI_I2C_MIN_PAYLOAD ||
+ phy->next_read_size > FDP_NCI_I2C_MAX_PAYLOAD) {
+ dev_dbg(&client->dev, "%s: corrupted packet\n",
+ __func__);
+ phy->next_read_size = FDP_NCI_I2C_MIN_PAYLOAD;
+ goto flush;
+ }
} else {
phy->next_read_size = FDP_NCI_I2C_MIN_PAYLOAD;
+ /*
+ * Only one data packet is delivered per call; if the
+ * device sends another, do not overwrite and leak the
+ * skb allocated for the previous one.
+ */
+ if (*skb) {
+ kfree_skb(*skb);
+ *skb = NULL;
+ }
+
*skb = alloc_skb(len, GFP_KERNEL);
if (*skb == NULL) {
r = -ENOMEM;
---
base-commit: 8e65320d91cdc3b241d4b94855c88459b91abf66
change-id: 20260616-b4-disp-b1f8ab4c-b06ad43c9be5
Best regards,
--
Bryam Vargas <hexlabsecurity@proton.me>
^ permalink raw reply related
* Re: [PATCH v2 net-next 1/1] tcp: Replace min_tso_segs() with tso_segs() CC callback for TCP Prague
From: Eric Dumazet @ 2026-06-17 4:29 UTC (permalink / raw)
To: Jakub Kicinski
Cc: Chia-Yu Chang (Nokia), ncardwell@google.com, jolsa@kernel.org,
yonghong.song@linux.dev, song@kernel.org,
linux-kselftest@vger.kernel.org, memxor@gmail.com,
shuah@kernel.org, martin.lau@linux.dev, ast@kernel.org,
daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com,
horms@kernel.org, dsahern@kernel.org, bpf@vger.kernel.org,
netdev@vger.kernel.org, pabeni@redhat.com, jhs@mojatatu.com,
stephen@networkplumber.org, davem@davemloft.net,
andrew+netdev@lunn.ch, donald.hunter@gmail.com, kuniyu@google.com,
ij@kernel.org, Koen De Schepper (Nokia), g.white@cablelabs.com,
ingemar.s.johansson@ericsson.com, mirja.kuehlewind@ericsson.com,
cheshire@apple.com, rs.ietf@gmx.at, Jason_Livingood@comcast.com,
vidhi_goel@apple.com
In-Reply-To: <20260616082302.3618bd90@kernel.org>
On Tue, Jun 16, 2026 at 8:23 AM Jakub Kicinski <kuba@kernel.org> wrote:
>
> On Tue, 16 Jun 2026 12:23:11 +0000 Chia-Yu Chang (Nokia) wrote:
> > > On Mon, 15 Jun 2026 18:51:02 -0700 Jakub Kicinski wrote:
> > > > On Sun, 14 Jun 2026 09:17:56 +0200 chia-yu.chang@nokia-bell-labs.com
> > > > Eric, Neal, looks good?
> > > >
> > > > The min rtt thing in tcp_tso_autosize() helps a bit but if the sender
> > > > gets congested for a longer stretch min_rtts on new connections are
> > > > high and we're back to sending small TSO, keeping the sender overloaded.
> > > > Which is to say - I _hope_ this also solves some of Meta's problems :)
> > >
> > > Ugh, I didn't see the Sashiko report, it's only CCed to the author and bpf@, not to netdev :/
> > >
> > > The zero-check sounds legit. Let's revisit this after the merge window.
> >
> > Thanks for the comment, I will take action after the merge window.
> >
> > And, please correct me if I am wrong, the next eligible submission is expected from 30-June, right?
>
> It usually opens Monday morning (PST) so Jun 29th
I missed this thread, I can not keep up with emails sent during
weekends in May/June/July
Please Chia-Yu, consider sending patches during weekdays; I would have
a better chance to look at them.
^ permalink raw reply
* Re: [Intel-wired-lan] [PATCH net-next v4] ixgbe: implement get_queue_stats_rx
From: Kshitiz Bartariya @ 2026-06-17 4:20 UTC (permalink / raw)
To: Simon Horman
Cc: intel-wired-lan, anthony.l.nguyen, przemyslaw.kitszel,
andrew+netdev, davem, edumazet, kuba, pabeni, jedrzej.jagielski,
intel-wired-lan, netdev, linux-kernel
In-Reply-To: <20260615115806.756776-1-horms@kernel.org>
Hi Simon,
For the review generated by AI, I had done changes on that line previously but Jakub Kicinski <kuba@kernel.org> pointed out that such checks are redundant https://lore.kernel.org/lkml/20260525085356.5c336491@kernel.org/ .
Kindly let me know according to whom I've to make the final changes.
Thanks,
Kshitiz
From: Simon Horman <horms@kernel.org>
To: <intel-wired-lan@osuosl.org>
Cc: "Simon Horman"<horms@kernel.org>, <anthony.l.nguyen@intel.com>, <przemyslaw.kitszel@intel.com>, <andrew+netdev@lunn.ch>, <davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>, <jedrzej.jagielski@intel.com>, <kshitiz.bartariya@zohomail.in>, <intel-wired-lan@lists.osuosl.org>, <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Date: Mon, 15 Jun 2026 17:28:06 +0530
Subject: Re: [Intel-wired-lan] [PATCH net-next v4] ixgbe: implement get_queue_stats_rx
> This is an AI-generated review of your patch. The human sending this
> email has considered the AI review valid, or at least plausible.
> Full review at: https://netdev-ai.bots.linux.dev/sashiko/
> ---
> ixgbe: implement get_queue_stats_rx
>
> This patch wires ixgbe into the netdev_stat_ops interface so that per-RX
> queue counters (bytes, packets, alloc_fail, csum_bad) are exported
> through the netdev generic netlink API.
>
> > diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
> > index bc16e4c93fd4..67844e25af23 100644
> > --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
> > +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
> > @@ -9759,6 +9759,30 @@ static void ixgbe_get_stats64(struct net_device *netdev,
> > stats->rx_missed_errors = netdev->stats.rx_missed_errors;
> > }
> >
> > +static void ixgbe_get_queue_stats_rx(struct net_device *dev, int idx,
> > + struct netdev_queue_stats_rx *stats)
> > +{
> > + struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev);
> > + struct ixgbe_ring *ring = adapter->rx_ring[idx];
> > +
>
> [High]
> Can adapter->rx_ring[idx] be observed NULL here?
>
> Elsewhere in the same driver, this slot is treated as nullable. The
> writer side uses WRITE_ONCE() in both directions, for example in
> ixgbe_free_q_vector():
>
> WRITE_ONCE(adapter->rx_ring[ring->queue_index], NULL);
>
> and the existing readers in ixgbe_main.c pair that with READ_ONCE() and
> a NULL guard, e.g. ixgbe_get_stats64():
>
> struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]);
> if (ring) {
> ...
> }
>
> and ixgbe_update_stats():
>
> struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]);
> if (!rx_ring)
> continue;
>
> If a userspace caller issues a per-queue qstats request while the driver
> is reconfiguring queues (e.g. ixgbe_clear_interrupt_scheme() /
> ixgbe_init_interrupt_scheme() during reset), would a plain dereference
> here oops?
>
> Should this callback follow the same READ_ONCE() plus NULL-skip pattern
> used in ixgbe_get_stats64() and ixgbe_update_stats()?
>
> > + stats->bytes = ring->stats.bytes;
> > + stats->packets = ring->stats.packets;
>
> [Medium]
> Should these 64-bit reads be wrapped in a u64_stats_sync read section?
>
> The writer side, ixgbe_update_rx_ring_stats(), updates these counters
> under ring->syncp:
>
> u64_stats_update_begin(&rx_ring->syncp);
> rx_ring->stats.packets += total_packets;
> rx_ring->stats.bytes += total_bytes;
> u64_stats_update_end(&rx_ring->syncp);
>
> and the syncp is initialized at probe (u64_stats_init() on ring->syncp).
> ixgbe_get_stats64() in this same file already mirrors that on the read
> side:
>
> do {
> start = u64_stats_fetch_begin(&ring->syncp);
> packets = ring->stats.packets;
> bytes = ring->stats.bytes;
> } while (u64_stats_fetch_retry(&ring->syncp, start));
>
> On 32-bit kernels a 64-bit load is not atomic, so without the fetch
> loop can the values returned to userspace be torn (high half from one
> update, low half from another)?
>
> > + stats->alloc_fail = ring->rx_stats.alloc_rx_page_failed +
> > + ring->rx_stats.alloc_rx_buff_failed;
> > + stats->csum_bad = ring->rx_stats.csum_err;
> > +}
> > +
>
> [ ... ]
>
^ permalink raw reply
* Re: [PATCH v1 net-next] ipv4: fib_rule: Move fib4_rules_exit() to ->exit().
From: Eric Dumazet @ 2026-06-17 4:20 UTC (permalink / raw)
To: patchwork-bot+netdevbpf
Cc: Kuniyuki Iwashima, dsahern, idosch, davem, kuba, pabeni, horms,
kuni1840, netdev, syzbot+965506b59a2de0b6905c
In-Reply-To: <178165020689.1270198.450287651539968178.git-patchwork-notify@kernel.org>
On Tue, Jun 16, 2026 at 3:50 PM <patchwork-bot+netdevbpf@kernel.org> wrote:
>
> Hello:
>
> This patch was applied to netdev/net-next.git (main)
> by Jakub Kicinski <kuba@kernel.org>:
>
> On Tue, 16 Jun 2026 19:13:48 +0000 you wrote:
> > syzbot reported use-after-free of net->ipv4.rules_ops. [0]
> >
> > It can be reproduced with these commands:
> >
> > while true; do
> > ip netns add ns1
> > ip -n ns1 link set dev lo up
> > ip -n ns1 address add 192.0.2.1/24 dev lo
> > ip -n ns1 link add name dummy1 up type dummy
> > ip -n ns1 address add 198.51.100.1/24 dev dummy1
> > ip -n ns1 rule add ipproto tcp sport 12345 table 12345
> > ip -n ns1 fou add port 5555 ipproto 47 local 192.0.2.1 peer 198.51.100.2 peer_port 54321
> > ip netns del ns1
> > done
> >
> > [...]
Note that even with both patches:
fib_net_ops runs its exit handler -> frees rules_ops and fib_table_hash.
The devices are still fully UP (because default_device_exit_batch()
has not run yet).
An external packet (e.g., from the host side of a veth pair) arrives.
In enqueue_to_backlog():
Since the device is still UP, netif_running(dev) is still true.
Our newly merged lock-serialized check will pass, and the packet is queued.
The softirq processes the packet and calls __fib_lookup() or
fib_get_table() on the dying netns.
It will hit a UAF on the already-freed rules_ops or fib_table_hash.
If we want to make the netns exit 100% bulletproof against this
remaining window (and not revert Kuniyuki patches)
I have patches hardeniin the routing layers (RCU-safety), making
rules_ops and fib6_table RCU-safe and checking for NULL),
and additionally make fib_table_hash RCU-safe.
This way, even if a packet arrives during this window, the lookup will
safely fail-safe (returning -ENETUNREACH) instead of crashing.
I had these patches written yesterday before realizing the issue I was
looking at was generically fixed in enqueue_to_backlog()
^ permalink raw reply
* Re: [PATCH net] gve: fix header buffer corruption with header-split and HW-GRO
From: Eric Dumazet @ 2026-06-17 4:03 UTC (permalink / raw)
To: Joshua Washington
Cc: netdev, Harshitha Ramamurthy, Andrew Lunn, David S. Miller,
Jakub Kicinski, Paolo Abeni, Willem de Bruijn, Tim Hostetler,
Ziwei Xiao, Praveen Kaligineedi, Jeroen de Borst, linux-kernel,
Ankit Garg, stable, Jordan Rhee
In-Reply-To: <20260617013208.3781453-1-joshwash@google.com>
On Tue, Jun 16, 2026 at 6:32 PM Joshua Washington <joshwash@google.com> wrote:
>
> From: Ankit Garg <nktgrg@google.com>
>
> The DQO RX datapath programs a per-buffer-queue-descriptor
> header_buf_addr at post time and reads the split header back at
> completion time. Both the post and the read currently index the
> header buffer by queue position rather than by the buffer's identity:
>
> - post (gve_rx_post_buffers_dqo): header_buf_addr is computed from
> bufq->tail
> - read (gve_rx_dqo): the header is read from desc_idx (the completion
> queue head index)
>
...
> Cc: stable@vger.kernel.org
> Fixes: 5e37d8254e7f ("gve: Add header split data path")
> Signed-off-by: Ankit Garg <nktgrg@google.com>
> Reviewed-by: Praveen Kaligineedi <pkaligineedi@google.com>
> Reviewed-by: Jordan Rhee <jordanrhee@google.com>
> Reviewed-by: Harshitha Ramamurthy <hramamurthy@google.com>
> Signed-off-by: Joshua Washington <joshwash@google.com>
> ---
Reviewed-by: Eric Dumazet <edumazet@google.com>
^ permalink raw reply
* Re: [PATCH v1 bpf-next 0/2] bpf: bpf_redirect_peer egress redirection
From: Jiayuan Chen @ 2026-06-17 3:36 UTC (permalink / raw)
To: Paul Chaignon, Jordan Rife
Cc: bpf, netdev, Alexei Starovoitov, Daniel Borkmann, Andrii Nakryiko,
Martin KaFai Lau, Stanislav Fomichev
In-Reply-To: <ajAXF8Nvg91xU4f2@mail.gmail.com>
On 6/15/26 11:15 PM, Paul Chaignon wrote:
> On Sat, Jun 13, 2026 at 11:34:04AM -0700, Jordan Rife wrote:
>> We have several use cases where a pod injects traffic into the datapath
>> of another so that the traffic appears to have originated from that
>> pod. One such use case is a synthetic flow generator which injects
>> synthetic traffic into a pod's datapath to enable dynamic probing and
>> debugging. Another is a transparent proxy where connections originating
>> from one pod are redirected towards another which proxies that
>> connection. The new connection is bound to the IP of the original pod
>> using IP_TRANSPARENT and its traffic is injected into that pod's
>> datapath and handled as if it had originated there. This can be used for
>> mTLS, etc.
>>
>> We use bpf_redirect(BPF_F_INGRESS) to direct traffic leaving the proxy,
>> flow generator, etc. towards the target pod, ensuring that eBPF programs
>> that are meant to intercept traffic leaving that pod are executed.
>> However, this doesn't work with netkit.
>>
>> With netkit, an ingress redirection from proxy to workload skips eBPF
>> programs that are meant to intercept traffic leaving the pod, since they
>> reside on the netkit peer device. One workaround is to attach the
>> same program to both the netkit peer device and the TCX ingress hook for
>> the netkit pair's primary interface, but
>>
>> a) This seems hacky and we need to be careful not to run the same
>> program twice for the same skb in cases where we want to pass that
>> traffic to the host stack.
>> b) We're trying to keep the proxy redirection / traffic injection
>> systems as modular and separated from Cilium as possible, the system
>> that manages netkit setup and core eBPF programming.
>>
>> It would be handy if instead we could redirect traffic directly from
>> one netkit peer device to another. This patch proposes an extension
>> to bpf_redirect_peer to allow us to do just that.
>>
>> With this patch, the BPF_F_INGRESS flag tells bpf_redirect_peer to emit
>> the skb in the egress direction of the target interface's peer device
>> While the main use case is netkit, I suppose you could also use this
>> mode with veth as well if, e.g., there were some eBPF programs attached
>> to that side of the veth pair that needed to intercept traffic.
>>
>> +---------------------------------------------------------------------+
>> | +-------------------------+ 6. bpf_redirect_neigh(eth0) |
>> | | pod (10.244.0.10) | ------------------------ |
>> | | | | | |
>> | | +--------+ | | +---------+ | |
>> | | 1. packet -->| | | | | | | |
>> | | leaves ^ | netkit |<===========|======| netkit | | |
>> | | | | peer |=======(eBPF)=====>| primary | | |
>> | | | | | | | | | | |
>> | | | +--------+ | | +---------+ | |
>> | | | | | 2. bpf_redirect v |
>> | +-----------|-------------+ |___________________ +-------|
>> | | | | eth0 |
>> | | 5. bpf_redirect_peer(BPF_F_INGRESS) | +-------|
>> | |________________________ | |
>> | +-------------------------+ | | |
>> | | proxy (10.244.0.11) | | | |
>> | | IP_TRANSPARENT | | | |
>> | | +--------+ | | +---------+ | |
>> | | 3. packet <--| | | | | |<-- |
>> | | enters | netkit |<===========|======| netkit | |
>> | | [proxy] | peer |=======(eBPF)=====>| primary | |
>> | | 4. packet -->| | | | | |
>> | | leaves +--------+ | +---------+ |
>> | | sip=10.244.0.10 | |
>> | +-------------------------+ |
>> +---------------------------------------------------------------------+
>>
>> Using the proxy use case as an example, in step 5 we would redirect
>> traffic leaving the proxy towards the pod's peer device using
>> bpf_redirect_peer(BPF_F_INGRESS).
>>
>> As a bonus, since the skb doesn't have to go through the backlog queue
>> it can take full advantage of netkit's performance benefits. I set up a
> The motivation makes sense. Cilium could probably use this as well to
> avoid some of the hacks we have around proxy reinjection.
>
>> test where outgoing iperf3 traffic is injected into the datapath of
>> another pod using either bpf_redirect_peer(BPF_F_INGRESS) or
>> bpf_redirect(BPF_F_INGRESS). I used Cilium's eBPF host routing mode
>> which skips the host stack and uses BPF redirect helpers to do all the
>> routing.
>>
>> (net.ipv4.tcp_congestion_control=cubic,mtu=1500,100GiB link,Cilium
>> eBPF host routing mode)
>>
>> BASELINE [bpf_redirect(BPF_F_INGRESS)]
>> 1. [iperf pod] ==bpf_redirect([pod b], BPF_F_INGRESS)==> [pod b]
>> 2. [pod b] ==bpf_redirect_neigh([eth0])==> eth0
>> 3. eth0 ==over network==> [host b]
>>
>> [ ID] Interval Transfer Bitrate Retr
>> [ 5] 0.00-60.00 sec 231 GBytes 33.0 Gbits/sec 12060 sender
>> [ 5] 0.00-60.00 sec 230 GBytes 33.0 Gbits/sec receiver
>>
>> TEST [bpf_redirect_peer(BPF_F_INGRESS)]
>> 1. [iperf pod] ==bpf_redirect_peer([pod b], BPF_F_INGRESS)==> [pod b]
>> 2. [pod b] ==bpf_redirect_neigh([eth0])==> eth0
>> 3. eth0 ==over network==> [host b]
>>
>> [ ID] Interval Transfer Bitrate Retr
>> [ 5] 0.00-60.00 sec 272 GBytes 38.9 Gbits/sec 0 sender
>> [ 5] 0.00-60.00 sec 272 GBytes 38.9 Gbits/sec receiver
>>
>> In this test, using bpf_redirect_peer(BPF_F_INGRESS) for the hop from
>> [iperf pod] to [pod b] led to ~18% more throughput compared to
>> bpf_redirect(BPF_F_INGRESS).
>>
>> Note: I wasn't sure about the flag name. I can see where BPF_F_INGRESS
>> might be confusing, since technically it's an egress redirection
>> from the perspective of the peer device's namespace. But, I didn't
>> want to add a BPF_F_EGRESS flag just for this and convinced myself
>> it makes sense, because from the perspective of the caller the skb
>> will be flowing towards the current namespace.
> IMO, calling it BPF_F_EGRESS would be less confusing. It's a shame we
> can't have the same flag API between bpf_redirect() and
> bpf_redirect_peer(), but this is creating inconsistent semantics for
> the terms egress/ingress across the two helpers.
Agree.
For the existing bpf_redirect_peer(ifindex, 0), there are two ways to
read what 0 means:
1. If we consider the operated object to be the peer of ifindex, then 0
means the peer does ingress.
2. If we consider the operated object to be ifindex itself, then 0 means
ifindex does egress
(which results in its peer doing ingress).
This patch's new mode operates on the peer — on the host side, we want
to "write" to the dev inside the pod to
make the packet look like it leaves the pod. That fits reading (1), where
the flag describes the peer's direction: 0 is peer ingress, and this new
mode is peer egress.
So BPF_F_EGRESS would be the clearer name; reusing BPF_F_INGRESS for
what is really a
peer-egress action is what creates the ambiguity.
^ permalink raw reply
* [PATCH net] net: airoha: Fix TX scheduler queue mask loop upper bound
From: Wayen Yan @ 2026-06-17 3:20 UTC (permalink / raw)
To: netdev
Cc: lorenzo, horms, pabeni, kuba, edumazet, andrew+netdev,
angelogioacchino.delregno, matthias.bgg, linux-arm-kernel,
linux-mediatek
In airoha_qdma_set_chan_tx_sched(), the loop clearing queue mask was
using AIROHA_NUM_TX_RING (32) instead of AIROHA_NUM_QOS_QUEUES (8).
Each channel has 8 queues, and TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)
computes BIT(i + (channel * 8)). With i ranging 0..31, this causes:
- channel 0: clears bit 0..31 (all 4 channels) instead of 0..7
- channel 1: clears bit 8..31 (channels 1-3) instead of 8..15
- channel 2: clears bit 16..31 (channels 2-3) instead of 16..23
- channel 3: clears bit 24..31 (channel 3 only) - correct by accident
While BIT(32+) on arm64 produces 64-bit values truncated to 0 in u32
mask parameter, the loop still incorrectly clears queues within the
same channel beyond queue 7.
Fix by using AIROHA_NUM_QOS_QUEUES (8) as the loop upper bound.
Fixes: ef1ca9271313 ("net: airoha: Add sched HTB offload support")
Signed-off-by: Wayen Yan <win847@gmail.com>
---
drivers/net/ethernet/airoha/airoha_eth.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 31cdb11cd7..a1eda13400 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2217,7 +2217,7 @@ static int airoha_qdma_set_chan_tx_sched(struct net_device *dev,
struct airoha_gdm_port *port = netdev_priv(dev);
int i;
- for (i = 0; i < AIROHA_NUM_TX_RING; i++)
+ for (i = 0; i < AIROHA_NUM_QOS_QUEUES; i++)
airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel),
TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i));
--
2.51.0
^ permalink raw reply related
* Re: [PATCH net-next] r8169: migrate Rx path to page_pool
From: Atharva Potdar @ 2026-06-17 3:28 UTC (permalink / raw)
To: Francois Romieu
Cc: hkallweit1, nic_swsd, andrew+netdev, davem, edumazet, kuba,
pabeni, netdev
In-Reply-To: <20260614220934.GA3575431@electric-eye.fr.zoreil.com>
Hi Heiner, Francois,
Thank you for reviewing this patch.
Francois:
> You may consider fdd7b4c3302c93f6833e338903ea77245eb510b4 and some related
> changes around that time.
I am sorry but I don't fully understand the context of this commit or
the behaviour it addresses. Could you please help me regarding what I
need to watch out for this change?
Heiner:
> Assuming your link speed is 1Gbps, 470Mbps is quite low.
I apologize, that was my benchmark figure when I passed my NIC via
VFIO to a VM for testing. When I tested it bare metal again with
iperf3, I hit line rates of 941 Mbps.
> If I read this correctly, max_mtu may be lower with this patch.
> This may cause a regression for existing users.
My main intention for restricting to order-0 pages is to prepare the
driver for XDP support in the subsequent patches. I understand this
causes a regression but I am not sure of another way to tackle it. How
do you prefer I handle this to avoid breaking current setups while
still having the driver be ready for XDP?
> Did you test also on non-x86 architectures? We had DMA-related regressions
> in the past which showed up on certain non-x86 architectures only.
Unfortunately, I currently only have access to x86 hardware. I cannot
test this on a bare-metal ARM machine, only an ARM VM - which may not
show those hardware issues. How is the testing typically handled for
other architectures in a situation like this?
Thanks,
Atharva.
^ permalink raw reply
* [PATCH] net: airoha: Fix off-by-one error in HTB rate-limit channel removal
From: Wayen Yan @ 2026-06-17 2:51 UTC (permalink / raw)
To: netdev
Cc: lorenzo, horms, pabeni, kuba, edumazet, andrew+netdev,
angelogioacchino.delregno, matthias.bgg, linux-arm-kernel,
linux-mediatek
In airoha_tc_remove_htb_queue(), the rate-limit was being cleared
using (queue + 1) instead of queue, causing:
- The original channel rate-limit configuration to remain active
- The next channel to be incorrectly disabled
- Potential out-of-bounds access when queue == 3 (channel 4)
The alloc path (airoha_tc_htb_alloc_leaf_queue) correctly uses
channel (0..3), but the remove path incorrectly added 1.
Fix by using queue directly to match the alloc and rollback paths.
Fixes: ef1ca9271313 ("net: airoha: Add sched HTB offload support")
Signed-off-by: Wayen Yan <win847@gmail.com>
---
drivers/net/ethernet/airoha/airoha_eth.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 31cdb11cd7..02807b3967 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2805,7 +2805,7 @@ static void airoha_tc_remove_htb_queue(struct net_device *dev, int queue)
struct airoha_gdm_port *port = netdev_priv(dev);
netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1);
- airoha_qdma_set_tx_rate_limit(dev, queue + 1, 0, 0);
+ airoha_qdma_set_tx_rate_limit(dev, queue, 0, 0);
clear_bit(queue, port->qos_sq_bmap);
}
--
2.51.0
^ permalink raw reply related
* Re: [RESEND PATCH v1] net: dsa: motorcomm: add yt92xx dsa driver
From: Kyle Switch @ 2026-06-17 2:41 UTC (permalink / raw)
To: Julian Braha, mmyangfl, andrew, olteanv, davem, edumazet, kuba,
pabeni, horms, netdev, linux-kernel
Cc: ming.xu, xiaolin.xu, jianmin.wang, de.ge
In-Reply-To: <eeacfa0d-9303-407f-8e8a-ecc95d1ab1c8@gmail.com>
On 6/15/26 23:01, Julian Braha wrote:
> Hi Kyle,
>
> On 6/15/26 12:12, Kyle Switch wrote:
>
>> diff --git a/drivers/net/dsa/motorcomm/Kconfig b/drivers/net/dsa/motorcomm/Kconfig
>> new file mode 100644
>> index 000000000000..f40d75e2a3f2
>> --- /dev/null
>> +++ b/drivers/net/dsa/motorcomm/Kconfig
>> @@ -0,0 +1,30 @@
>> +# SPDX-License-Identifier: GPL-2.0-only
>> +
>> +config MOTORCOMM
>> + tristate "Motorcomm YT92XX switch family support"
>> + depends on NET_DSA
>> + select FIXED_PHY
>> + help
>> + This driver adds support for Motorcomm switch chips. It supports
>> + YT921X and YT922X switch.
>> +
>> +choice
>> + prompt "Motorcomm switch series selection"
>> + depends on MOTORCOMM
>> +
>> +config MOTORCOMM_YT921X
>> + bool "Motorcomm YT921X series."
>> +
>> +config MOTORCOMM_YT922X
>> + bool "Motorcomm YT922X series."
>> +endchoice
>> +
>> +config NET_DSA_MOTORCOMM
>> + tristate "Motorcomm YT92XX switch DSA driver"
>> + depends on MOTORCOMM
>> + depends on (MOTORCOMM_YT921X || MOTORCOMM_YT922X)
>> + select NET_DSA_TAG_MOTORCOMM
>> + select NET_IEEE8021Q_HELPERS if DCB
>> + help
>> + Select to enable support for Motorcomm driver.
>> +
>> diff --git a/drivers/net/dsa/motorcomm/Makefile b/drivers/net/dsa/motorcomm/Makefile
> NET_DSA_MOTORCOMM already depends on:
> (MOTORCOMM_YT921X || MOTORCOMM_YT922X)
> with both of those options depending on MOTORCOMM due to the 'choice'
> that they're in, so this additional dependency on MOTORCOMM is
> unnecessary.
>
> You could also consider using a comment to document that this option is
> depended on indirectly.
Ans: agreed, i will fix this later.
>
> - Julian Braha
^ permalink raw reply
* Re: [RESEND PATCH v1] net: dsa: motorcomm: add yt92xx dsa driver
From: Kyle Switch @ 2026-06-17 2:37 UTC (permalink / raw)
To: David Yang
Cc: andrew, olteanv, davem, edumazet, kuba, pabeni, horms, netdev,
linux-kernel, ming.xu, xiaolin.xu, jianmin.wang, de.ge
In-Reply-To: <CAAXyoMOp8mYLUx4CQBn=9R8rNqEsb8ybWD0z+=FJgh2j-F0s8A@mail.gmail.com>
On 6/16/26 02:55, David Yang wrote:
> On Mon, Jun 15, 2026 at 7:12 PM Kyle Switch <kyle.switch@motor-comm.com> wrote:
>>
>> Add yt92xx dsa driver supports yt921x and yt922x switch series.
>> To support more switch series in the future (e.g., yt923x), the most common configurations are abstracted into switch operation interfaces, due to yt921x and yt922x share similar register layouts and operational logic.
>
> You are blindly plugging existing code into your SDK, without sorting
> out register operations (for example in set_mac_eee and
> port_change_mtu).
>
> Do not post code you don't understand. Ask if you are not sure.
Ans: Thank you for your suggestion. I will recheck the code logic again in the future.
>
>> +#define CMM_PARAM_CHK(expr, err_code) \
>> + do { \
>> + if ((u32)(expr)) { \
>> + return err_code; \
>> + } \
>> + } while (0)
>> +
>> +#define CMM_ERR_CHK(op, ret) \
>> + do { \
>> + ret = (op); \
>> + if (ret != CMM_ERR_OK) \
>> + return ret; \
>> + } while (0)
>
> Do not use macros like this.
Ans: Acknowledged, i will consider how to optimize them in the future.
>
>> +#define GET_FIELD(value, low_bit, width) \
>> + (((value) >> (low_bit)) & ((1U << (width)) - 1))
>> +#define CLR_FIELD(value, low_bit, width) \
>> + ((value) & (~(((1U << (width)) - 1) << (low_bit))))
>> +
>> +#define HAL_FIELD_SET(low_bit, width, entry, data) \
>> + do { \
>> + *(entry) &= (~(((1UL << (width)) - 1) << (low_bit))); \
>> + *(entry) |= ((data) << (low_bit)); \
>> + } while (0)
>> +
>> +#define HAL_FIELD_GET(low_bit, width, entry, pdata) \
>> + (*(pdata) = (((*(entry)) >> (low_bit)) & ((1UL << (width)) - 1)))
>
> FIELD_PREP() and FIELD_GET().
>
>> +/*
>> + * Macro Definition
>> + */
>> +#ifndef NULL
>> +#define NULL 0
>> +#endif
>> +
>> +#ifndef FALSE
>> +#define FALSE 0
>> +#endif
>> +
>> +#ifndef TRUE
>> +#define TRUE 1
>> +#endif
>
> Nonsense.
Ans: Acknowledge, will be fixed later.
>
>> + /* Print chipid here since we are interested in lower 16 bits */
>> + dev_info(dev,
>> + "Motorcomm %s ethernet switch.\n",
>> + info->name);
>
> Stop copy-n-paste.
Ans: Sry for this, i will recheck the code to make sure each line of comments and code
meaningful again.
>
> Please, start with a minimal patch that only marks functions which use
> different registers/procedures and makes them virtual, and implement
> them for yt922x in the future.
>
>> + {
>> + .compatible = "motorcomm,yt9215,8bytes",
>> + .data = &yt92xx_chip_info[YT9215_8B],
>> + },
>
> Do not change devicetree compatible strings.
Ans: agreed, this will be fixed later.
>
>> --- a/include/uapi/linux/if_ether.h
>> +++ b/include/uapi/linux/if_ether.h
>> @@ -118,7 +118,7 @@
>> #define ETH_P_QINQ1 0x9100 /* deprecated QinQ VLAN [ NOT AN OFFICIALLY REGISTERED ID ] */
>> #define ETH_P_QINQ2 0x9200 /* deprecated QinQ VLAN [ NOT AN OFFICIALLY REGISTERED ID ] */
>> #define ETH_P_QINQ3 0x9300 /* deprecated QinQ VLAN [ NOT AN OFFICIALLY REGISTERED ID ] */
>> -#define ETH_P_YT921X 0x9988 /* Motorcomm YT921x DSA [ NOT AN OFFICIALLY REGISTERED ID ] */
>> +#define ETH_P_YT92XX 0x9988 /* Motorcomm YT92xx DSA [ NOT AN OFFICIALLY REGISTERED ID ] */
>> #define ETH_P_EDSA 0xDADA /* Ethertype DSA [ NOT AN OFFICIALLY REGISTERED ID ] */
>> #define ETH_P_DSA_8021Q 0xDADB /* Fake VLAN Header for DSA [ NOT AN OFFICIALLY REGISTERED ID ] */
>> #define ETH_P_DSA_A5PSW 0xE001 /* A5PSW Tag Value [ NOT AN OFFICIALLY REGISTERED ID ] */
>
> UAPI stands for User-space API. Do not change it unless there is a
> very very good reason.
>
Ans: The default tpid both yt921x and yt922x is 0x9988. I have modified this to
allow for simultaneous use in both yt922x and yt921x scenarios.
>> +/* To define the from cpu tag format 8 bytes:
>> + *
>> + * 0 1 2 3 4 5 6 7 | 0 1 2 3 4 5 6 7
>> + *|<----------TPID 0x9988---------->|
>> + *|<--RESERVE-->|<-----DST PORT---->|
>> + *|-|<---------RESERVE------------->|
>> + *|<------------------------------->|
>> + */
>> +#define YT922X_TAG_FORMAT2_NAME "yt922x-8b"
>> +#define YT922X_FORMAT2_TAG_LEN 8
>> +#define YT922X_PKT_TYPE GENMASK(15, 14)
>> +#define YT922X_8B_CPUTAG_PKT_FROM_CPU 0x1
>> +#define YT922X_8B_CPUTAG_SRC_PORT GENMASK(6, 2)
>> +#define YT922X_8B_CPUTAG_DST_PORTMASK GENMASK(8, 0)
>> +#define YT922X_8B_CPUTAG_DST_PORTMASK_0 BIT(15)
>> +#define YT922X_8B_CPUTAG_DST_PORTMASK_0_EN 0x1
>> +#define YT922X_8B_CPUTAG_FORCE_DST BIT(9)
>> +#define YT922X_8B_CPUTAG_FORCE_DST_EN 0x1
>
> If yt922x tag format shares no common with yt921x, make a new tag driver.
Ans: thank you for your suggestion, we will consider whether to create a new driver in the new file.
>
>> +static struct dsa_tag_driver *dsa_tag_driver_array[] = {
>> + &DSA_TAG_DRIVER_NAME(yt921x_netdev_ops),
>> + &DSA_TAG_DRIVER_NAME(yt922x_4b_netdev_ops),
>> + &DSA_TAG_DRIVER_NAME(yt922x_8b_netdev_ops),
>> +};
>
> If both are supported by the chip and 4b does nothing more than 8b
> does, do not bother with it.
Ans: 4b and 8b dsa tag may have different application scenarios. from my opinion,
1. 4b dsa tag can save 4 bytes of payload
2. 8b dsa tag carry more package info.
^ permalink raw reply
* [PATCH net-next] ionic: Change list definition method
From: Lei Zhu @ 2026-06-17 2:32 UTC (permalink / raw)
To: brett.creeley, andrew+netdev, davem, edumazet, kuba; +Cc: netdev, zhulei_szu
From: Lei Zhu <zhulei@kylinos.cn>
The LIST_HEAD macro can both define a linked list and initialize
it in one step. To simplify code, we replace the separate operations
of linked list definition and manual initialization with the LIST_HEAD
macro.
Signed-off-by: Lei Zhu <zhulei@kylinos.cn>
---
drivers/net/ethernet/pensando/ionic/ionic_rx_filter.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_rx_filter.c b/drivers/net/ethernet/pensando/ionic/ionic_rx_filter.c
index 528114877677..967f4e1e97b4 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_rx_filter.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_rx_filter.c
@@ -558,8 +558,8 @@ struct sync_item {
void ionic_rx_filter_sync(struct ionic_lif *lif)
{
struct device *dev = lif->ionic->dev;
- struct list_head sync_add_list;
- struct list_head sync_del_list;
+ LIST_HEAD(sync_add_list);
+ LIST_HEAD(sync_del_list);
struct sync_item *sync_item;
struct ionic_rx_filter *f;
struct hlist_head *head;
@@ -567,9 +567,6 @@ void ionic_rx_filter_sync(struct ionic_lif *lif)
struct sync_item *spos;
unsigned int i;
- INIT_LIST_HEAD(&sync_add_list);
- INIT_LIST_HEAD(&sync_del_list);
-
clear_bit(IONIC_LIF_F_FILTER_SYNC_NEEDED, lif->state);
/* Copy the filters to be added and deleted
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v2] net: rds: check cmsg_len before reading rds_rdma_args in size pass
From: Michael Bommarito @ 2026-06-17 2:31 UTC (permalink / raw)
To: Allison Henderson, David S . Miller, Jakub Kicinski, Paolo Abeni,
Eric Dumazet
Cc: Simon Horman, netdev, linux-rdma, rds-devel, linux-kernel
rds_rm_size() handles RDS_CMSG_RDMA_ARGS after only CMSG_OK() and then
calls rds_rdma_extra_size(), which reads args->local_vec_addr and
args->nr_local without first checking that cmsg_len covers struct
rds_rdma_args. The other two RDS_CMSG_RDMA_ARGS consumers already guard
this: rds_rdma_bytes() in rds_sendmsg() and rds_cmsg_rdma_args() in
rds_cmsg_send() both reject cmsg_len < CMSG_LEN(sizeof(struct
rds_rdma_args)). Add the same check to rds_rm_size() so all three RDMA
args passes are consistent.
This is a consistency and hardening change with no behavioral effect for
well-formed senders and no reachable bug today: rds_rdma_bytes() runs
before rds_rm_size() in rds_sendmsg() and already rejects a short
RDS_CMSG_RDMA_ARGS, so the size pass is not reached with an undersized
cmsg. But rds_rm_size() reads the args independently of that earlier
pass, and nothing in rds_rm_size() itself records or enforces the
precondition, so a reader or a future refactor of the size pass cannot
tell the cmsg has already been length-checked. Applying the same
cmsg_len guard in all three RDS_CMSG_RDMA_ARGS consumers keeps that
invariant local to each and robust to reordering.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Michael Bommarito <michael.bommarito@gmail.com>
---
v2:
- Re-target net-next and drop the Fixes: tag and the stable Cc. This
is a consistency/hardening change, not a reachable bug: as Allison
Henderson noted, rds_rdma_bytes() runs before rds_rm_size() in
rds_sendmsg() and already rejects a short RDS_CMSG_RDMA_ARGS, so a
user cannot reach the rds_rm_size() read through sendmsg.
- Corrected the changelog: the two sibling guards are rds_rdma_bytes()
in rds_sendmsg() and rds_cmsg_rdma_args() in rds_cmsg_send(); the
former runs before, not after, rds_rm_size().
- Dropped the KASAN/AF_RDS reachability framing. No code change from v1.
- v1: https://lore.kernel.org/all/20260614130725.2520842-1-michael.bommarito@gmail.com/
net/rds/send.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/net/rds/send.c b/net/rds/send.c
index d8b14ff9d366b..6ca3192b1d8af 100644
--- a/net/rds/send.c
+++ b/net/rds/send.c
@@ -967,6 +967,8 @@ static int rds_rm_size(struct msghdr *msg, int num_sgs,
switch (cmsg->cmsg_type) {
case RDS_CMSG_RDMA_ARGS:
+ if (cmsg->cmsg_len < CMSG_LEN(sizeof(struct rds_rdma_args)))
+ return -EINVAL;
if (vct->indx >= vct->len) {
vct->len += vct->incr;
tmp_iov =
base-commit: 5200f5f493f79f14bbdc349e402a40dfb32f23c8
--
2.53.0
^ permalink raw reply related
* Re: [PATCH net-next v2] net: dsa: Fix skb ownership in taggers
From: Qingfang Deng @ 2026-06-17 2:22 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Florian Fainelli,
Jonas Gorski, Hauke Mehrtens, Kurt Kanzenbach, Woojung Huh,
UNGLinuxDriver, Chester A. Unal, Daniel Golle, Matthias Brugger,
AngeloGioacchino Del Regno, Wei Fang, Clark Wang,
Clément Léger, George McCollister, David Yang, netdev,
Sashiko AI Review
In-Reply-To: <20260616-dsa-fix-free-skb-v2-1-9dbda6a19e97@kernel.org>
On 16 Jun 2026 at 11:36:22 +0200, Linus Walleij wrote:
> --- a/net/dsa/tag_rtl4_a.c
> +++ b/net/dsa/tag_rtl4_a.c
> @@ -41,8 +41,10 @@ static struct sk_buff *rtl4a_tag_xmit(struct sk_buff *skb,
> u16 out;
>
> /* Pad out to at least 60 bytes */
> - if (unlikely(__skb_put_padto(skb, ETH_ZLEN, false)))
> + if (unlikely(__skb_put_padto(skb, ETH_ZLEN, false))) {
> + kfree_skb(skb);
> return NULL;
> + }
This can be simplified to eth_skb_pad().
>
> netdev_dbg(dev, "add realtek tag to package to port %d\n",
> dp->index);
> --- a/net/dsa/tag_rzn1_a5psw.c
> +++ b/net/dsa/tag_rzn1_a5psw.c
> @@ -48,7 +48,7 @@ static struct sk_buff *a5psw_tag_xmit(struct sk_buff *skb, struct net_device *de
> * least 60 bytes otherwise they will be discarded when they enter the
> * switch port logic.
> */
> - if (__skb_put_padto(skb, ETH_ZLEN, false))
> + if (skb_put_padto(skb, ETH_ZLEN))
> return NULL;
Same here.
>
> /* provide 'A5PSW_TAG_LEN' bytes additional space */
- Qingfang
^ permalink raw reply
* [PATCH net] net/wan/hdlc_ppp: sync per-proto timers before freeing hdlc state
From: Fan Wu @ 2026-06-17 2:05 UTC (permalink / raw)
To: netdev
Cc: Krzysztof Halasa, Jakub Kicinski, David S. Miller, Eric Dumazet,
Paolo Abeni, Andrew Lunn, linux-kernel, Fan Wu, stable
Each PPP control protocol (LCP/IPCP/IPV6CP) embedded in struct ppp
registers a timer via timer_setup(). That struct ppp is the
hdlc->state allocation, which detach_hdlc_protocol() frees with kfree()
in both teardown paths: unregister_hdlc_device() and the re-attach inside
attach_hdlc_protocol().
The ppp proto never registered a .detach callback, so
detach_hdlc_protocol() performs no timer synchronization before the
kfree(). The only cancel, timer_delete(&proto->timer) in ppp_cp_event(),
is partial (it does not wait for a running callback) and only runs on the
->CLOSED transition; ppp_stop()/ppp_close() do not sync either. A
ppp_timer callback already executing (blocked on ppp->lock) survives the
kfree and then dereferences proto->state / ppp->lock in freed memory,
leading to a use-after-free.
Fix this by adding a .detach helper that calls timer_shutdown_sync() on
every per-proto timer. detach_hdlc_protocol() invokes proto->detach(dev)
before kfree(hdlc->state), so timer_shutdown_sync()
now runs on both free paths.
timer_shutdown_sync() is used instead of timer_delete_sync() because the
keepalive path re-arms the timer through add_timer()/mod_timer() and
shutdown blocks any re-activation during teardown.
Initialize the per-protocol timers in ppp_ioctl() when the protocol is
attached, and remove the now-redundant timer_setup() from ppp_start(), so
that the timers are initialized exactly once at attach time and
ppp_timer_release() never operates on uninitialized timer_list
structures. attach_hdlc_protocol() uses kmalloc() (not kzalloc), so
struct ppp's protos[i].timer is uninitialized garbage until the first
timer_setup(); without this init-at-attach, attaching the PPP protocol
without ever bringing the device up would leave timer_shutdown_sync()
operating on uninitialized memory in .detach. Moving the init out of
ppp_start() (which only runs on NETDEV_UP) into the attach path makes the
initialization unconditional and avoids initializing the same timer_list
twice.
This bug was found by static analysis.
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Cc: stable@vger.kernel.org
Signed-off-by: Fan Wu <fanwu01@zju.edu.cn>
---
drivers/net/wan/hdlc_ppp.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/net/wan/hdlc_ppp.c b/drivers/net/wan/hdlc_ppp.c
index 159295c4bd6d820ca51bb768a70437b541cb3f1e..302ed27944e7c8586a04f70ea639f2da0f7dcbb9 100644
--- a/drivers/net/wan/hdlc_ppp.c
+++ b/drivers/net/wan/hdlc_ppp.c
@@ -619,7 +619,6 @@ static void ppp_start(struct net_device *dev)
struct proto *proto = &ppp->protos[i];
proto->dev = dev;
- timer_setup(&proto->timer, ppp_timer, 0);
proto->state = CLOSED;
}
ppp->protos[IDX_LCP].pid = PID_LCP;
@@ -639,6 +638,15 @@ static void ppp_close(struct net_device *dev)
ppp_tx_flush();
}
+static void ppp_timer_release(struct net_device *dev)
+{
+ struct ppp *ppp = get_ppp(dev);
+ int i;
+
+ for (i = 0; i < IDX_COUNT; i++)
+ timer_shutdown_sync(&ppp->protos[i].timer);
+}
+
static struct hdlc_proto proto = {
.start = ppp_start,
.stop = ppp_stop,
@@ -647,6 +655,7 @@ static struct hdlc_proto proto = {
.ioctl = ppp_ioctl,
.netif_rx = ppp_rx,
.module = THIS_MODULE,
+ .detach = ppp_timer_release,
};
static const struct header_ops ppp_header_ops = {
@@ -657,7 +666,7 @@ static int ppp_ioctl(struct net_device *dev, struct if_settings *ifs)
{
hdlc_device *hdlc = dev_to_hdlc(dev);
struct ppp *ppp;
- int result;
+ int i, result;
switch (ifs->type) {
case IF_GET_PROTO:
@@ -685,6 +694,8 @@ static int ppp_ioctl(struct net_device *dev, struct if_settings *ifs)
return result;
ppp = get_ppp(dev);
+ for (i = 0; i < IDX_COUNT; i++)
+ timer_setup(&ppp->protos[i].timer, ppp_timer, 0);
spin_lock_init(&ppp->lock);
ppp->req_timeout = 2;
ppp->cr_retries = 10;
--
2.39.2
^ permalink raw reply related
* Re: [RESEND PATCH v1] net: dsa: motorcomm: add yt92xx dsa driver
From: Kyle Switch @ 2026-06-17 2:00 UTC (permalink / raw)
To: Andrew Lunn
Cc: mmyangfl, olteanv, davem, edumazet, kuba, pabeni, horms, netdev,
linux-kernel, ming.xu, xiaolin.xu, jianmin.wang, de.ge
In-Reply-To: <3f7bf73b-c8dc-451d-981f-5e5343291960@lunn.ch>
On 6/15/26 19:34, Andrew Lunn wrote:
> On Mon, Jun 15, 2026 at 07:12:35PM +0800, Kyle Switch wrote:
>> Add yt92xx dsa driver supports yt921x and yt922x switch series.
>> To support more switch series in the future (e.g., yt923x), the most common configurations are abstracted into switch operation interfaces, due to yt921x and yt922x share similar register layouts and operational logic.
>>
>> - Merge drivers/net/dsa/yt921x.c and the new yt922x support into a
>> unified yt92xx.c driver.
>>
>> - Add support for yt922x, which can operate with either 4 bytes or
>> 8 bytes DSA tag.
>>
>> - Not change yt921x behaviour but use common switch apis
>
> A 35K line patch is way too big. Please break this up into lots of
> small patches, each with good commit messages, which are obviously
> correct.
>
Thank you for your reminding, this patch will submitted in a series
of small patches.
This patch mainly contains three contents:
1. Underlying function interface for different motorcomm switch series in
the file driver/net/dsa/motorcomm/switch/.
2. Optimization existing yt921x dsa driver using common switch function apis.
3. New yt922x dsa driver.
Can you accept break this up into lots of small patch according to this logic?
if not, do you have any suggestion? thank you.
> Andrew
>
> ---
> pw-bot: cr
^ permalink raw reply
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