* Re: [PATCH rdma-next 08/13] RDMA/cgroup: Scope rdma cgroup device visibility to the net namespace
From: Tao Cui @ 2026-07-14 2:28 UTC (permalink / raw)
To: Jiri Pirko, Michal Koutný
Cc: cui.tao, linux-rdma, cgroups, netdev, linux-s390, linux-kselftest,
jgg, leon, parav, mbloch, cmeiohas, roman.gushchin, bvanassche,
zyjzyj2000, shuah, tj, hannes, alibuda, dust.li, sidraya, wenjia
In-Reply-To: <alSxB0wziQnNuyfn@FV6GYCPJ69>
在 2026/7/13 17:34, Jiri Pirko 写道:
> Thu, Jul 09, 2026 at 03:04:23PM +0200, mkoutny@suse.com wrote:
>> Hi.
>>
>> On Thu, Jul 09, 2026 at 11:55:27AM +0200, Jiri Pirko <jiri@resnulli.us> wrote:
>>> index 993446ab66d0..4523c1884d67 100644
>>> --- a/Documentation/admin-guide/cgroup-v2.rst
>>> +++ b/Documentation/admin-guide/cgroup-v2.rst
>>> @@ -2752,6 +2752,13 @@ RDMA
>>> The "rdma" controller regulates the distribution and accounting of
>>> RDMA resources.
>>>
>>> +When RDMA devices are isolated per network namespace (exclusive mode),
>>> +device names are unique only within a network namespace. The device lines
>>> +below are therefore scoped to the reading or writing process's network
>>> +namespace: only devices accessible from that namespace are listed, and a
>>> +limit is applied to the device of that name in that namespace. Configure
>>> +limits from the same network namespace as the workloads.
>>
>> OK.
>>
>>> --- a/include/linux/cgroup_rdma.h
>>> +++ b/include/linux/cgroup_rdma.h
>>> @@ -7,6 +7,7 @@
>>> #define _CGROUP_RDMA_H
>>>
>>> #include <linux/cgroup.h>
>>> +#include <net/net_namespace.h>
>>>
>>> enum rdmacg_resource_type {
>>> RDMACG_RESOURCE_HCA_HANDLE,
>>> @@ -34,6 +35,15 @@ struct rdmacg_device {
>>> struct list_head dev_node;
>>> struct list_head rpools;
>>> char *name;
>>> + /*
>>> + * Net namespace the device belongs to. @netns_shared mirrors
>>> + * ib_devices_shared_netns: when true the device is visible from every
>>> + * net namespace (shared mode); otherwise @net is the only namespace
>>> + * that may see and configure it. @netns_shared is updated when the
>>> + * sharing mode changes, so use {READ,WRITE}_ONCE() to access it.
>>> + */
>>> + possible_net_t net;
>>> + bool netns_shared;
>>
>> Any reason to store the netns_shared split per device? (IIUC, it's a
>> global parameter.)
>
> No reason, changed.
>
Hi Jiri,
A question on the v2 you mentioned to Michal.
Once netns_shared stops being cached per rdmacg_device,
rdmacg_device_visible() in kernel/cgroup/rdma.c still needs the current
sharing mode, whose authoritative value lives in the IB core
(ib_devices_shared_netns). How do you plan to expose it there without
the generic cgroup controller reaching back into drivers/infiniband/?
Exporting the global, or keeping an IB-side update hook, both feel a bit
awkward; it would be good to see which direction you took.
On the mechanism itself: it's the right call that rdmacg_try_charge()
stays out of the scoping. Charging takes the rdmacg_device pointer
directly (no name lookup), and a task can only charge a device it
already holds a handle to, so applying visibility there would be wrong.
The scoping deliberately touches only the name-based lookup (the write
path) and the enumeration (read/show) paths -- worth keeping that
invariant in mind so a later patch doesn't grow the filter.
Thanks,
Tao> Thanks!
>
>>
>> Thanks,
>> Michal
>
>
>
^ permalink raw reply
* Re: [PATCH net-next v2] mptcp: sockopt: implement IPV6_TCLASS
From: Geliang Tang @ 2026-07-14 2:22 UTC (permalink / raw)
To: David 'equinox' Lamparter, Matthieu Baerts, Mat Martineau
Cc: netdev, mptcp
In-Reply-To: <20260713135551.569365-1-equinox@diac24.net>
Hi David,
Thanks for your patch. However there is already a version under review
on the MPTCP mailing list that adds IPV6_TCLASS [1] (as well as IP_TTL
and IPV6_UNICAST_HOPS).
Thanks,
-Geliang
https://patchwork.kernel.org/project/mptcp/patch/2617b8684039574734b8622936ef126d6a7cd519.1754986785.git.tanggeliang@kylinos.cn/
On Mon, 2026-07-13 at 15:51 +0200, David 'equinox' Lamparter wrote:
> The IPV6_TCLASS setsockopt just needs to be forwarded to the
> individual
> TCP sockets, like IP_TOS is already handled for IPv4. The code here
> is
> pretty much identical, except there's no helper for IPv6 like IPv4's
> __ip_sock_set_tos().
>
> Coincidentally, ssh uses this sockopt and prints an error in the
> middle
> of your ongoing SSH session when it doesn't work (very annoying when
> doing SCP/SFTP on a multiplexed session.)
>
> Signed-off-by: David 'equinox' Lamparter <equinox@diac24.net>
> Cc: Matthieu Baerts <matttbe@kernel.org>
> Cc: Mat Martineau <martineau@kernel.org>
> Cc: Geliang Tang <geliang@kernel.org>
> ---
> [v2: added guard for CONFIG_IPV6=n. I could also add a stub for
> ipv6_setsockopt() in include/net/ipv6.h, that might be prettier?]
> ---
> net/mptcp/sockopt.c | 38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/net/mptcp/sockopt.c b/net/mptcp/sockopt.c
> index fcf6feb2a9eb..1b83bba0b58e 100644
> --- a/net/mptcp/sockopt.c
> +++ b/net/mptcp/sockopt.c
> @@ -394,6 +394,39 @@ static int mptcp_setsockopt_sol_socket(struct
> mptcp_sock *msk, int optname,
> return -EOPNOTSUPP;
> }
>
> +static int mptcp_setsockopt_v6_set_tclass(struct mptcp_sock *msk,
> int optname,
> + sockptr_t optval, unsigned
> int optlen)
> +{
> +#if !IS_ENABLED(CONFIG_IPV6)
> + return -EOPNOTSUPP;
> +#else
> + struct mptcp_subflow_context *subflow;
> + struct sock *sk = (struct sock *)msk;
> + int err, val;
> +
> + err = ipv6_setsockopt(sk, SOL_IPV6, optname, optval,
> optlen);
> +
> + if (err != 0)
> + return err;
> +
> + lock_sock(sk);
> + sockopt_seq_inc(msk);
> + val = READ_ONCE(inet6_sk(sk)->tclass);
> + mptcp_for_each_subflow(msk, subflow) {
> + struct sock *ssk = mptcp_subflow_tcp_sock(subflow);
> + bool slow;
> +
> + slow = lock_sock_fast(ssk);
> + inet6_sk(ssk)->tclass = val;
> + sk_dst_reset(ssk);
> + unlock_sock_fast(ssk, slow);
> + }
> + release_sock(sk);
> +
> + return 0;
> +#endif
> +}
> +
> static int mptcp_setsockopt_v6(struct mptcp_sock *msk, int optname,
> sockptr_t optval, unsigned int
> optlen)
> {
> @@ -436,6 +469,8 @@ static int mptcp_setsockopt_v6(struct mptcp_sock
> *msk, int optname,
>
> release_sock(sk);
> break;
> + case IPV6_TCLASS:
> + return mptcp_setsockopt_v6_set_tclass(msk, optname,
> optval, optlen);
> }
>
> return ret;
> @@ -1485,6 +1520,9 @@ static int mptcp_getsockopt_v6(struct
> mptcp_sock *msk, int optname,
> struct sock *sk = (void *)msk;
>
> switch (optname) {
> + case IPV6_TCLASS:
> + return mptcp_put_int_option(msk, optval, optlen,
> + READ_ONCE(inet6_sk(sk)-
> >tclass));
> case IPV6_V6ONLY:
> return mptcp_put_int_option(msk, optval, optlen,
> sk->sk_ipv6only);
^ permalink raw reply
* [PATCH net-next v3 4/4] net: stmmac: dwmac-socfpga: Add support for Agilex5 TSN GMAC with FPGA converter
From: muhammad.nazim.amirul.nazle.asmade @ 2026-07-14 2:13 UTC (permalink / raw)
To: dinguyen, maxime.chevallier
Cc: rmk+kernel, krzk+dt, conor+dt, robh, davem, edumazet, kuba,
pabeni, andrew+netdev, devicetree, linux-arm-kernel, netdev,
linux-kernel
In-Reply-To: <20260714021303.30042-1-muhammad.nazim.amirul.nazle.asmade@altera.com>
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
The Agilex5 SoCDK TSN Config2 board uses a GMII-to-RGMII converter
implemented as FPGA soft IP between gmac1 and its PHY. This converter
provides the RGMII TX/RX clock delays, so the MAC interface selector
must be configured for GMII while the PHY is configured without delays.
Add the "altr,socfpga-stmmac-agilex5-tsn" compatible to the match table
and detect it in probe to force GMII for the MAC interface selector and
strip the delay bits from phy_interface so the PHY is not configured to
add delays already provided by the FPGA converter.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
v3: No changes from v2.
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 1d7f0a57d288..bf591a68502f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -69,12 +69,13 @@ struct socfpga_dwmac {
void __iomem *tse_pcs_base;
void __iomem *sgmii_adapter_base;
bool f2h_ptp_ref_clk;
+ phy_interface_t mac_interface;
const struct socfpga_dwmac_ops *ops;
};
static phy_interface_t socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac)
{
- return dwmac->plat_dat->phy_interface;
+ return dwmac->mac_interface;
}
static void socfpga_sgmii_config(struct socfpga_dwmac *dwmac, bool enable)
@@ -650,6 +651,15 @@ static int socfpga_dwmac_probe(struct platform_device *pdev)
plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
plat_dat->select_pcs = socfpga_dwmac_select_pcs;
+ dwmac->mac_interface = plat_dat->phy_interface;
+
+ if (of_device_is_compatible(pdev->dev.of_node,
+ "altr,socfpga-stmmac-agilex5-tsn")) {
+ dwmac->mac_interface = PHY_INTERFACE_MODE_GMII;
+ if (phy_interface_mode_is_rgmii(plat_dat->phy_interface))
+ plat_dat->phy_interface = PHY_INTERFACE_MODE_RGMII;
+ }
+
ops->setup_plat_dat(dwmac);
return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
@@ -674,6 +684,7 @@ static const struct of_device_id socfpga_dwmac_match[] = {
{ .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops },
{ .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops },
{ .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_agilex5_ops },
+ { .compatible = "altr,socfpga-stmmac-agilex5-tsn", .data = &socfpga_agilex5_ops },
{ }
};
MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
--
2.43.7
^ permalink raw reply related
* [PATCH v3 3/4] dt-bindings: net: altr,socfpga-stmmac: Add altr,socfpga-stmmac-agilex5-tsn compatible
From: muhammad.nazim.amirul.nazle.asmade @ 2026-07-14 2:13 UTC (permalink / raw)
To: dinguyen, maxime.chevallier
Cc: rmk+kernel, krzk+dt, conor+dt, robh, davem, edumazet, kuba,
pabeni, andrew+netdev, devicetree, linux-arm-kernel, netdev,
linux-kernel
In-Reply-To: <20260714021303.30042-1-muhammad.nazim.amirul.nazle.asmade@altera.com>
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
The Agilex5 SoCDK TSN Config2 board uses a GMII-to-RGMII converter
implemented as FPGA soft IP between gmac1 and its PHY. This converter
provides the RGMII TX/RX clock delays. Document a new compatible string
for this MAC variant so the driver can detect it and configure the
interface accordingly.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
v3: No changes from v2.
.../devicetree/bindings/net/altr,socfpga-stmmac.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
index 63084f762373..81f030986fa3 100644
--- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
+++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
@@ -24,6 +24,7 @@ select:
- altr,socfpga-stmmac
- altr,socfpga-stmmac-a10-s10
- altr,socfpga-stmmac-agilex5
+ - altr,socfpga-stmmac-agilex5-tsn
required:
- compatible
@@ -46,6 +47,10 @@ properties:
- items:
- const: altr,socfpga-stmmac-agilex5
- const: snps,dwxgmac-2.10
+ - items:
+ - const: altr,socfpga-stmmac-agilex5-tsn
+ - const: altr,socfpga-stmmac-agilex5
+ - const: snps,dwxgmac-2.10
clocks:
minItems: 1
--
2.43.7
^ permalink raw reply related
* [PATCH v3 2/4] arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board
From: muhammad.nazim.amirul.nazle.asmade @ 2026-07-14 2:13 UTC (permalink / raw)
To: dinguyen, maxime.chevallier
Cc: rmk+kernel, krzk+dt, conor+dt, robh, davem, edumazet, kuba,
pabeni, andrew+netdev, devicetree, linux-arm-kernel, netdev,
linux-kernel
In-Reply-To: <20260714021303.30042-1-muhammad.nazim.amirul.nazle.asmade@altera.com>
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Add device tree for the Intel SoCFPGA Agilex5 SoCDK TSN Config2 board
variant. This configuration enables gmac1 as a TSN port alongside the
standard gmac2 Ethernet port.
The TSN port (gmac1) connects to its PHY through a GMII-to-RGMII
converter implemented as FPGA soft IP. This converter provides the
RGMII TX/RX clock delays, so phy-mode is set to "rgmii-id" to reflect
MAC-side delays. A board-specific compatible string is used so the
driver can detect the converter and strip the delay bits before
configuring the PHY.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
v3: No changes from v2.
arch/arm64/boot/dts/intel/Makefile | 1 +
.../intel/socfpga_agilex5_socdk_tsn_cfg2.dts | 131 ++++++++++++++++++
2 files changed, 132 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 270c70fdf084..ce7cf3a63275 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex5_socdk_013b.dtb \
socfpga_agilex5_socdk_modular.dtb \
socfpga_agilex5_socdk_nand.dtb \
+ socfpga_agilex5_socdk_tsn_cfg2.dtb \
socfpga_agilex72_socdk.dtb \
socfpga_agilex7m_socdk.dtb \
socfpga_n5x_socdk.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts
new file mode 100644
index 000000000000..bf13ccfc1faa
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026, Altera Corporation
+ */
+#include "socfpga_agilex5.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex5 SoCDK TSN Config2";
+ compatible = "intel,socfpga-agilex5-socdk-tsn-cfg2", "intel,socfpga-agilex5";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "hps_led0";
+ gpios = <&porta 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gmac1 {
+ status = "okay";
+ compatible = "altr,socfpga-stmmac-agilex5-tsn",
+ "altr,socfpga-stmmac-agilex5",
+ "snps,dwxgmac-2.10";
+ phy-mode = "rgmii-id";
+ phy-handle = <&emac1_phy0>;
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ emac1_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&emac2_phy0>;
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ emac2_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ m25p,fast-read;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x04200000>;
+ };
+
+ root: partition@4200000 {
+ label = "root";
+ reg = <0x04200000 0x0be00000>;
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
2.43.7
^ permalink raw reply related
* [PATCH v3 1/4] dt-bindings: arm: altera: Add Agilex5 SoCDK TSN Config2 board
From: muhammad.nazim.amirul.nazle.asmade @ 2026-07-14 2:13 UTC (permalink / raw)
To: dinguyen, maxime.chevallier
Cc: rmk+kernel, krzk+dt, conor+dt, robh, davem, edumazet, kuba,
pabeni, andrew+netdev, devicetree, linux-arm-kernel, netdev,
linux-kernel
In-Reply-To: <20260714021303.30042-1-muhammad.nazim.amirul.nazle.asmade@altera.com>
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Add compatible string for the Intel SoCFPGA Agilex5 SoCDK TSN Config2
board variant. This board enables gmac1 as a TSN port with an FPGA
GMII-to-RGMII converter providing the RGMII clock delays.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Acked-by: Krzysztof Kozlowski <krzk+dt@kernel.org>
---
v3: Add missing Acked-by from Krzysztof Kozlowski inadvertently dropped in v2.
v2: Replace mac-mode DT property with compatible string detection.
Use phy-mode = "rgmii-id" to reflect MAC-side delay handling.
Fix Makefile indentation.
Documentation/devicetree/bindings/arm/altera.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 3030cf46fe74..e431469a7175 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -114,6 +114,7 @@ properties:
- intel,socfpga-agilex5-socdk-debug
- intel,socfpga-agilex5-socdk-modular
- intel,socfpga-agilex5-socdk-nand
+ - intel,socfpga-agilex5-socdk-tsn-cfg2
- const: intel,socfpga-agilex5
- description: Agilex72 boards
--
2.43.7
^ permalink raw reply related
* [PATCH v3 0/4] Add Agilex5 SoCDK TSN Config2 board support
From: muhammad.nazim.amirul.nazle.asmade @ 2026-07-14 2:12 UTC (permalink / raw)
To: dinguyen, maxime.chevallier
Cc: rmk+kernel, krzk+dt, conor+dt, robh, davem, edumazet, kuba,
pabeni, andrew+netdev, devicetree, linux-arm-kernel, netdev,
linux-kernel
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
This series adds support for the Intel SoCFPGA Agilex5 SoCDK TSN Config2
board variant, which enables gmac1 as a TSN Ethernet port alongside the
standard gmac2 port.
The TSN port (gmac1) connects to its PHY through a GMII-to-RGMII converter
implemented as FPGA soft IP. This converter provides the RGMII TX/RX clock
delays, requiring the MAC interface selector to be configured for GMII while
the PHY-facing interface is configured as RGMII without delay duplication.
This is handled by introducing a new compatible string
"altr,socfpga-stmmac-agilex5-tsn" detected in the driver probe to configure
the interface modes appropriately.
v3:
- Add missing Acked-by from Krzysztof Kozlowski on patch 1, inadvertently
dropped in v2.
v2:
- Replace mac-mode DT property with compatible string-based detection per
Andrew Lunn's feedback.
- Use phy-mode = "rgmii-id" to correctly reflect MAC-side delay handling.
- Rename compatible string to altr,socfpga-stmmac-agilex5-tsn for
consistency with existing altr,socfpga-stmmac-* compatibles.
- Fix Makefile indentation reported by Krzysztof Kozlowski.
- Add DT binding documentation for new net compatible string (new patch).
Nazim Amirul (4):
dt-bindings: arm: altera: Add Agilex5 SoCDK TSN Config2 board
arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board
dt-bindings: net: altr,socfpga-stmmac: Add
altr,socfpga-stmmac-agilex5-tsn compatible
net: stmmac: dwmac-socfpga: Add support for Agilex5 TSN GMAC with FPGA
converter
.../devicetree/bindings/arm/altera.yaml | 1 +
.../bindings/net/altr,socfpga-stmmac.yaml | 5 +
arch/arm64/boot/dts/intel/Makefile | 1 +
.../intel/socfpga_agilex5_socdk_tsn_cfg2.dts | 131 ++++++++++++++++++
.../ethernet/stmicro/stmmac/dwmac-socfpga.c | 13 +-
5 files changed, 150 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts
--
2.43.7
^ permalink raw reply
* [PATCH net-next] octeontx2-af: add new mbox to support sync cycle on rx path
From: Ratheesh Kannoth @ 2026-07-14 2:07 UTC (permalink / raw)
To: linux-kernel, netdev
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, sgoutham, Satha Rao,
Ratheesh Kannoth
From: Satha Rao <skoteshwar@marvell.com>
sync ensures that all packets that were in flight are flushed out to
memory. This can be used to assist in the tearing down of an active RQ.
To complete disabling RQs or disabling SMQ and its SQs, LF software
send mbox to AF to complete RX_SW_SYNC.
Change-Id: Iaadf5e6b26a7920693fca9921b2050af0e8e2322
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 1 +
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 13 +++++++++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index f87cdf1b971d..92175de036d5 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -362,6 +362,7 @@ M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \
nix_bp_cfg_rsp) \
M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \
msg_rsp) \
+M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp) \
M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
msg_req, nix_inline_ipsec_cfg) \
M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 78667a0977c0..0e2e6cde3de2 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -6324,6 +6324,19 @@ int rvu_mbox_handler_nix_bandprof_get_hwinfo(struct rvu *rvu, struct msg_req *re
return 0;
}
+int rvu_mbox_handler_nix_rx_sw_sync(struct rvu *rvu, struct msg_req *req,
+ struct msg_rsp *rsp)
+{
+ int blkaddr;
+
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc);
+ if (blkaddr < 0)
+ return NIX_AF_ERR_AF_LF_INVALID;
+
+ nix_rx_sync(rvu, blkaddr);
+ return 0;
+}
+
static struct nix_mcast_grp_elem *rvu_nix_mcast_find_grp_elem(struct nix_mcast_grp *mcast_grp,
u32 mcast_grp_idx)
{
--
2.43.0
^ permalink raw reply related
* [PATCH v4 net-next 7/7] net: ena: Implement gettimexattrs64 callback for PTP attributes
From: Arthur Kiyanovski @ 2026-07-14 2:03 UTC (permalink / raw)
To: David Miller, Jakub Kicinski, netdev
Cc: Arthur Kiyanovski, Richard Cochran, Eric Dumazet, Paolo Abeni,
David Woodhouse, Thomas Gleixner, Miroslav Lichvar, Andrew Lunn,
Wen Gu, Xuan Zhuo, David Woodhouse, Yonatan Sarna,
Zorik Machulsky, Alexander Matushevsky, Saeed Bshara, Matt Wilson,
Anthony Liguori, Nafea Bshara, Evgeny Schmeilin, Netanel Belgazal,
Ali Saidi, Benjamin Herrenschmidt, Noam Dagan, David Arinzon,
Evgeny Ostrovsky, Ofir Tabachnik, Amit Bernstein, linux-kselftest,
linux-doc, shuah, Jonathan Corbet, Shuah Khan, Simon Horman,
vadim.fedorenko
In-Reply-To: <20260714020340.25014-1-akiyano@amazon.com>
Implement the gettimexattrs64 callback in the ENA driver to support
the PTP_SYS_OFFSET_EXTENDED_ATTRS ioctl.
This enables applications to retrieve PHC timestamps with quality
attributes through the standard PTP ioctl interface.
The ENA device currently reports only error_bound (valid bit set).
Other attributes are not reported (valid bits unset).
Signed-off-by: Amit Bernstein <amitbern@amazon.com>
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
---
drivers/net/ethernet/amazon/ena/ena_phc.c | 58 +++++++++++++++++++----
1 file changed, 48 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/amazon/ena/ena_phc.c b/drivers/net/ethernet/amazon/ena/ena_phc.c
index 2bcb5af564e2..725c36fe3f6e 100644
--- a/drivers/net/ethernet/amazon/ena/ena_phc.c
+++ b/drivers/net/ethernet/amazon/ena/ena_phc.c
@@ -25,6 +25,43 @@ static int ena_phc_feature_enable(struct ptp_clock_info *clock_info,
return -EOPNOTSUPP;
}
+static int ena_phc_gettimexattrs64(struct ptp_clock_info *clock_info,
+ struct timespec64 *ts,
+ struct ptp_system_timestamp *sts,
+ struct ptp_clock_attrs *att)
+{
+ struct ena_phc_info *phc_info =
+ container_of(clock_info, struct ena_phc_info, clock_info);
+ u32 error_bound_nsec;
+ unsigned long flags;
+ u64 timestamp_nsec;
+ int rc;
+
+ spin_lock_irqsave(&phc_info->lock, flags);
+
+ ptp_read_system_prets(sts);
+
+ rc = ena_com_phc_get_timestamp(phc_info->adapter->ena_dev,
+ ×tamp_nsec,
+ &error_bound_nsec);
+
+ ptp_read_system_postts(sts);
+
+ spin_unlock_irqrestore(&phc_info->lock, flags);
+
+ if (rc)
+ return rc;
+
+ *ts = ns_to_timespec64(timestamp_nsec);
+
+ if (att) {
+ att->error_bound = error_bound_nsec;
+ att->valid |= PTP_ATTRS_VALID_ERROR_BOUND;
+ }
+
+ return 0;
+}
+
static int ena_phc_gettimex64(struct ptp_clock_info *clock_info,
struct timespec64 *ts,
struct ptp_system_timestamp *sts)
@@ -62,16 +99,17 @@ static int ena_phc_settime64(struct ptp_clock_info *clock_info,
}
static struct ptp_clock_info ena_ptp_clock_info = {
- .owner = THIS_MODULE,
- .n_alarm = 0,
- .n_ext_ts = 0,
- .n_per_out = 0,
- .pps = 0,
- .adjtime = ena_phc_adjtime,
- .adjfine = ena_phc_adjfine,
- .gettimex64 = ena_phc_gettimex64,
- .settime64 = ena_phc_settime64,
- .enable = ena_phc_feature_enable,
+ .owner = THIS_MODULE,
+ .n_alarm = 0,
+ .n_ext_ts = 0,
+ .n_per_out = 0,
+ .pps = 0,
+ .adjtime = ena_phc_adjtime,
+ .adjfine = ena_phc_adjfine,
+ .gettimexattrs64 = ena_phc_gettimexattrs64,
+ .gettimex64 = ena_phc_gettimex64,
+ .settime64 = ena_phc_settime64,
+ .enable = ena_phc_feature_enable,
};
/* Enable/Disable PHC by the kernel, affects on the next init flow */
--
2.47.3
^ permalink raw reply related
* [PATCH v4 net-next 6/7] net: ena: Add error bound to PHC communication layer
From: Arthur Kiyanovski @ 2026-07-14 2:03 UTC (permalink / raw)
To: David Miller, Jakub Kicinski, netdev
Cc: Arthur Kiyanovski, Richard Cochran, Eric Dumazet, Paolo Abeni,
David Woodhouse, Thomas Gleixner, Miroslav Lichvar, Andrew Lunn,
Wen Gu, Xuan Zhuo, David Woodhouse, Yonatan Sarna,
Zorik Machulsky, Alexander Matushevsky, Saeed Bshara, Matt Wilson,
Anthony Liguori, Nafea Bshara, Evgeny Schmeilin, Netanel Belgazal,
Ali Saidi, Benjamin Herrenschmidt, Noam Dagan, David Arinzon,
Evgeny Ostrovsky, Ofir Tabachnik, Amit Bernstein, linux-kselftest,
linux-doc, shuah, Jonathan Corbet, Shuah Khan, Simon Horman,
vadim.fedorenko
In-Reply-To: <20260714020340.25014-1-akiyano@amazon.com>
Extend the ENA PHC communication layer to retrieve error bound from
the device.
Update ena_com_phc_get_timestamp() to retrieve error_bound alongside
timestamps.
Add error handling and statistics for error_bound retrieval failures.
Signed-off-by: Amit Bernstein <amitbern@amazon.com>
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
---
.../device_drivers/ethernet/amazon/ena.rst | 2 +
drivers/net/ethernet/amazon/ena/ena_com.c | 40 ++++++++++++-------
drivers/net/ethernet/amazon/ena/ena_com.h | 5 ++-
drivers/net/ethernet/amazon/ena/ena_debugfs.c | 3 ++
drivers/net/ethernet/amazon/ena/ena_phc.c | 3 +-
5 files changed, 36 insertions(+), 17 deletions(-)
diff --git a/Documentation/networking/device_drivers/ethernet/amazon/ena.rst b/Documentation/networking/device_drivers/ethernet/amazon/ena.rst
index 14784a0a6a8a..ce9ba84bfd01 100644
--- a/Documentation/networking/device_drivers/ethernet/amazon/ena.rst
+++ b/Documentation/networking/device_drivers/ethernet/amazon/ena.rst
@@ -306,6 +306,8 @@ PHC errors must remain below 1% of all PHC requests to maintain the desired leve
**phc_err_dv** | Number of failed get time attempts due to device errors (entering into block state).
**phc_err_ts** | Number of failed get time attempts due to timestamp errors (entering into block state),
| This occurs if driver exceeded the request limit or device received an invalid timestamp.
+**phc_err_eb** | Number of failed get time attempts due to error bound errors (entering into block state),
+ | This occurs if device received an excessively high or invalid error bound.
================= ======================================================
PHC timeouts:
diff --git a/drivers/net/ethernet/amazon/ena/ena_com.c b/drivers/net/ethernet/amazon/ena/ena_com.c
index 40d1fd64bc34..353cb88e880e 100644
--- a/drivers/net/ethernet/amazon/ena/ena_com.c
+++ b/drivers/net/ethernet/amazon/ena/ena_com.c
@@ -45,7 +45,8 @@
#define ENA_PHC_DEFAULT_EXPIRE_TIMEOUT_USEC 10
#define ENA_PHC_DEFAULT_BLOCK_TIMEOUT_USEC 1000
#define ENA_PHC_REQ_ID_OFFSET 0xDEAD
-#define ENA_PHC_ERROR_FLAGS (ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP)
+#define ENA_PHC_ERROR_FLAGS (ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP | \
+ ENA_ADMIN_PHC_ERROR_FLAG_ERROR_BOUND)
/*****************************************************************************/
/*****************************************************************************/
@@ -1726,7 +1727,7 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev)
if (phc->expire_timeout_usec > phc->block_timeout_usec)
phc->expire_timeout_usec = phc->block_timeout_usec;
- /* Prepare PHC feature command */
+ /* Prepare PHC config feature command */
memset(&set_feat_cmd, 0x0, sizeof(set_feat_cmd));
set_feat_cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
set_feat_cmd.feat_common.feature_id = ENA_ADMIN_PHC_CONFIG;
@@ -1781,7 +1782,8 @@ void ena_com_phc_destroy(struct ena_com_dev *ena_dev)
phc->virt_addr = NULL;
}
-int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp)
+int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp,
+ u32 *error_bound)
{
const ktime_t zero_system_time = ktime_set(0, 0);
struct ena_com_phc_info *phc = &ena_dev->phc;
@@ -1828,6 +1830,8 @@ int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp)
* a PHC error, this occurs if device:
* - exceeded the get time request limit
* - received an invalid timestamp
+ * - received an excessively high error bound
+ * - received an invalid error bound
*/
netdev_err(ena_dev->net_device,
"PHC get time request 0x%x failed (error 0x%x)\n",
@@ -1835,9 +1839,11 @@ int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp)
resp->error_flags);
phc->stats.phc_err_ts += !!(resp->error_flags &
ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP);
+ phc->stats.phc_err_eb += !!(resp->error_flags &
+ ENA_ADMIN_PHC_ERROR_FLAG_ERROR_BOUND);
} else {
/* Device updated req_id during blocking time
- * with valid timestamp
+ * with valid timestamp and error bound
*/
phc->stats.phc_exp++;
}
@@ -1864,9 +1870,9 @@ int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp)
/* Stalling until the device updates req_id */
while (1) {
if (unlikely(ktime_after(ktime_get(), expire_time))) {
- /* Gave up waiting for updated req_id, PHC enters into
- * blocked state until passing blocking time,
- * during this time any get PHC timestamp will fail with
+ /* Gave up waiting for updated req_id,
+ * PHC enters into blocked state until passing blocking
+ * time, during this time, any request will fail with
* device busy error
*/
ret = -EBUSY;
@@ -1881,20 +1887,21 @@ int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp)
continue;
}
- /* Ensure PHC payload (timestamp, error_flags) is read
- * after req_id update is observed
+ /* Ensure PHC payload (timestamp, error_bound, error_flags)
+ * is read after req_id update is observed
*/
dma_rmb();
/* req_id was updated by the device which indicates that
- * PHC timestamp and error_flags are updated too,
- * checking errors before retrieving timestamp
+ * PHC timestamp, error_bound and error_flags are updated too,
+ * checking error flags before retrieving timestamp and
+ * error_bound values
*/
if (unlikely(resp->error_flags & ENA_PHC_ERROR_FLAGS)) {
- /* Retrieved invalid PHC timestamp, PHC enters into
- * blocked state until passing blocking time,
- * during this time any get PHC timestamp requests
- * will fail with device busy error
+ /* Retrieved timestamp or error bound errors,
+ * PHC enters into blocked state until passing blocking
+ * time, during this time, any request will fail with
+ * device busy error
*/
ret = -EBUSY;
break;
@@ -1902,12 +1909,15 @@ int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp)
/* PHC timestamp value is returned to the caller */
*timestamp = resp->timestamp;
+ if (error_bound)
+ *error_bound = resp->error_bound;
/* Update statistic on valid PHC timestamp retrieval */
phc->stats.phc_cnt++;
/* This indicates PHC state is active */
phc->system_time = zero_system_time;
+
break;
}
diff --git a/drivers/net/ethernet/amazon/ena/ena_com.h b/drivers/net/ethernet/amazon/ena/ena_com.h
index 64df2c48c9a6..fcbff1a9eb7a 100644
--- a/drivers/net/ethernet/amazon/ena/ena_com.h
+++ b/drivers/net/ethernet/amazon/ena/ena_com.h
@@ -216,6 +216,7 @@ struct ena_com_stats_phc {
u64 phc_skp;
u64 phc_err_dv;
u64 phc_err_ts;
+ u64 phc_err_eb;
};
struct ena_com_admin_queue {
@@ -462,9 +463,11 @@ void ena_com_phc_destroy(struct ena_com_dev *ena_dev);
/* ena_com_phc_get_timestamp - Retrieve PHC timestamp
* @ena_dev: ENA communication layer struct
* @timestamp: Retrieved PHC timestamp
+ * @error_bound: maximum possible deviation of the timestamp (nanosecond)
* @return - 0 on success, negative value on failure
*/
-int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp);
+int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp,
+ u32 *error_bound);
/* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism
* @ena_dev: ENA communication layer struct
diff --git a/drivers/net/ethernet/amazon/ena/ena_debugfs.c b/drivers/net/ethernet/amazon/ena/ena_debugfs.c
index 46ed80986724..db9d1843996b 100644
--- a/drivers/net/ethernet/amazon/ena/ena_debugfs.c
+++ b/drivers/net/ethernet/amazon/ena/ena_debugfs.c
@@ -32,6 +32,9 @@ static int phc_stats_show(struct seq_file *file, void *priv)
seq_printf(file,
"phc_err_ts: %llu\n",
adapter->ena_dev->phc.stats.phc_err_ts);
+ seq_printf(file,
+ "phc_err_eb: %llu\n",
+ adapter->ena_dev->phc.stats.phc_err_eb);
return 0;
}
diff --git a/drivers/net/ethernet/amazon/ena/ena_phc.c b/drivers/net/ethernet/amazon/ena/ena_phc.c
index c2a3ff1ef645..2bcb5af564e2 100644
--- a/drivers/net/ethernet/amazon/ena/ena_phc.c
+++ b/drivers/net/ethernet/amazon/ena/ena_phc.c
@@ -40,7 +40,8 @@ static int ena_phc_gettimex64(struct ptp_clock_info *clock_info,
ptp_read_system_prets(sts);
rc = ena_com_phc_get_timestamp(phc_info->adapter->ena_dev,
- ×tamp_nsec);
+ ×tamp_nsec,
+ NULL);
ptp_read_system_postts(sts);
--
2.47.3
^ permalink raw reply related
* [PATCH v4 net-next 5/7] net: ena: Update PHC admin interface for error bound support
From: Arthur Kiyanovski @ 2026-07-14 2:03 UTC (permalink / raw)
To: David Miller, Jakub Kicinski, netdev
Cc: Arthur Kiyanovski, Richard Cochran, Eric Dumazet, Paolo Abeni,
David Woodhouse, Thomas Gleixner, Miroslav Lichvar, Andrew Lunn,
Wen Gu, Xuan Zhuo, David Woodhouse, Yonatan Sarna,
Zorik Machulsky, Alexander Matushevsky, Saeed Bshara, Matt Wilson,
Anthony Liguori, Nafea Bshara, Evgeny Schmeilin, Netanel Belgazal,
Ali Saidi, Benjamin Herrenschmidt, Noam Dagan, David Arinzon,
Evgeny Ostrovsky, Ofir Tabachnik, Amit Bernstein, linux-kselftest,
linux-doc, shuah, Jonathan Corbet, Shuah Khan, Simon Horman,
vadim.fedorenko
In-Reply-To: <20260714020340.25014-1-akiyano@amazon.com>
Extend the ENA admin interface to support error bound.
Add error_bound to the PHC response structure.
Introduce a feature version mechanism to indicate device supports
error_bound, and add an error flag for error_bound retrieval failures.
This enables the driver to retrieve error_bound information from the
device alongside timestamps.
Signed-off-by: Amit Bernstein <amitbern@amazon.com>
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
---
.../net/ethernet/amazon/ena/ena_admin_defs.h | 17 +++++++++++------
drivers/net/ethernet/amazon/ena/ena_com.c | 11 ++++++-----
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/amazon/ena/ena_admin_defs.h b/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
index 898ecd96b96a..2d132c4bc590 100644
--- a/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
+++ b/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
@@ -128,12 +128,14 @@ enum ena_admin_get_stats_scope {
ENA_ADMIN_ETH_TRAFFIC = 1,
};
-enum ena_admin_phc_type {
- ENA_ADMIN_PHC_TYPE_READLESS = 0,
+enum ena_admin_phc_feature_version {
+ /* Readless with error_bound */
+ ENA_ADMIN_PHC_FEATURE_VERSION_0 = 0,
};
enum ena_admin_phc_error_flags {
ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP = BIT(0),
+ ENA_ADMIN_PHC_ERROR_FLAG_ERROR_BOUND = BIT(1),
};
/* ENA SRD configuration for ENI */
@@ -1035,10 +1037,10 @@ struct ena_admin_queue_ext_feature_desc {
};
struct ena_admin_feature_phc_desc {
- /* PHC type as defined in enum ena_admin_get_phc_type,
- * used only for GET command.
+ /* PHC version as defined in enum ena_admin_phc_feature_version,
+ * used only for GET command as max supported PHC version by the device.
*/
- u8 type;
+ u8 version;
/* Reserved - MBZ */
u8 reserved1[3];
@@ -1224,7 +1226,10 @@ struct ena_admin_phc_resp {
/* PHC timestamp (nsec) */
u64 timestamp;
- u8 reserved2[12];
+ u8 reserved2[8];
+
+ /* Timestamp error limit (nsec) */
+ u32 error_bound;
/* Bit field of enum ena_admin_phc_error_flags */
u32 error_flags;
diff --git a/drivers/net/ethernet/amazon/ena/ena_com.c b/drivers/net/ethernet/amazon/ena/ena_com.c
index 297fb36ab8c1..40d1fd64bc34 100644
--- a/drivers/net/ethernet/amazon/ena/ena_com.c
+++ b/drivers/net/ethernet/amazon/ena/ena_com.c
@@ -1682,11 +1682,11 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev)
struct ena_admin_set_feat_cmd set_feat_cmd;
int ret = 0;
- /* Get device PHC default configuration */
+ /* Get default device PHC configuration */
ret = ena_com_get_feature(ena_dev,
&get_feat_resp,
ENA_ADMIN_PHC_CONFIG,
- 0);
+ ENA_ADMIN_PHC_FEATURE_VERSION_0);
if (unlikely(ret)) {
netdev_err(ena_dev->net_device,
"Failed to get PHC feature configuration, error: %d\n",
@@ -1694,10 +1694,11 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev)
return ret;
}
- /* Supporting only readless PHC retrieval */
- if (get_feat_resp.u.phc.type != ENA_ADMIN_PHC_TYPE_READLESS) {
+ /* Supporting only PHC V0 (readless mode with error bound) */
+ if (get_feat_resp.u.phc.version != ENA_ADMIN_PHC_FEATURE_VERSION_0) {
netdev_err(ena_dev->net_device,
- "Unsupported PHC type, error: %d\n",
+ "Unsupported PHC version (0x%X), error: %d\n",
+ get_feat_resp.u.phc.version,
-EOPNOTSUPP);
return -EOPNOTSUPP;
}
--
2.47.3
^ permalink raw reply related
* [PATCH v4 net-next 4/7] ptp: ptp_vmclock: Implement attributes ioctls
From: Arthur Kiyanovski @ 2026-07-14 2:03 UTC (permalink / raw)
To: David Miller, Jakub Kicinski, netdev
Cc: Arthur Kiyanovski, Richard Cochran, Eric Dumazet, Paolo Abeni,
David Woodhouse, Thomas Gleixner, Miroslav Lichvar, Andrew Lunn,
Wen Gu, Xuan Zhuo, David Woodhouse, Yonatan Sarna,
Zorik Machulsky, Alexander Matushevsky, Saeed Bshara, Matt Wilson,
Anthony Liguori, Nafea Bshara, Evgeny Schmeilin, Netanel Belgazal,
Ali Saidi, Benjamin Herrenschmidt, Noam Dagan, David Arinzon,
Evgeny Ostrovsky, Ofir Tabachnik, Amit Bernstein, linux-kselftest,
linux-doc, shuah, Jonathan Corbet, Shuah Khan, Simon Horman,
vadim.fedorenko
In-Reply-To: <20260714020340.25014-1-akiyano@amazon.com>
Implement the gettimexattrs64 and getcrosststampattrs callbacks in the
ptp_vmclock driver to provide clock quality attributes through the new
PTP_SYS_OFFSET_EXTENDED_ATTRS and PTP_SYS_OFFSET_PRECISE_ATTRS ioctls.
The ptp_vmclock device exposes:
- error_bound: Derived from time_maxerror_nanosec, accumulated with
counter frequency error (counter_period_maxerror_rate_frac_sec) over
elapsed counter ticks
- clock_status: Mapped from the device's clock_status field
- timescale: Always reports TAI (UTC sources are converted by tai_adjust()
before the attributes are populated)
The legacy ioctls return -EINVAL when clock_status is UNRELIABLE since
they have no way to communicate clock state to userspace. The attrs
ioctls have a status field for this purpose, so they treat UNRELIABLE
as success and let userspace check the status field.
To avoid a race where the hypervisor could update clock_status between
the timestamp call and the UNRELIABLE check, the clock state is captured
inside the seq_count loop for a consistent snapshot with the timestamp.
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
---
drivers/ptp/ptp_vmclock.c | 197 ++++++++++++++++++++++++++++++++++----
1 file changed, 181 insertions(+), 16 deletions(-)
diff --git a/drivers/ptp/ptp_vmclock.c b/drivers/ptp/ptp_vmclock.c
index eebdcd5ebc08..16b728c0f591 100644
--- a/drivers/ptp/ptp_vmclock.c
+++ b/drivers/ptp/ptp_vmclock.c
@@ -53,6 +53,17 @@ struct vmclock_state {
char *name;
};
+/**
+ * struct vmclock_crosststamp_ctx - context for get_device_system_crosststamp()
+ * @st: vmclock device state
+ * @attrs: optional output for PTP clock attributes, populated inside the
+ * seq_count loop for a consistent snapshot with the timestamp
+ */
+struct vmclock_crosststamp_ctx {
+ struct vmclock_state *st;
+ struct ptp_clock_attrs *attrs;
+};
+
#define VMCLOCK_MAX_WAIT ms_to_ktime(100)
/* Require at least the flags field to be present. All else can be optional. */
@@ -95,13 +106,111 @@ static bool tai_adjust(struct vmclock_abi *clk, uint64_t *sec)
return false;
}
+static uint8_t vmclock_get_ptp_timescale(uint8_t vmclock_time_type)
+{
+ switch (vmclock_time_type) {
+ case VMCLOCK_TIME_UTC:
+ return PTP_TIMESCALE_UTC;
+ case VMCLOCK_TIME_TAI:
+ return PTP_TIMESCALE_TAI;
+ case VMCLOCK_TIME_MONOTONIC:
+ return PTP_TIMESCALE_MONOTONIC;
+ default:
+ return PTP_TIMESCALE_UNKNOWN;
+ }
+}
+
+static uint8_t vmclock_get_ptp_status(uint8_t vmclock_status)
+{
+ switch (vmclock_status) {
+ case VMCLOCK_STATUS_UNKNOWN:
+ return PTP_CLOCK_STATUS_UNKNOWN;
+ case VMCLOCK_STATUS_INITIALIZING:
+ return PTP_CLOCK_STATUS_INITIALIZING;
+ case VMCLOCK_STATUS_SYNCHRONIZED:
+ return PTP_CLOCK_STATUS_SYNCED;
+ case VMCLOCK_STATUS_FREERUNNING:
+ return PTP_CLOCK_STATUS_FREE_RUNNING;
+ case VMCLOCK_STATUS_UNRELIABLE:
+ return PTP_CLOCK_STATUS_UNRELIABLE;
+ default:
+ return PTP_CLOCK_STATUS_UNKNOWN;
+ }
+}
+
+static void vmclock_populate_ptp_attributes(struct vmclock_state *st,
+ struct ptp_clock_attrs *att,
+ uint64_t delta)
+{
+ uint64_t maxerror_ns = UINT_MAX;
+
+ if (!att)
+ return;
+
+ /* Only calculate if the base error is flagged as valid
+ * by the hypervisor.
+ */
+ if (VMCLOCK_FIELD_PRESENT(st->clk, time_maxerror_nanosec) &&
+ (le64_to_cpu(st->clk->flags) & VMCLOCK_FLAG_TIME_MAXERROR_VALID)) {
+ maxerror_ns = le64_to_cpu(st->clk->time_maxerror_nanosec);
+
+ /* If frequency error is also valid, accumulate it
+ * over the delta.
+ */
+ if (VMCLOCK_FIELD_PRESENT(st->clk, counter_period_maxerror_rate_frac_sec) &&
+ (le64_to_cpu(st->clk->flags) & VMCLOCK_FLAG_PERIOD_MAXERROR_VALID)) {
+ uint64_t maxerror_rate, err_hi, err_frac, growth_ns;
+
+ if (st->clk->counter_period_shift >= 128) {
+ maxerror_ns = U64_MAX;
+ goto saturate;
+ }
+
+ maxerror_rate = le64_to_cpu(st->clk->counter_period_maxerror_rate_frac_sec);
+ err_frac = mul_u64_u64_shr_add_u64(&err_hi, delta,
+ maxerror_rate,
+ st->clk->counter_period_shift,
+ 0);
+
+ if (err_hi >= U64_MAX / NSEC_PER_SEC) {
+ maxerror_ns = U64_MAX;
+ goto saturate;
+ }
+
+ growth_ns = (err_hi * NSEC_PER_SEC) +
+ mul_u64_u64_shr(err_frac, NSEC_PER_SEC, 64);
+
+ /* Guard against overflow */
+ if (U64_MAX - growth_ns < maxerror_ns)
+ maxerror_ns = U64_MAX;
+ else
+ maxerror_ns += growth_ns;
+ }
+ }
+
+saturate:
+ /* PTP UAPI error_bound is 32-bit nanoseconds */
+ att->error_bound = (maxerror_ns > UINT_MAX) ?
+ UINT_MAX : (uint32_t)maxerror_ns;
+ att->valid |= PTP_ATTRS_VALID_ERROR_BOUND;
+ att->timescale = vmclock_get_ptp_timescale(st->clk->time_type);
+ /* tai_adjust() already converted UTC to TAI before we're called */
+ if (st->clk->time_type == VMCLOCK_TIME_UTC)
+ att->timescale = PTP_TIMESCALE_TAI;
+ att->valid |= PTP_ATTRS_VALID_TIMESCALE;
+ att->status = vmclock_get_ptp_status(st->clk->clock_status);
+ att->valid |= PTP_ATTRS_VALID_STATUS;
+}
+
static int vmclock_get_crosststamp(struct vmclock_state *st,
struct ptp_system_timestamp *sts,
struct system_counterval_t *system_counter,
- struct timespec64 *tspec)
+ struct timespec64 *tspec,
+ struct ptp_clock_attrs *attrs)
{
ktime_t deadline = ktime_add(ktime_get(), VMCLOCK_MAX_WAIT);
uint64_t cycle, delta, seq, frac_sec;
+ uint8_t clock_status = VMCLOCK_STATUS_UNKNOWN;
#ifdef CONFIG_X86
/*
@@ -121,9 +230,6 @@ static int vmclock_get_crosststamp(struct vmclock_state *st,
*/
virt_rmb();
- if (st->clk->clock_status == VMCLOCK_STATUS_UNRELIABLE)
- return -EINVAL;
-
/*
* When invoked for gettimex64(), fill in the pre/post system
* times. The simple case is when system time is based on the
@@ -164,6 +270,17 @@ static int vmclock_get_crosststamp(struct vmclock_state *st,
if (!tai_adjust(st->clk, &tspec->tv_sec))
return -EINVAL;
+ /*
+ * Capture clock state inside the seq_count loop for a
+ * consistent snapshot with the timestamp. The attrs path
+ * reports it to userspace via the status field; the legacy
+ * path saves it for the UNRELIABLE check after the loop.
+ */
+ if (attrs)
+ vmclock_populate_ptp_attributes(st, attrs, delta);
+ else
+ clock_status = st->clk->clock_status;
+
/*
* This pairs with a write barrier in the hypervisor
* which populates this structure.
@@ -181,6 +298,17 @@ static int vmclock_get_crosststamp(struct vmclock_state *st,
system_counter->cs_id = st->cs_id;
}
+ /*
+ * If attrs is set, attributes were already populated inside the
+ * seq_count loop. Return success even for UNRELIABLE — the attrs
+ * ioctl can report the status to userspace.
+ */
+ if (attrs)
+ return 0;
+
+ if (clock_status == VMCLOCK_STATUS_UNRELIABLE)
+ return -EINVAL;
+
return 0;
}
@@ -193,7 +321,8 @@ static int vmclock_get_crosststamp(struct vmclock_state *st,
static int vmclock_get_crosststamp_kvmclock(struct vmclock_state *st,
struct ptp_system_timestamp *sts,
struct system_counterval_t *system_counter,
- struct timespec64 *tspec)
+ struct timespec64 *tspec,
+ struct ptp_clock_attrs *attrs)
{
struct pvclock_vcpu_time_info *pvti = this_cpu_pvti();
unsigned int pvti_ver;
@@ -204,7 +333,8 @@ static int vmclock_get_crosststamp_kvmclock(struct vmclock_state *st,
do {
pvti_ver = pvclock_read_begin(pvti);
- ret = vmclock_get_crosststamp(st, sts, system_counter, tspec);
+ ret = vmclock_get_crosststamp(st, sts, system_counter, tspec,
+ attrs);
if (ret)
break;
@@ -233,17 +363,19 @@ static int ptp_vmclock_get_time_fn(ktime_t *device_time,
struct system_counterval_t *system_counter,
void *ctx)
{
- struct vmclock_state *st = ctx;
+ struct vmclock_crosststamp_ctx *vctx = ctx;
+ struct vmclock_state *st = vctx->st;
struct timespec64 tspec;
int ret;
#ifdef SUPPORT_KVMCLOCK
if (READ_ONCE(st->sys_cs_id) == CSID_X86_KVM_CLK)
ret = vmclock_get_crosststamp_kvmclock(st, NULL, system_counter,
- &tspec);
+ &tspec, vctx->attrs);
else
#endif
- ret = vmclock_get_crosststamp(st, NULL, system_counter, &tspec);
+ ret = vmclock_get_crosststamp(st, NULL, system_counter, &tspec,
+ vctx->attrs);
if (!ret)
*device_time = timespec64_to_ktime(tspec);
@@ -251,12 +383,11 @@ static int ptp_vmclock_get_time_fn(ktime_t *device_time,
return ret;
}
-static int ptp_vmclock_getcrosststamp(struct ptp_clock_info *ptp,
- struct system_device_crosststamp *xtstamp)
+static int ptp_vmclock_do_getcrosststamp(struct vmclock_crosststamp_ctx *vctx,
+ struct system_device_crosststamp *xtstamp)
{
- struct vmclock_state *st = container_of(ptp, struct vmclock_state,
- ptp_clock_info);
- int ret = get_device_system_crosststamp(ptp_vmclock_get_time_fn, st,
+ struct vmclock_state *st = vctx->st;
+ int ret = get_device_system_crosststamp(ptp_vmclock_get_time_fn, vctx,
NULL, xtstamp);
#ifdef SUPPORT_KVMCLOCK
/*
@@ -273,13 +404,23 @@ static int ptp_vmclock_getcrosststamp(struct ptp_clock_info *ptp,
systime_snapshot.cs_id == CSID_X86_KVM_CLK) {
WRITE_ONCE(st->sys_cs_id, systime_snapshot.cs_id);
ret = get_device_system_crosststamp(ptp_vmclock_get_time_fn,
- st, NULL, xtstamp);
+ vctx, NULL, xtstamp);
}
}
#endif
return ret;
}
+static int ptp_vmclock_getcrosststamp(struct ptp_clock_info *ptp,
+ struct system_device_crosststamp *xtstamp)
+{
+ struct vmclock_state *st = container_of(ptp, struct vmclock_state,
+ ptp_clock_info);
+ struct vmclock_crosststamp_ctx vctx = { .st = st };
+
+ return ptp_vmclock_do_getcrosststamp(&vctx, xtstamp);
+}
+
/*
* PTP clock operations
*/
@@ -306,7 +447,29 @@ static int ptp_vmclock_gettimex(struct ptp_clock_info *ptp, struct timespec64 *t
struct vmclock_state *st = container_of(ptp, struct vmclock_state,
ptp_clock_info);
- return vmclock_get_crosststamp(st, sts, NULL, ts);
+ return vmclock_get_crosststamp(st, sts, NULL, ts, NULL);
+}
+
+static int ptp_vmclock_gettimexattrs(struct ptp_clock_info *ptp,
+ struct timespec64 *ts,
+ struct ptp_system_timestamp *sts,
+ struct ptp_clock_attrs *att)
+{
+ struct vmclock_state *st = container_of(ptp, struct vmclock_state,
+ ptp_clock_info);
+
+ return vmclock_get_crosststamp(st, sts, NULL, ts, att);
+}
+
+static int ptp_vmclock_getcrosststampattrs(struct ptp_clock_info *ptp,
+ struct system_device_crosststamp *xtstamp,
+ struct ptp_clock_attrs *att)
+{
+ struct vmclock_state *st = container_of(ptp, struct vmclock_state,
+ ptp_clock_info);
+ struct vmclock_crosststamp_ctx vctx = { .st = st, .attrs = att };
+
+ return ptp_vmclock_do_getcrosststamp(&vctx, xtstamp);
}
static int ptp_vmclock_enable(struct ptp_clock_info *ptp,
@@ -324,9 +487,11 @@ static const struct ptp_clock_info ptp_vmclock_info = {
.adjfine = ptp_vmclock_adjfine,
.adjtime = ptp_vmclock_adjtime,
.gettimex64 = ptp_vmclock_gettimex,
+ .gettimexattrs64 = ptp_vmclock_gettimexattrs,
.settime64 = ptp_vmclock_settime,
.enable = ptp_vmclock_enable,
.getcrosststamp = ptp_vmclock_getcrosststamp,
+ .getcrosststampattrs = ptp_vmclock_getcrosststampattrs,
};
static struct ptp_clock *vmclock_ptp_register(struct device *dev,
--
2.47.3
^ permalink raw reply related
* [PATCH v4 net-next 3/7] selftests/ptp: Add testptp support for attributes ioctls
From: Arthur Kiyanovski @ 2026-07-14 2:03 UTC (permalink / raw)
To: David Miller, Jakub Kicinski, netdev
Cc: Arthur Kiyanovski, Richard Cochran, Eric Dumazet, Paolo Abeni,
David Woodhouse, Thomas Gleixner, Miroslav Lichvar, Andrew Lunn,
Wen Gu, Xuan Zhuo, David Woodhouse, Yonatan Sarna,
Zorik Machulsky, Alexander Matushevsky, Saeed Bshara, Matt Wilson,
Anthony Liguori, Nafea Bshara, Evgeny Schmeilin, Netanel Belgazal,
Ali Saidi, Benjamin Herrenschmidt, Noam Dagan, David Arinzon,
Evgeny Ostrovsky, Ofir Tabachnik, Amit Bernstein, linux-kselftest,
linux-doc, shuah, Jonathan Corbet, Shuah Khan, Simon Horman,
vadim.fedorenko
In-Reply-To: <20260714020340.25014-1-akiyano@amazon.com>
Add support for testing the new PTP_SYS_OFFSET_EXTENDED_ATTRS and
PTP_SYS_OFFSET_PRECISE_ATTRS ioctls in the testptp utility.
New command-line options:
-a: Get extended offset with attributes (error_bound, clock_status,
timescale)
-A: Get precise cross-timestamp with attributes
These options allow testing and validation of PHC devices that provide
clock quality information alongside timestamps.
Also display the new clock_attrs capability in the -c output, and
update print_system_timestamp to print unrecognized clock types instead
of silently dropping them.
Signed-off-by: Amit Bernstein <amitbern@amazon.com>
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
---
tools/testing/selftests/ptp/testptp.c | 111 +++++++++++++++++++++++++-
1 file changed, 109 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/ptp/testptp.c b/tools/testing/selftests/ptp/testptp.c
index d3bcfd03fce4..99607da01b22 100644
--- a/tools/testing/selftests/ptp/testptp.c
+++ b/tools/testing/selftests/ptp/testptp.c
@@ -147,10 +147,13 @@ static void usage(char *progname)
" -t val shift the ptp clock time by 'val' seconds\n"
" -T val set the ptp clock time to 'val' seconds\n"
" -x val get an extended ptp clock time with the desired number of samples (up to %d)\n"
+ " -a val get extended timestamps with attributes (error_bound,\n"
+ " clock_status, timescale, counter), up to %d samples\n"
" -X get a ptp clock cross timestamp\n"
+ " -A get a precise cross timestamp with attributes\n"
" -y val pre/post tstamp timebase to use {realtime|monotonic|monotonic-raw}\n"
" -z test combinations of rising/falling external time stamp flags\n",
- progname, PTP_MAX_SAMPLES);
+ progname, PTP_MAX_SAMPLES, PTP_MAX_SAMPLES);
}
static void print_system_timestamp(int sample_num, __kernel_clockid_t clockid,
@@ -171,6 +174,8 @@ static void print_system_timestamp(int sample_num, __kernel_clockid_t clockid,
sample_num, when, sec, nsec);
break;
default:
+ printf("sample #%2d: unknown clock %d %s: %lld.%09u\n",
+ sample_num, clockid, when, sec, nsec);
break;
}
}
@@ -188,6 +193,7 @@ int main(int argc, char *argv[])
struct ptp_sys_offset *sysoff;
struct ptp_sys_offset_extended *soe;
struct ptp_sys_offset_precise *xts;
+ struct ptp_sys_offset_attrs *attrs_data;
char *progname;
unsigned int i;
@@ -208,7 +214,9 @@ int main(int argc, char *argv[])
int list_pins = 0;
int pct_offset = 0;
int getextended = 0;
+ int getextendedattrs = 0;
int getcross = 0;
+ int getcrossattrs = 0;
int n_samples = 0;
int pin_index = -1, pin_func;
int pps = -1;
@@ -226,7 +234,8 @@ int main(int argc, char *argv[])
progname = strrchr(argv[0], '/');
progname = progname ? 1+progname : argv[0];
- while (EOF != (c = getopt(argc, argv, "cd:e:E:f:F:ghH:i:k:lL:n:o:p:P:rsSt:T:w:x:Xy:z"))) {
+ while (EOF != (c = getopt(argc, argv,
+ "a:Acd:e:E:f:F:ghH:i:k:lL:n:o:p:P:rsSt:T:w:x:Xy:z"))) {
switch (c) {
case 'c':
capabilities = 1;
@@ -311,9 +320,22 @@ int main(int argc, char *argv[])
return -1;
}
break;
+ case 'a':
+ getextendedattrs = atoi(optarg);
+ if (getextendedattrs < 1 ||
+ getextendedattrs > PTP_MAX_SAMPLES) {
+ fprintf(stderr,
+ "number of extended attrs timestamp samples must be between 1 and %d; was asked for %d\n",
+ PTP_MAX_SAMPLES, getextendedattrs);
+ return -1;
+ }
+ break;
case 'X':
getcross = 1;
break;
+ case 'A':
+ getcrossattrs = 1;
+ break;
case 'y':
if (!strcasecmp(optarg, "realtime"))
ext_clockid = CLOCK_REALTIME;
@@ -367,6 +389,8 @@ int main(int argc, char *argv[])
" %d programmable pins\n"
" %d cross timestamping\n"
" %d adjust_phase\n"
+ " %d extended_attrs\n"
+ " %d precise_attrs\n"
" %d maximum phase adjustment (ns)\n",
caps.max_adj,
caps.n_alarm,
@@ -376,6 +400,8 @@ int main(int argc, char *argv[])
caps.n_pins,
caps.cross_timestamping,
caps.adjust_phase,
+ caps.extended_attrs,
+ caps.precise_attrs,
caps.max_phase_adj);
}
}
@@ -648,6 +674,49 @@ int main(int argc, char *argv[])
free(soe);
}
+ if (getextendedattrs) {
+ attrs_data = calloc(1, sizeof(*attrs_data) +
+ getextendedattrs * sizeof(struct ptp_timestamp));
+ if (!attrs_data) {
+ perror("calloc");
+ return -1;
+ }
+
+ attrs_data->request.num_samples = getextendedattrs;
+ attrs_data->request.clock_id = ext_clockid;
+
+ if (ioctl(fd, PTP_SYS_OFFSET_EXTENDED_ATTRS, attrs_data)) {
+ perror("PTP_SYS_OFFSET_EXTENDED_ATTRS");
+ } else {
+ printf("extended attrs timestamp request returned %d samples\n",
+ getextendedattrs);
+
+ for (i = 0; i < getextendedattrs; i++) {
+ struct ptp_timestamp *ts = &attrs_data->timestamps[i];
+
+ printf(" sample #%u:\n", i);
+ printf(" sys before: %lld ns\n",
+ (long long)ts->pre_systime.sys_time);
+ printf(" phc time: %lld.%09u\n",
+ ts->devtime.device_time.sec,
+ ts->devtime.device_time.nsec);
+ if (ts->devtime.attrs.valid & PTP_ATTRS_VALID_ERROR_BOUND)
+ printf(" error_bound: %u ns\n",
+ ts->devtime.attrs.error_bound);
+ if (ts->devtime.attrs.valid & PTP_ATTRS_VALID_STATUS)
+ printf(" status: %u\n",
+ ts->devtime.attrs.status);
+ if (ts->devtime.attrs.valid & PTP_ATTRS_VALID_TIMESCALE)
+ printf(" timescale: %u\n",
+ ts->devtime.attrs.timescale);
+ printf(" sys after: %lld ns\n",
+ (long long)ts->post_systime.sys_time);
+ }
+ }
+
+ free(attrs_data);
+ }
+
if (getcross) {
xts = calloc(1, sizeof(*xts));
if (!xts) {
@@ -671,6 +740,44 @@ int main(int argc, char *argv[])
free(xts);
}
+ if (getcrossattrs) {
+ attrs_data = calloc(1, sizeof(*attrs_data) +
+ sizeof(struct ptp_timestamp));
+ if (!attrs_data) {
+ perror("calloc");
+ return -1;
+ }
+
+ attrs_data->request.num_samples = 1;
+ attrs_data->request.clock_id = ext_clockid;
+
+ if (ioctl(fd, PTP_SYS_OFFSET_PRECISE_ATTRS, attrs_data)) {
+ perror("PTP_SYS_OFFSET_PRECISE_ATTRS");
+ } else {
+ struct ptp_timestamp *ts = &attrs_data->timestamps[0];
+
+ puts("precise attrs crosstimestamp request okay");
+ printf("device time: %lld.%09u\n",
+ ts->devtime.device_time.sec,
+ ts->devtime.device_time.nsec);
+ printf("system time: %lld ns\n",
+ (long long)ts->systime.sys_time);
+ printf("raw time: %lld ns\n",
+ (long long)ts->systime.sys_rawtime);
+ if (ts->devtime.attrs.valid & PTP_ATTRS_VALID_ERROR_BOUND)
+ printf("error_bound: %u ns\n",
+ ts->devtime.attrs.error_bound);
+ if (ts->devtime.attrs.valid & PTP_ATTRS_VALID_STATUS)
+ printf("status: %u\n",
+ ts->devtime.attrs.status);
+ if (ts->devtime.attrs.valid & PTP_ATTRS_VALID_TIMESCALE)
+ printf("timescale: %u\n",
+ ts->devtime.attrs.timescale);
+ }
+
+ free(attrs_data);
+ }
+
if (channel >= 0) {
if (ioctl(fd, PTP_MASK_CLEAR_ALL)) {
perror("PTP_MASK_CLEAR_ALL");
--
2.47.3
^ permalink raw reply related
* [PATCH v4 net-next 2/7] selftests/ptp: Extract print_system_timestamp helper in testptp
From: Arthur Kiyanovski @ 2026-07-14 2:03 UTC (permalink / raw)
To: David Miller, Jakub Kicinski, netdev
Cc: Arthur Kiyanovski, Richard Cochran, Eric Dumazet, Paolo Abeni,
David Woodhouse, Thomas Gleixner, Miroslav Lichvar, Andrew Lunn,
Wen Gu, Xuan Zhuo, David Woodhouse, Yonatan Sarna,
Zorik Machulsky, Alexander Matushevsky, Saeed Bshara, Matt Wilson,
Anthony Liguori, Nafea Bshara, Evgeny Schmeilin, Netanel Belgazal,
Ali Saidi, Benjamin Herrenschmidt, Noam Dagan, David Arinzon,
Evgeny Ostrovsky, Ofir Tabachnik, Amit Bernstein, linux-kselftest,
linux-doc, shuah, Jonathan Corbet, Shuah Khan, Simon Horman,
vadim.fedorenko
In-Reply-To: <20260714020340.25014-1-akiyano@amazon.com>
Extract the repeated switch-on-clockid pattern used for printing
system timestamps into a reusable helper function. This removes
code duplication in the -x (PTP_SYS_OFFSET_EXTENDED) output path
and prepares for additional callers.
The "after" timestamp lines now include the sample number prefix
for consistency with the "before" lines, slightly changing the
output format.
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
---
tools/testing/selftests/ptp/testptp.c | 70 ++++++++++++---------------
1 file changed, 32 insertions(+), 38 deletions(-)
diff --git a/tools/testing/selftests/ptp/testptp.c b/tools/testing/selftests/ptp/testptp.c
index ed1e2886ba3c..d3bcfd03fce4 100644
--- a/tools/testing/selftests/ptp/testptp.c
+++ b/tools/testing/selftests/ptp/testptp.c
@@ -153,6 +153,28 @@ static void usage(char *progname)
progname, PTP_MAX_SAMPLES);
}
+static void print_system_timestamp(int sample_num, __kernel_clockid_t clockid,
+ long long sec, unsigned int nsec,
+ const char *when)
+{
+ switch (clockid) {
+ case CLOCK_REALTIME:
+ printf("sample #%2d: real time %s: %lld.%09u\n",
+ sample_num, when, sec, nsec);
+ break;
+ case CLOCK_MONOTONIC:
+ printf("sample #%2d: monotonic time %s: %lld.%09u\n",
+ sample_num, when, sec, nsec);
+ break;
+ case CLOCK_MONOTONIC_RAW:
+ printf("sample #%2d: monotonic-raw time %s: %lld.%09u\n",
+ sample_num, when, sec, nsec);
+ break;
+ default:
+ break;
+ }
+}
+
int main(int argc, char *argv[])
{
struct ptp_clock_caps caps;
@@ -608,46 +630,18 @@ int main(int argc, char *argv[])
getextended);
for (i = 0; i < getextended; i++) {
- switch (ext_clockid) {
- case CLOCK_REALTIME:
- printf("sample #%2d: real time before: %lld.%09u\n",
- i, soe->ts[i][0].sec,
- soe->ts[i][0].nsec);
- break;
- case CLOCK_MONOTONIC:
- printf("sample #%2d: monotonic time before: %lld.%09u\n",
- i, soe->ts[i][0].sec,
- soe->ts[i][0].nsec);
- break;
- case CLOCK_MONOTONIC_RAW:
- printf("sample #%2d: monotonic-raw time before: %lld.%09u\n",
- i, soe->ts[i][0].sec,
- soe->ts[i][0].nsec);
- break;
- default:
- break;
- }
+ print_system_timestamp(i, ext_clockid,
+ soe->ts[i][0].sec,
+ soe->ts[i][0].nsec,
+ "before");
+
printf(" phc time: %lld.%09u\n",
soe->ts[i][1].sec, soe->ts[i][1].nsec);
- switch (ext_clockid) {
- case CLOCK_REALTIME:
- printf(" real time after: %lld.%09u\n",
- soe->ts[i][2].sec,
- soe->ts[i][2].nsec);
- break;
- case CLOCK_MONOTONIC:
- printf(" monotonic time after: %lld.%09u\n",
- soe->ts[i][2].sec,
- soe->ts[i][2].nsec);
- break;
- case CLOCK_MONOTONIC_RAW:
- printf(" monotonic-raw time after: %lld.%09u\n",
- soe->ts[i][2].sec,
- soe->ts[i][2].nsec);
- break;
- default:
- break;
- }
+
+ print_system_timestamp(i, ext_clockid,
+ soe->ts[i][2].sec,
+ soe->ts[i][2].nsec,
+ "after");
}
}
--
2.47.3
^ permalink raw reply related
* [PATCH v4 net-next 1/7] ptp: Add ioctls for PHC timestamps with quality attributes
From: Arthur Kiyanovski @ 2026-07-14 2:03 UTC (permalink / raw)
To: David Miller, Jakub Kicinski, netdev
Cc: Arthur Kiyanovski, Richard Cochran, Eric Dumazet, Paolo Abeni,
David Woodhouse, Thomas Gleixner, Miroslav Lichvar, Andrew Lunn,
Wen Gu, Xuan Zhuo, David Woodhouse, Yonatan Sarna,
Zorik Machulsky, Alexander Matushevsky, Saeed Bshara, Matt Wilson,
Anthony Liguori, Nafea Bshara, Evgeny Schmeilin, Netanel Belgazal,
Ali Saidi, Benjamin Herrenschmidt, Noam Dagan, David Arinzon,
Evgeny Ostrovsky, Ofir Tabachnik, Amit Bernstein, linux-kselftest,
linux-doc, shuah, Jonathan Corbet, Shuah Khan, Simon Horman,
vadim.fedorenko
In-Reply-To: <20260714020340.25014-1-akiyano@amazon.com>
Introduce two new ioctls that extend existing PTP timestamp interfaces
with clock quality information:
- PTP_SYS_OFFSET_EXTENDED_ATTRS: Extends PTP_SYS_OFFSET_EXTENDED
- PTP_SYS_OFFSET_PRECISE_ATTRS: Extends PTP_SYS_OFFSET_PRECISE
These ioctls provide quality attributes alongside timestamps:
1. error_bound: Maximum deviation from true time (nanoseconds), based
on device's internal clock state
2. clock_status: Synchronization state (unknown, initializing,
synchronized, free-running, unreliable)
3. timescale: Time reference (TAI, UTC, etc.)
4. counter_value: Raw system counter (e.g. TSC ticks) captured by the
timekeeping core alongside each system timestamp
5. counter_id: Identifies the counter source (e.g. TSC, ARM arch counter)
This supports three use cases:
1. Managed PHC devices (e.g., ENA, vmclock) that maintain their own
synchronization and can report quality metrics directly to userspace
without requiring ptp4l
2. Applications that need complete time quality information in a single
call, regardless of how the PHC is synchronized
3. VMMs that need raw system counter values paired
with PTP timestamps for feed-forward clock calibration, avoiding the
feedback loop inherent in NTP-style synchronization
Timescale definitions use a Continuity/Discipline framework to describe
timeline properties and steering behavior consistently across all
entries.
This implementation is based on the original RFC and the UAPI design
discussion linked below.
Link: https://lore.kernel.org/netdev/20250724115657.150-1-darinzon@amazon.com/
Link: https://lore.kernel.org/all/87se7ht25o.ffs@tglx/
Signed-off-by: Amit Bernstein <amitbern@amazon.com>
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
---
drivers/ptp/ptp_chardev.c | 166 ++++++++++++++++++--
drivers/ptp/ptp_clock.c | 4 +-
include/linux/ptp_clock_kernel.h | 30 ++++
include/uapi/linux/ptp_clock.h | 254 ++++++++++++++++++++++++++++++-
4 files changed, 439 insertions(+), 15 deletions(-)
diff --git a/drivers/ptp/ptp_chardev.c b/drivers/ptp/ptp_chardev.c
index dc23cd708cfe..be33f8ead727 100644
--- a/drivers/ptp/ptp_chardev.c
+++ b/drivers/ptp/ptp_chardev.c
@@ -190,6 +190,8 @@ static long ptp_clock_getcaps(struct ptp_clock *ptp, void __user *arg)
.cross_timestamping = ptp->info->getcrosststamp != NULL,
.adjust_phase = ptp->info->adjphase != NULL &&
ptp->info->getmaxphase != NULL,
+ .extended_attrs = ptp->info->gettimexattrs64 != NULL,
+ .precise_attrs = ptp->info->getcrosststampattrs != NULL,
};
if (caps.adjust_phase)
@@ -347,11 +349,28 @@ typedef int (*ptp_gettimex_fn)(struct ptp_clock_info *,
struct timespec64 *,
struct ptp_system_timestamp *);
+static int ptp_validate_sys_offset_clockid(__kernel_clockid_t clockid)
+{
+ switch (clockid) {
+ case CLOCK_REALTIME:
+ case CLOCK_MONOTONIC:
+ case CLOCK_MONOTONIC_RAW:
+ return 0;
+ case CLOCK_AUX ... CLOCK_AUX_LAST:
+ if (IS_ENABLED(CONFIG_POSIX_AUX_CLOCKS))
+ return 0;
+ fallthrough;
+ default:
+ return -EINVAL;
+ }
+}
+
static long ptp_sys_offset_extended(struct ptp_clock *ptp, void __user *arg,
ptp_gettimex_fn gettimex_fn)
{
struct ptp_sys_offset_extended *extoff __free(kfree) = NULL;
struct ptp_system_timestamp sts;
+ int err;
if (!gettimex_fn)
return -EOPNOTSUPP;
@@ -363,23 +382,13 @@ static long ptp_sys_offset_extended(struct ptp_clock *ptp, void __user *arg,
if (extoff->n_samples > PTP_MAX_SAMPLES || extoff->rsv[0] || extoff->rsv[1])
return -EINVAL;
- switch (extoff->clockid) {
- case CLOCK_REALTIME:
- case CLOCK_MONOTONIC:
- case CLOCK_MONOTONIC_RAW:
- break;
- case CLOCK_AUX ... CLOCK_AUX_LAST:
- if (IS_ENABLED(CONFIG_POSIX_AUX_CLOCKS))
- break;
- fallthrough;
- default:
- return -EINVAL;
- }
+ err = ptp_validate_sys_offset_clockid(extoff->clockid);
+ if (err)
+ return err;
sts.clockid = extoff->clockid;
for (unsigned int i = 0; i < extoff->n_samples; i++) {
struct timespec64 ts;
- int err;
err = gettimex_fn(ptp->info, &ts, &sts);
if (err)
@@ -404,6 +413,131 @@ static long ptp_sys_offset_extended(struct ptp_clock *ptp, void __user *arg,
return copy_to_user(arg, extoff, sizeof(*extoff)) ? -EFAULT : 0;
}
+static long ptp_sys_offset_extended_attrs(struct ptp_clock *ptp, void __user *arg)
+{
+ struct ptp_sys_offset_attrs *data __free(kfree) = NULL;
+ struct ptp_system_timestamp sts;
+ unsigned int n_samples;
+ int err;
+
+ data = memdup_user(arg, sizeof(*data));
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
+ if (data->request.valid ||
+ data->request.num_samples > PTP_MAX_SAMPLES ||
+ data->request.num_samples == 0)
+ return -EINVAL;
+
+ err = ptp_validate_sys_offset_clockid(data->request.clock_id);
+ if (err)
+ return err;
+
+ n_samples = data->request.num_samples;
+ sts.clockid = data->request.clock_id;
+ kfree(data);
+ data = kzalloc(struct_size(data, timestamps, n_samples), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->request.num_samples = n_samples;
+
+ for (unsigned int i = 0; i < n_samples; i++) {
+ struct ptp_clock_attrs att = {};
+ struct timespec64 ts;
+
+ if (ptp->info->gettimexattrs64)
+ err = ptp->info->gettimexattrs64(ptp->info, &ts,
+ &sts, &att);
+ else if (ptp->info->gettimex64)
+ err = ptp->info->gettimex64(ptp->info, &ts, &sts);
+ else
+ return -EOPNOTSUPP;
+
+ if (err)
+ return err;
+
+ /* Filter out disabled or unavailable clocks */
+ if (!sts.pre_sts.valid || !sts.post_sts.valid)
+ return -EINVAL;
+
+ data->timestamps[i].pre_systime.sys_time =
+ ktime_to_ns(sts.pre_sts.systime);
+ data->timestamps[i].pre_systime.sys_rawtime =
+ ktime_to_ns(sts.pre_sts.monoraw);
+ data->timestamps[i].pre_systime.sys_counter =
+ sts.pre_sts.cycles;
+ data->timestamps[i].pre_systime.sys_counter_id =
+ sts.pre_sts.cs_id;
+ data->timestamps[i].devtime.device_time.sec = ts.tv_sec;
+ data->timestamps[i].devtime.device_time.nsec = ts.tv_nsec;
+ data->timestamps[i].devtime.attrs = att;
+ data->timestamps[i].post_systime.sys_time =
+ ktime_to_ns(sts.post_sts.systime);
+ data->timestamps[i].post_systime.sys_rawtime =
+ ktime_to_ns(sts.post_sts.monoraw);
+ data->timestamps[i].post_systime.sys_counter =
+ sts.post_sts.cycles;
+ data->timestamps[i].post_systime.sys_counter_id =
+ sts.post_sts.cs_id;
+ }
+
+ return copy_to_user(arg, data,
+ struct_size(data, timestamps, n_samples)) ? -EFAULT : 0;
+}
+
+static long ptp_sys_offset_precise_attrs(struct ptp_clock *ptp, void __user *arg)
+{
+ struct ptp_sys_offset_attrs *data __free(kfree) = NULL;
+ struct system_device_crosststamp xtstamp;
+ struct ptp_clock_attrs att = {};
+ struct timespec64 ts;
+ int err;
+
+ data = memdup_user(arg, sizeof(*data));
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
+ if (data->request.valid ||
+ data->request.num_samples != 1)
+ return -EINVAL;
+
+ err = ptp_validate_sys_offset_clockid(data->request.clock_id);
+ if (err)
+ return err;
+
+ kfree(data);
+ data = kzalloc(struct_size(data, timestamps, 1), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ if (ptp->info->getcrosststampattrs)
+ err = ptp->info->getcrosststampattrs(ptp->info, &xtstamp, &att);
+ else if (ptp->info->getcrosststamp)
+ err = ptp->info->getcrosststamp(ptp->info, &xtstamp);
+ else
+ return -EOPNOTSUPP;
+
+ if (err)
+ return err;
+
+ ts = ktime_to_timespec64(xtstamp.device);
+ data->timestamps[0].systime.sys_time =
+ ktime_to_ns(xtstamp.sys_systime);
+ data->timestamps[0].systime.sys_rawtime =
+ ktime_to_ns(xtstamp.sys_monoraw);
+ data->timestamps[0].systime.sys_counter =
+ xtstamp.sys_counter.cycles;
+ data->timestamps[0].systime.sys_counter_id =
+ xtstamp.sys_counter.cs_id;
+ data->timestamps[0].devtime.device_time.sec = ts.tv_sec;
+ data->timestamps[0].devtime.device_time.nsec = ts.tv_nsec;
+ data->timestamps[0].devtime.attrs = att;
+
+ return copy_to_user(arg, data,
+ struct_size(data, timestamps, 1)) ? -EFAULT : 0;
+}
+
static long ptp_sys_offset(struct ptp_clock *ptp, void __user *arg)
{
struct ptp_sys_offset *sysoff __free(kfree) = NULL;
@@ -539,11 +673,17 @@ long ptp_ioctl(struct posix_clock_context *pccontext, unsigned int cmd,
return ptp_sys_offset_precise(ptp, argptr,
ptp->info->getcrosststamp);
+ case PTP_SYS_OFFSET_PRECISE_ATTRS:
+ return ptp_sys_offset_precise_attrs(ptp, argptr);
+
case PTP_SYS_OFFSET_EXTENDED:
case PTP_SYS_OFFSET_EXTENDED2:
return ptp_sys_offset_extended(ptp, argptr,
ptp->info->gettimex64);
+ case PTP_SYS_OFFSET_EXTENDED_ATTRS:
+ return ptp_sys_offset_extended_attrs(ptp, argptr);
+
case PTP_SYS_OFFSET:
case PTP_SYS_OFFSET2:
return ptp_sys_offset(ptp, argptr);
diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c
index d6f54ccaf93b..849aef8191c5 100644
--- a/drivers/ptp/ptp_clock.c
+++ b/drivers/ptp/ptp_clock.c
@@ -112,7 +112,9 @@ static int ptp_clock_gettime(struct posix_clock *pc, struct timespec64 *tp)
struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
int err;
- if (ptp->info->gettimex64)
+ if (ptp->info->gettimexattrs64)
+ err = ptp->info->gettimexattrs64(ptp->info, tp, NULL, NULL);
+ else if (ptp->info->gettimex64)
err = ptp->info->gettimex64(ptp->info, tp, NULL);
else
err = ptp->info->gettime64(ptp->info, tp);
diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h
index 36a27a910595..b2a418081687 100644
--- a/include/linux/ptp_clock_kernel.h
+++ b/include/linux/ptp_clock_kernel.h
@@ -123,11 +123,34 @@ struct ptp_system_timestamp {
* reading the lowest bits of the PHC timestamp and the second
* reading immediately follows that.
*
+ * @gettimexattrs64: Reads the current time from the hardware clock and
+ * optionally also the system clock with additional clock
+ * attributes.
+ * parameter ts: Holds the PHC timestamp.
+ * parameter sts: If not NULL, it holds a pair of
+ * timestamps from the system clock. The first reading is
+ * made right before reading the lowest bits of the PHC
+ * timestamp and the second reading immediately follows that.
+ * parameter att: If not NULL, it holds the maximum error
+ * bound for the returned PHC timestamp in nanoseconds,
+ * the timescale for the returned PHC timestamp and the
+ * clock's qualitative synchronization status.
+ *
* @getcrosststamp: Reads the current time from the hardware clock and
* system clock simultaneously.
* parameter cts: Contains timestamp (device,system) pair,
* where system time is realtime and monotonic.
*
+ * @getcrosststampattrs: Reads the current time from the hardware clock and
+ * system clock simultaneously with additional data on
+ * hardware clock accuracy and reliability.
+ * parameter cts: Contains timestamp (device,system)
+ * pair, where system time is realtime and monotonic.
+ * parameter att: If not NULL, it holds the maximum error
+ * bound for the returned PHC timestamp in nanoseconds,
+ * the timescale for the returned PHC timestamp and the
+ * clock's qualitative synchronization status.
+ *
* @settime64: Set the current time on the hardware clock.
* parameter ts: Time value to set.
*
@@ -209,8 +232,15 @@ struct ptp_clock_info {
int (*gettime64)(struct ptp_clock_info *ptp, struct timespec64 *ts);
int (*gettimex64)(struct ptp_clock_info *ptp, struct timespec64 *ts,
struct ptp_system_timestamp *sts);
+ int (*gettimexattrs64)(struct ptp_clock_info *ptp,
+ struct timespec64 *ts,
+ struct ptp_system_timestamp *sts,
+ struct ptp_clock_attrs *att);
int (*getcrosststamp)(struct ptp_clock_info *ptp,
struct system_device_crosststamp *cts);
+ int (*getcrosststampattrs)(struct ptp_clock_info *ptp,
+ struct system_device_crosststamp *cts,
+ struct ptp_clock_attrs *att);
int (*settime64)(struct ptp_clock_info *p, const struct timespec64 *ts);
int (*getcycles64)(struct ptp_clock_info *ptp, struct timespec64 *ts);
int (*getcyclesx64)(struct ptp_clock_info *ptp, struct timespec64 *ts,
diff --git a/include/uapi/linux/ptp_clock.h b/include/uapi/linux/ptp_clock.h
index 46d45f902486..88c2da6bc8c6 100644
--- a/include/uapi/linux/ptp_clock.h
+++ b/include/uapi/linux/ptp_clock.h
@@ -79,6 +79,137 @@
*/
#define PTP_PEROUT_V1_VALID_FLAGS (0)
+/*
+ * Clock status values for struct ptp_clock_attrs.status
+ */
+enum ptp_clock_status {
+ /* Clock synchronization status cannot be reliably determined */
+ PTP_CLOCK_STATUS_UNKNOWN = 0,
+
+ /* Clock is acquiring synchronization */
+ PTP_CLOCK_STATUS_INITIALIZING = 1,
+
+ /* Clock is synchronized and maintained accurately by the device */
+ PTP_CLOCK_STATUS_SYNCED = 2,
+
+ /* Clock is drifting but remains within acceptable error bounds */
+ PTP_CLOCK_STATUS_HOLDOVER = 3,
+
+ /* Clock is drifting without adjustments or synchronization */
+ PTP_CLOCK_STATUS_FREE_RUNNING = 4,
+
+ /* Clock is unreliable, the error_bound value cannot be trusted */
+ PTP_CLOCK_STATUS_UNRELIABLE = 5
+};
+
+/*
+ * Clock timescale values for struct ptp_clock_attrs.timescale.
+ *
+ * These definitions describe the mathematical properties and reference
+ * epochs of the timescale provided by the PHC.
+ *
+ * Discipline: Describes the frequency/phase steering behavior.
+ * Continuity: Describes whether the timeline is uninterrupted.
+ */
+enum ptp_clock_timescale {
+ /* Unknown or unspecified timescale */
+ PTP_TIMESCALE_UNKNOWN = 0,
+
+ /********************* Absolute Atomic Timescales *********************
+ * These timescales are continuous, monotonic standards based on atomic
+ * physics. They do not experience phase jumps.
+ **********************************************************************/
+
+ /**
+ * International Atomic Time (TAI)
+ * Epoch: 1958-01-01 00:00:00.
+ * Continuity: Strictly monotonic and continuous; no leap seconds.
+ * Discipline: Primary atomic reference; no phase jumps.
+ */
+ PTP_TIMESCALE_TAI = 1,
+
+ /**
+ * Terrestrial Time (TT)
+ * Epoch: 1958-01-01 00:00:00.
+ * Continuity: Strictly monotonic and continuous; no leap seconds.
+ * Discipline: Defined as TAI + 32.184s constant offset.
+ */
+ PTP_TIMESCALE_TT = 2,
+
+ /**
+ * Global Positioning System (GPS) Time
+ * Epoch: 1980-01-06 00:00:00.
+ * Continuity: Strictly monotonic and continuous; no leap seconds.
+ * Discipline: Defined by the GPS constellation; fixed offset from TAI.
+ */
+ PTP_TIMESCALE_GPS = 3,
+
+ /****************** UTC-Based Timescales (Civil Time) *****************
+ * These timescales are derived from TAI but adjusted to align with
+ * the Earth's rotation, primarily through leap seconds.
+ **********************************************************************/
+
+ /**
+ * Coordinated Universal Time (UTC) - Wall-clock (CLOCK_REALTIME)
+ * Epoch: 1970-01-01 00:00:00 (Unix epoch).
+ * Continuity: Discontinuous; subject to 1-second leap second
+ * phase jumps.
+ * Discipline: Frequency steered; incorporates leap second corrections.
+ *
+ * Note: Leap-smeared UTC MUST NOT be advertised as PTP_TIMESCALE_UTC.
+ * Smear algorithms are not standardized and the resulting timescale
+ * is ambiguous. Implementations using smeared UTC MUST advertise
+ * PTP_TIMESCALE_UNKNOWN or PTP_TIMESCALE_PROPRIETARY instead.
+ */
+ PTP_TIMESCALE_UTC = 4,
+
+ /**
+ * POSIX Time (Unix Time)
+ * Epoch: 1970-01-01 00:00:00.
+ * Continuity: Discontinuous; leap seconds handled by
+ * repeating/skipping values.
+ * Discipline: Follows UTC frequency steering and phase jumps.
+ */
+ PTP_TIMESCALE_POSIX = 5,
+
+ /****************** System-Relative Monotonic Clocks ******************
+ * These timescales are relative to a system event (like boot)
+ * and are not synchronized to an external atomic standard.
+ **********************************************************************/
+
+ /**
+ * Monotonic System Clock (CLOCK_MONOTONIC)
+ * Epoch: Arbitrary (System boot time).
+ * Continuity: Strictly monotonic; no leap seconds.
+ * Discipline: Frequency steered to match system reference;
+ * does not advance during suspend.
+ */
+ PTP_TIMESCALE_MONOTONIC = 6,
+
+ /**
+ * Raw Monotonic System Clock (CLOCK_MONOTONIC_RAW)
+ * Epoch: Arbitrary (System boot time).
+ * Continuity: Strictly monotonic; no leap seconds.
+ * Discipline: Raw hardware oscillator; no frequency steering
+ * or discipline.
+ */
+ PTP_TIMESCALE_MONOTONIC_RAW = 7,
+
+ /**
+ * Boot Time System Clock (CLOCK_BOOTTIME)
+ * Epoch: Arbitrary (System boot time).
+ * Continuity: Strictly monotonic and continuous; no leap seconds.
+ * Discipline: Frequency steered to match system reference;
+ * advances during suspend.
+ */
+ PTP_TIMESCALE_BOOTTIME = 8,
+
+ /********************** Vendor-Specific Timescale *********************/
+
+ /* A proprietary or vendor-specific timescale with custom rules. */
+ PTP_TIMESCALE_PROPRIETARY = 9,
+};
+
/*
* struct ptp_clock_time - represents a time value
*
@@ -94,6 +225,119 @@ struct ptp_clock_time {
__u32 reserved;
};
+/*
+ * Hardware counter identifiers for struct ptp_sys_time.sys_counter_id
+ */
+enum ptp_counter_id {
+ /* Counter value not available or type not specified */
+ PTP_COUNTER_UNKNOWN = 0,
+
+ /* x86 Time Stamp Counter (TSC) */
+ PTP_COUNTER_X86_TSC = 1,
+
+ /* ARM Generic Timer virtual counter */
+ PTP_COUNTER_ARM_ARCH = 2,
+};
+
+/* Valid flags for struct ptp_clock_attrs.valid */
+#define PTP_ATTRS_VALID_ERROR_BOUND (1 << 0)
+#define PTP_ATTRS_VALID_TIMESCALE (1 << 1)
+#define PTP_ATTRS_VALID_STATUS (1 << 2)
+
+/**
+ * struct ptp_clock_attrs - quality attributes for a PHC timestamp
+ *
+ * @valid: Bitmask of PTP_ATTRS_VALID_* indicating which fields
+ * are populated. Zero means no attributes available.
+ * @error_bound: Maximum error in nanoseconds. Valid only when
+ * PTP_ATTRS_VALID_ERROR_BOUND is set.
+ * @timescale: Clock timescale (enum ptp_clock_timescale). Valid only
+ * when PTP_ATTRS_VALID_TIMESCALE is set.
+ * @status: Synchronization status (enum ptp_clock_status). Valid
+ * only when PTP_ATTRS_VALID_STATUS is set.
+ * @rsv: Reserved for future use, must be zero.
+ */
+struct ptp_clock_attrs {
+ __u32 valid;
+ __u32 error_bound;
+ __u32 timescale;
+ __u32 status;
+ __u32 rsv[4];
+};
+
+/**
+ * struct ptp_sys_time - system time snapshot with counter value
+ *
+ * @sys_time: System time in nanoseconds (clock selected by request).
+ * @sys_rawtime: CLOCK_MONOTONIC_RAW time in nanoseconds.
+ * @sys_counter: Raw clocksource counter value (0 = unavailable).
+ * @sys_counter_id: Identifies the counter (enum ptp_counter_id).
+ * @rsv: Reserved for future use, must be zero.
+ */
+struct ptp_sys_time {
+ __s64 sys_time;
+ __s64 sys_rawtime;
+ __u64 sys_counter;
+ __u32 sys_counter_id;
+ __u32 rsv;
+};
+
+/**
+ * struct ptp_dev_time - device timestamp with quality attributes
+ *
+ * @device_time: PHC timestamp value.
+ * @attrs: Quality attributes for this timestamp.
+ */
+struct ptp_dev_time {
+ struct ptp_clock_time device_time;
+ struct ptp_clock_attrs attrs;
+};
+
+/**
+ * struct ptp_timestamp - a complete timestamp sample
+ *
+ * For PTP_SYS_OFFSET_EXTENDED_ATTRS: pre_systime and post_systime bracket
+ * the device read (ABA sandwich).
+ * For PTP_SYS_OFFSET_PRECISE_ATTRS: only systime (union with pre_systime)
+ * is meaningful; post_systime is zeroed.
+ */
+struct ptp_timestamp {
+ union {
+ struct ptp_sys_time systime;
+ struct ptp_sys_time pre_systime;
+ };
+ struct ptp_dev_time devtime;
+ struct ptp_sys_time post_systime;
+};
+
+/**
+ * struct ptp_attrs_request - request parameters for attrs ioctls
+ *
+ * @valid: Bitmask for future request extensions. Must be zero for now.
+ * @clock_id: Clock base for system timestamps (CLOCK_REALTIME, etc).
+ * @num_samples: Number of timestamp samples requested.
+ * For PTP_SYS_OFFSET_PRECISE_ATTRS must be 1.
+ * @rsv: Reserved for future use, must be zero.
+ */
+struct ptp_attrs_request {
+ __u32 valid;
+ __kernel_clockid_t clock_id;
+ __u32 num_samples;
+ __u32 rsv[3];
+};
+
+/**
+ * struct ptp_sys_offset_attrs - unified data structure for attrs ioctls
+ *
+ * Used by both PTP_SYS_OFFSET_EXTENDED_ATTRS and
+ * PTP_SYS_OFFSET_PRECISE_ATTRS. Userspace allocates space for
+ * request.num_samples entries in the timestamps array.
+ */
+struct ptp_sys_offset_attrs {
+ struct ptp_attrs_request request;
+ struct ptp_timestamp timestamps[];
+};
+
struct ptp_clock_caps {
int max_adj; /* Maximum frequency adjustment in parts per billon. */
int n_alarm; /* Number of programmable alarms. */
@@ -106,7 +350,11 @@ struct ptp_clock_caps {
/* Whether the clock supports adjust phase */
int adjust_phase;
int max_phase_adj; /* Maximum phase adjustment in nanoseconds. */
- int rsv[11]; /* Reserved for future use. */
+ /* Whether the clock supports extended timestamps with attributes */
+ int extended_attrs;
+ /* Whether the clock supports precise cross-timestamps with attributes */
+ int precise_attrs;
+ int rsv[9]; /* Reserved for future use. */
};
struct ptp_extts_request {
@@ -252,6 +500,10 @@ struct ptp_pin_desc {
_IOWR(PTP_CLK_MAGIC, 21, struct ptp_sys_offset_precise)
#define PTP_SYS_OFFSET_EXTENDED_CYCLES \
_IOWR(PTP_CLK_MAGIC, 22, struct ptp_sys_offset_extended)
+#define PTP_SYS_OFFSET_PRECISE_ATTRS \
+ _IOWR(PTP_CLK_MAGIC, 23, struct ptp_sys_offset_attrs)
+#define PTP_SYS_OFFSET_EXTENDED_ATTRS \
+ _IOWR(PTP_CLK_MAGIC, 24, struct ptp_sys_offset_attrs)
struct ptp_extts_event {
struct ptp_clock_time t; /* Time event occurred. */
--
2.47.3
^ permalink raw reply related
* [PATCH v4 net-next 0/7] ptp: Add PHC timestamp quality attributes
From: Arthur Kiyanovski @ 2026-07-14 2:03 UTC (permalink / raw)
To: David Miller, Jakub Kicinski, netdev
Cc: Arthur Kiyanovski, Richard Cochran, Eric Dumazet, Paolo Abeni,
David Woodhouse, Thomas Gleixner, Miroslav Lichvar, Andrew Lunn,
Wen Gu, Xuan Zhuo, David Woodhouse, Yonatan Sarna,
Zorik Machulsky, Alexander Matushevsky, Saeed Bshara, Matt Wilson,
Anthony Liguori, Nafea Bshara, Evgeny Schmeilin, Netanel Belgazal,
Ali Saidi, Benjamin Herrenschmidt, Noam Dagan, David Arinzon,
Evgeny Ostrovsky, Ofir Tabachnik, Amit Bernstein, linux-kselftest,
linux-doc, shuah, Jonathan Corbet, Shuah Khan, Simon Horman,
vadim.fedorenko
This series adds quality attributes to PTP Hardware Clock (PHC)
timestamps, allowing userspace to obtain error bound, clock status,
timescale, and system counter values alongside timestamps in a single
call.
Motivation
----------
The existing PTP APIs return timestamps without any indication of
their quality. Applications that need clock accuracy and
synchronization status commonly rely on external tools such as
ptp4l, which implement synchronization logic and can export their
measurement of clock accuracy. For managed PHC devices — such as
the ENA network adapter, whose clock is synchronized by the device
without userspace involvement — these tools are not available, and
the existing APIs lack a way to report quality metrics to consumers
of time.
This was previously proposed as an RFC [1] with a single ioctl.
Based on community feedback, the design was reworked to cover both
the extended (multi-sample) and precise (cross-timestamp) paths.
Design
------
The UAPI was redesigned based on Thomas Gleixner's proposal [2]:
- A unified data structure (struct ptp_sys_offset_attrs) is used
for both extended and precise ioctls.
- A u32 valid bitmask in struct ptp_clock_attrs indicates which
attributes are populated, replacing sentinel values. Drivers
set only the bits for attributes they provide.
- System counter values (cycles + counter_id) are carried in
struct ptp_sys_time alongside each system timestamp. These are
populated by the timekeeping core cross-timestamp infrastructure,
which is now merged in net-next [3] — drivers do not fill them.
This series therefore applies directly to net-next with no
out-of-tree dependency.
- Graceful degradation: the attrs ioctls work even on devices
without attrs callbacks, falling back to gettimex64 /
getcrosststamp and returning attrs.valid = 0.
A capability flag is added to ptp_clock_caps so userspace can
discover attributes support.
Patches 2-3 add testptp support for the new ioctls.
Patch 4 implements the attributes for ptp_vmclock, reporting
error bound, clock status, and timescale.
Patches 5-7 implement the attributes for the ENA driver,
reporting error bound from the device's PHC layer.
v4:
- Complete UAPI redesign per Thomas Gleixner's proposal [2]:
unified data structure with u32 valid bitmask, system counter
in ptp_sys_time (populated by core, not drivers), graceful
degradation for devices without attrs callbacks. (Thomas Gleixner,
David Woodhouse)
- Counter values moved from driver attrs callback to timekeeping
core infrastructure — drivers no longer set counter_id or
counter_value.
- Flexible array member for timestamps[] (kernel bounds the copy,
userspace allocates for num_samples requested).
- Drop separate ptp_clock_attributes kernel struct — driver
callbacks fill the UAPI ptp_clock_attrs directly.
v3:
- Remove patch 5/8 from v2 (return-code bugfix) — sent separately
as [PATCH net] to the net tree.
- Zero-initialize struct ptp_clock_attributes in PTP core ioctl
handlers to prevent stack leak of unset fields. (Simon Horman,
sashiko)
- ptp_vmclock: validate counter_period_shift < 128 to prevent
undefined behavior on untrusted hypervisor input. (sashiko)
- ptp_vmclock: add overflow check on err_hi * NSEC_PER_SEC to
prevent silent wraparound producing erroneously small error
bound. (sashiko)
- ptp_vmclock: report PTP_TIMESCALE_TAI after tai_adjust() to
avoid timescale mismatch. (sashiko)
- ENA: set counter_id = 0, counter_value = 0 in gettimexattrs64
for defense-in-depth. (sashiko)
v2:
- Fix build bisectability: move ena_com.c consumer updates into
patch 6/8 and ena_phc.c caller update into patch 7/8 so each
patch compiles independently.
- Add missing Cc for Amit Bernstein (co-author of ENA patches).
[1] https://lore.kernel.org/netdev/20250724115657.150-1-darinzon@amazon.com/
[2] https://lore.kernel.org/all/87se7ht25o.ffs@tglx/
[3] https://lore.kernel.org/all/20260526165826.392227559@kernel.org/
Arthur Kiyanovski (7):
ptp: Add ioctls for PHC timestamps with quality attributes
selftests/ptp: Extract print_system_timestamp helper in testptp
selftests/ptp: Add testptp support for attributes ioctls
ptp: ptp_vmclock: Implement attributes ioctls
net: ena: Update PHC admin interface for error bound support
net: ena: Add error bound to PHC communication layer
net: ena: Implement gettimexattrs64 callback for PTP attributes
.../device_drivers/ethernet/amazon/ena.rst | 2 +
.../net/ethernet/amazon/ena/ena_admin_defs.h | 17 +-
drivers/net/ethernet/amazon/ena/ena_com.c | 51 ++--
drivers/net/ethernet/amazon/ena/ena_com.h | 5 +-
drivers/net/ethernet/amazon/ena/ena_debugfs.c | 3 +
drivers/net/ethernet/amazon/ena/ena_phc.c | 61 ++++-
drivers/ptp/ptp_chardev.c | 166 +++++++++++-
drivers/ptp/ptp_clock.c | 4 +-
drivers/ptp/ptp_vmclock.c | 197 ++++++++++++--
include/linux/ptp_clock_kernel.h | 30 +++
include/uapi/linux/ptp_clock.h | 254 +++++++++++++++++-
tools/testing/selftests/ptp/testptp.c | 181 ++++++++++---
12 files changed, 862 insertions(+), 109 deletions(-)
--
2.47.3
^ permalink raw reply
* [PATCH net] octeontx2: Fix Klocwork issues in AF and PF drivers
From: Ratheesh Kannoth @ 2026-07-14 2:02 UTC (permalink / raw)
To: davem, linux-kernel, naveenm, netdev, sgoutham
Cc: andrew+netdev, edumazet, kuba, pabeni, richardcochran,
Suman Ghosh, Ratheesh Kannoth
From: Suman Ghosh <sumang@marvell.com>
Fix null dereference, uninitialized variable, and error-path resource
leak findings reported by Klocwork across the OcteonTX2 AF and PF code.
Fixes: 818ed8933bd1 ("octeontx2-af: Re-enable MAC TX in otx2_stop processing")
Cc: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Suman Ghosh <sumang@marvell.com>
Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/af/cgx.c | 12 +++++++++---
.../net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c | 8 +++++---
drivers/net/ethernet/marvell/octeontx2/af/npc.h | 6 +++---
drivers/net/ethernet/marvell/octeontx2/af/ptp.c | 11 ++++++++++-
drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c | 2 +-
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c | 2 +-
.../net/ethernet/marvell/octeontx2/af/rvu_debugfs.c | 8 +++++++-
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 2 +-
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c | 2 +-
.../net/ethernet/marvell/octeontx2/nic/otx2_flows.c | 1 +
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c | 3 +++
drivers/net/ethernet/marvell/octeontx2/nic/qos.c | 1 +
12 files changed, 43 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
index 2e94d5105016..70c8ef5f0be0 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
@@ -491,12 +491,19 @@ int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id)
u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id)
{
struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
- struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
struct mac_ops *mac_ops;
+ struct lmac *lmac;
int index;
u64 cfg;
int id;
+ if (!cgx_dev)
+ return 0;
+
+ lmac = lmac_pdata(lmac_id, cgx_dev);
+ if (!lmac)
+ return 0;
+
mac_ops = cgx_dev->mac_ops;
id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
@@ -1709,10 +1716,10 @@ unsigned long cgx_get_lmac_bmap(void *cgxd)
static int cgx_lmac_init(struct cgx *cgx)
{
u8 max_dmac_filters;
+ u64 lmac_list = 0;
struct lmac *lmac;
int err, filter;
unsigned int i;
- u64 lmac_list;
/* lmac_list specifies which lmacs are enabled
* when bit n is set to 1, LMAC[n] is enabled
@@ -2021,7 +2028,6 @@ static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)
list_add(&cgx->cgx_list, &cgx_list);
-
cgx_populate_features(cgx);
mutex_init(&cgx->lock);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c b/drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
index d98b49f47970..cc19d16e660f 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
@@ -632,8 +632,8 @@ int rvu_mbox_handler_mcs_free_resources(struct rvu *rvu,
{
u16 pcifunc = req->hdr.pcifunc;
struct mcs_rsrc_map *map;
+ int rc = -EINVAL;
struct mcs *mcs;
- int rc = 0;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
@@ -682,8 +682,8 @@ int rvu_mbox_handler_mcs_alloc_resources(struct rvu *rvu,
{
u16 pcifunc = req->hdr.pcifunc;
struct mcs_rsrc_map *map;
+ int rsrc_id = -EINVAL, i;
struct mcs *mcs;
- int rsrc_id, i;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
@@ -744,6 +744,8 @@ int rvu_mbox_handler_mcs_alloc_resources(struct rvu *rvu,
rsp->rsrc_cnt++;
}
break;
+ default:
+ goto exit;
}
rsp->rsrc_type = req->rsrc_type;
@@ -856,7 +858,7 @@ int rvu_mbox_handler_mcs_ctrl_pkt_rule_write(struct rvu *rvu,
static void rvu_mcs_set_lmac_bmap(struct rvu *rvu)
{
struct mcs *mcs = mcs_get_pdata(0);
- unsigned long lmac_bmap;
+ unsigned long lmac_bmap = 0;
int cgx, lmac, port;
for (port = 0; port < mcs->hw->lmac_cnt; port++) {
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc.h b/drivers/net/ethernet/marvell/octeontx2/af/npc.h
index eaed172f1606..402cd56b835e 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/npc.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/npc.h
@@ -522,7 +522,7 @@ struct npc_coalesced_kpu_prfl {
u8 name[NPC_NAME_LEN]; /* KPU Profile name */
u64 version; /* KPU firmware/profile version */
u8 num_prfl; /* No of NPC profiles. */
- u16 prfl_sz[];
+ u16 prfl_sz[0];
};
struct npc_mcam_kex {
@@ -549,7 +549,7 @@ struct npc_kpu_fwdata {
* struct npc_kpu_profile_cam[entries];
* struct npc_kpu_profile_action[entries];
*/
- u8 data[];
+ u8 data[0];
} __packed;
struct npc_lt_def {
@@ -639,7 +639,7 @@ struct npc_kpu_profile_fwdata {
* Custom KPU CAM and ACTION configuration entries.
* struct npc_kpu_fwdata kpu[kpus];
*/
- u8 data[];
+ u8 data[0];
} __packed;
struct rvu_npc_mcam_rule {
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c
index 58e62e955554..6ccaa9de998c 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c
@@ -517,6 +517,7 @@ static int ptp_pps_on(struct ptp *ptp, int on, u64 period)
static int ptp_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
+ void __iomem * const *base;
struct ptp *ptp;
int err;
@@ -536,7 +537,15 @@ static int ptp_probe(struct pci_dev *pdev,
if (err)
goto error_free;
- ptp->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO];
+ base = pcim_iomap_table(pdev);
+ if (!base)
+ goto error_free;
+
+ ptp->reg_base = base[PCI_PTP_BAR_NO];
+ if (!ptp->reg_base) {
+ err = -ENODEV;
+ goto error_free;
+ }
pci_set_drvdata(pdev, ptp);
if (!first_ptp_block)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
index 4ff3935ed3fe..3b1f1dbfc27e 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
@@ -507,7 +507,7 @@ int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable)
void *cgxd;
if (!is_cgx_config_permitted(rvu, pcifunc))
- return LMAC_AF_ERR_PERM_DENIED;
+ return 0;
rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
cgxd = rvu_cgx_pdata(cgx_id, rvu);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
index f404117bf6c8..fbe41537ea9a 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
@@ -83,8 +83,8 @@ static irqreturn_t cpt_af_flt_intr_handler(int vec, void *ptr)
struct rvu_block *block = ptr;
struct rvu *rvu = block->rvu;
int blkaddr = block->addr;
+ int i, eng = 0;
u64 reg, val;
- int i, eng;
u8 grp;
reg = rvu_read64(rvu, blkaddr, CPT_AF_FLTX_INT(vec));
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
index 3456313d3b3c..230794abbb4f 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
@@ -496,13 +496,17 @@ RVU_DEBUG_SEQ_FOPS(mcs_rx_secy_stats, mcs_rx_secy_stats_display, NULL);
static void rvu_dbg_mcs_init(struct rvu *rvu)
{
+ char *dname = NULL;
struct mcs *mcs;
- char dname[10];
int i;
if (!rvu->mcs_blk_cnt)
return;
+ dname = kmalloc_array(rvu->mcs_blk_cnt, sizeof(char), GFP_KERNEL);
+ if (!dname)
+ return;
+
rvu->rvu_dbg.mcs_root = debugfs_create_dir("mcs", rvu->rvu_dbg.root);
for (i = 0; i < rvu->mcs_blk_cnt; i++) {
@@ -546,6 +550,8 @@ static void rvu_dbg_mcs_init(struct rvu *rvu)
debugfs_create_file("port", 0600, rvu->rvu_dbg.mcs_tx, mcs,
&rvu_dbg_mcs_tx_port_stats_fops);
}
+
+ kfree(dname);
}
#define LMT_MAPTBL_ENTRY_SIZE 16
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 6a0ce2665031..c1333c4d45ec 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -5540,7 +5540,7 @@ static void nix_inline_ipsec_cfg(struct rvu *rvu, struct nix_inline_ipsec_cfg *r
int blkaddr)
{
u8 cpt_idx, cpt_blkaddr;
- u64 val;
+ u64 val = 0;
cpt_idx = (blkaddr == BLKADDR_NIX0) ? 0 : 1;
if (req->enable) {
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
index c7bc0b3a29b9..6b3ad91bb903 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
@@ -2210,8 +2210,8 @@ static int npc_load_kpu_profile_from_fw(struct rvu *rvu)
rvu->kpu_prfl_addr = NULL;
} else {
kfree(rvu->kpu_fwdata);
+ rvu->kpu_fwdata = NULL;
}
- rvu->kpu_fwdata = NULL;
rvu->kpu_fwdata_sz = 0;
}
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
index 5dd0591fed99..99d78fc5a2c4 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
@@ -272,6 +272,7 @@ int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count)
if (allocated) {
pfvf->flags |= OTX2_FLAG_MCAM_ENTRIES_ALLOC;
pfvf->flags |= OTX2_FLAG_NTUPLE_SUPPORT;
+ pfvf->flags |= OTX2_FLAG_TC_FLOWER_SUPPORT;
}
if (allocated != count)
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
index 2e33b33ec993..33577a90fc1e 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
@@ -489,6 +489,9 @@ static void otx2_pfvf_mbox_handler(struct work_struct *work)
return;
inval_msg:
+ if (!msg)
+ return;
+
otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id);
otx2_mbox_msg_send(mbox, vf_idx);
}
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/qos.c b/drivers/net/ethernet/marvell/octeontx2/nic/qos.c
index 69c0911e28e9..02e593017556 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/qos.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/qos.c
@@ -533,6 +533,7 @@ otx2_qos_sw_create_leaf_node(struct otx2_nic *pfvf,
err = otx2_qos_add_child_node(parent, node);
if (err) {
mutex_unlock(&pfvf->qos.qos_lock);
+ kfree(node);
return ERR_PTR(err);
}
mutex_unlock(&pfvf->qos.qos_lock);
--
2.43.0
^ permalink raw reply related
* [PATCH v3 net-next 3/9] octeontx2-pf: switch: Add pf files hierarchy
From: Ratheesh Kannoth @ 2026-07-14 1:53 UTC (permalink / raw)
To: linux-kernel, netdev
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, sgoutham,
Ratheesh Kannoth
In-Reply-To: <20260714015331.1801922-1-rkannoth@marvell.com>
Adds CONFIG_OCTEONTX_SWITCH, links stub switch objects into the PF
module, and introduces empty sw_* init/deinit and notifier hooks for
later patches.
Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
---
.../net/ethernet/marvell/octeontx2/Kconfig | 10 ++++++++++
.../ethernet/marvell/octeontx2/nic/Makefile | 5 ++++-
.../marvell/octeontx2/nic/switch/sw_fdb.c | 16 +++++++++++++++
.../marvell/octeontx2/nic/switch/sw_fdb.h | 13 ++++++++++++
.../marvell/octeontx2/nic/switch/sw_fib.c | 16 +++++++++++++++
.../marvell/octeontx2/nic/switch/sw_fib.h | 20 +++++++++++++++++++
.../marvell/octeontx2/nic/switch/sw_fl.c | 16 +++++++++++++++
.../marvell/octeontx2/nic/switch/sw_fl.h | 13 ++++++++++++
.../marvell/octeontx2/nic/switch/sw_nb.c | 17 ++++++++++++++++
.../marvell/octeontx2/nic/switch/sw_nb.h | 20 +++++++++++++++++++
10 files changed, 145 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h
diff --git a/drivers/net/ethernet/marvell/octeontx2/Kconfig b/drivers/net/ethernet/marvell/octeontx2/Kconfig
index 47e549c581f0..e2fb6dd71078 100644
--- a/drivers/net/ethernet/marvell/octeontx2/Kconfig
+++ b/drivers/net/ethernet/marvell/octeontx2/Kconfig
@@ -28,6 +28,16 @@ config NDC_DIS_DYNAMIC_CACHING
, NPA stack pages etc in NDC. Also locks down NIX SQ/CQ/RQ/RSS and
NPA Aura/Pool contexts.
+config OCTEONTX_SWITCH
+ bool "Marvell OcteonTX2 switch driver"
+ depends on (64BIT && COMPILE_TEST) || ARM64
+ depends on OCTEONTX2_PF
+ default n
+ help
+ This driver supports Marvell's OcteonTX2 switch.
+ Marvell SWITCH HW can offload L2, L3 flow. ARM core interacts
+ with Marvell SW HW thru mbox.
+
config OCTEONTX2_PF
tristate "Marvell OcteonTX2 NIC Physical Function driver"
select OCTEONTX2_MBOX
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile
index 883e9f4d601c..123b0af23abd 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile
@@ -9,7 +9,10 @@ obj-$(CONFIG_RVU_ESWITCH) += rvu_rep.o
rvu_nicpf-y := otx2_pf.o otx2_common.o otx2_txrx.o otx2_ethtool.o \
otx2_flows.o otx2_tc.o cn10k.o cn20k.o otx2_dmac_flt.o \
- otx2_devlink.o qos_sq.o qos.o otx2_xsk.o
+ otx2_devlink.o qos_sq.o qos.o otx2_xsk.o \
+ switch/sw_fdb.o switch/sw_fl.o
+rvu_nicpf-$(CONFIG_OCTEONTX_SWITCH) += switch/sw_nb.o switch/sw_fib.o
+
rvu_nicvf-y := otx2_vf.o
rvu_rep-y := rep.o
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c
new file mode 100644
index 000000000000..6842c8d91ffc
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell RVU switch driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+#include "sw_fdb.h"
+
+int sw_fdb_init(void)
+{
+ return 0;
+}
+
+void sw_fdb_deinit(void)
+{
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h
new file mode 100644
index 000000000000..d4314d6d3ee4
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Marvell switch driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+#ifndef SW_FDB_H_
+#define SW_FDB_H_
+
+void sw_fdb_deinit(void);
+int sw_fdb_init(void);
+
+#endif // SW_FDB_H
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c
new file mode 100644
index 000000000000..12ddf8119372
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell RVU switch driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+#include "sw_fib.h"
+
+int sw_fib_init(void)
+{
+ return 0;
+}
+
+void sw_fib_deinit(void)
+{
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h
new file mode 100644
index 000000000000..9b72e95f2dd3
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Marvell switch driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+#ifndef SW_FIB_H_
+#define SW_FIB_H_
+
+#include <linux/kconfig.h>
+
+#if IS_ENABLED(CONFIG_OCTEONTX_SWITCH)
+void sw_fib_deinit(void);
+int sw_fib_init(void);
+#else
+static inline void sw_fib_deinit(void) {}
+static inline int sw_fib_init(void) { return 0; }
+#endif
+
+#endif /* SW_FIB_H_ */
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c
new file mode 100644
index 000000000000..36a2359a0a48
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell RVU switch driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+#include "sw_fl.h"
+
+int sw_fl_init(void)
+{
+ return 0;
+}
+
+void sw_fl_deinit(void)
+{
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h
new file mode 100644
index 000000000000..cd018d770a8a
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Marvell switch driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+#ifndef SW_FL_H_
+#define SW_FL_H_
+
+void sw_fl_deinit(void);
+int sw_fl_init(void);
+
+#endif // SW_FL_H
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c
new file mode 100644
index 000000000000..2d14a0590c5d
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell RVU switch driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+#include "sw_nb.h"
+
+int sw_nb_unregister(void)
+{
+ return 0;
+}
+
+int sw_nb_register(void)
+{
+ return 0;
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h
new file mode 100644
index 000000000000..73cc1e99b8ec
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Marvell switch driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+#ifndef SW_NB_H_
+#define SW_NB_H_
+
+#include <linux/kconfig.h>
+
+#if IS_ENABLED(CONFIG_OCTEONTX_SWITCH)
+int sw_nb_register(void);
+int sw_nb_unregister(void);
+#else
+static inline int sw_nb_register(void) { return 0; }
+static inline int sw_nb_unregister(void) { return 0; }
+#endif
+
+#endif /* SW_NB_H_ */
--
2.43.0
^ permalink raw reply related
* [PATCH v3 net-next 0/9] Switch support
From: Ratheesh Kannoth @ 2026-07-14 1:53 UTC (permalink / raw)
To: linux-kernel, netdev
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, sgoutham,
Ratheesh Kannoth
Marvell OcteonTX2 switch hardware is capable of accelerating L2, L3, and
flow. When representors are enabled through devlink, a logical port is
created in switch hardware for each representor device.
This patch series implements communication from the host OS to the switch
hardware and vice versa.
control plane (FDB / FIB / flow over mailbox)
+---------------------------------------------------------------------+
| HOST OS |
| |
| +------------+ +---------------------+ +---------------+ |
| | bridge / | | PF + notifiers | | TC / flower | |
| | routing | | (FDB, FIB, flow) | | offload | |
| +------+-----+ +-----------+---------+ +-------+-------+ |
| ^ | | |
| | slow path | | |
| | (unmatched pkts) v v |
| +------+------+ +------+------+ +------+------+ |
| | rep-eth0 | | PF / VF | <----> | RVU AF | |
| +------+------+ +-------------+ +------+------+ |
| | | |
| +------+------+ | |
| | rep-eth1 | | |
| +-------------+ | |
| | slow path (miss / control to host stack) | |
+---------------------------------------------------------------------+
| | | |
| | mailbox / PCIe | |
| v v |
+---------------------------------------------------------------------+
| SWITCH HARDWARE |
| |
| +---------------------------------------------------+ |
| | L2 tables | L3 tables | flow TCAM (HW) | |
| +-------+-------------+---------------+-------------+ |
| | fast path (HW) | |
| v v |
| lport0 <========================> lport1 |
| HW forwarding between ports |
| |
| slow path (miss): packets raised to host via representors |
+---------------------------------------------------------------------+
When representors are created, corresponding logical ports are created in
switchdev. Matching traffic is accelerated in switch hardware using
installed L2, L3, and flow rules. Packets that do not match offloaded
state, or that require software handling, take the slow path through
representors and the host networking stack. Control updates from the host
(FDB, FIB, TC flower) are sent to the AF over mailbox and programmed into
switch hardware tables.
Notifier callbacks are registered to receive system events such as FDB
add/delete and FIB add/delete. Flow add/delete operations are handled
through the ingress flow-table offload path. These events are captured and
processed by the NIC driver and forwarded to the switch device through the
AF driver. All message exchanges use the mailbox interface.
Bridge acceleration:
FDB add/delete notifications are processed, and learned SMAC information is
sent to the switch hardware. The switch inserts a hardware rule to
accelerate packets destined to the MAC address. Switch-initiated FDB
refresh is propagated back to the host bridge through an AF to PF/VF
mailbox and switchdev notifier.
L3 acceleration:
IPv4 and IPv6 FIB updates observed through netdev and FIB notifiers are
queued on the PF and sent to the AF. The AF batches fib_entry structures
and forwards them to switchdev when firmware is ready.
Flow acceleration:
TC flower rules accepted by the ingress flow-table offload callback are
translated into fl_tuple state, ingress and egress pcifunc are resolved
through FIB lookup, and flow updates are sent to the switch hardware
through the mailbox interface. Per-cookie packet counters are kept in sync
using NPC MCAM multi-stats when the switch requests a flow refresh.
Ratheesh Kannoth (9):
octeontx2-af: switch: Add AF to switch mbox and skeleton files
Host to switch mailbox definitions for FDB, FIB, flow, and flow stats;
AF-side L2/L3/flow skeleton objects.
octeontx2-af: switch: Add switch dev to AF mboxes
Switch to AF and AF to switchdev mailbox messages; interface query
handler and NPC helpers for flow delete/stats/features.
octeontx2-pf: switch: Add pf files hierarchy
CONFIG_OCTEONTX_SWITCH and stub PF switch objects for FDB, FIB, flow, and
notifier plumbing.
octeontx2-af: switch: Representor for switch port
Copy devlink switch_id to the AF and map representor pcifunc to a switch
port id when eswitch mode is enabled.
octeontx2-af: PAN switch TL1 scheduling and NPC channel control
Allocate multiple TL1 scheduler queues in PAN mode and honor caller
supplied NPC channel masks for multi-link steering.
octeontx2-pf: register switch notifiers for eswitch offload
Register PF notifier blocks for FIB, neighbour, address, netdev, and
switchdev FDB events; split IPv4/IPv6 handling.
octeontx2: plumb bridge FDB updates through AF and switchdev
End-to-end L2 offload from switchdev FDB notifications to AF to
switchdev, including firmware gating and FDB refresh to host.
octeontx2: offload host FIB updates to switch via AF mailbox
Queue IPv4/IPv6 FIB updates from notifiers and batch fib_entry delivery
from AF to switchdev.
octeontx2: add TC flow offload path for switch flows
Ingress flow-table offload for TC flower rules, AF forwarding to
switchdev, and flow counter refresh from switch to host.
.../net/ethernet/marvell/octeontx2/Kconfig | 13 +
.../ethernet/marvell/octeontx2/af/Makefile | 3 +-
.../net/ethernet/marvell/octeontx2/af/mbox.h | 227 ++++++++
.../net/ethernet/marvell/octeontx2/af/rvu.c | 110 ++++
.../net/ethernet/marvell/octeontx2/af/rvu.h | 6 +
.../ethernet/marvell/octeontx2/af/rvu_nix.c | 53 +-
.../ethernet/marvell/octeontx2/af/rvu_npc.c | 76 +++
.../marvell/octeontx2/af/rvu_npc_fs.c | 11 +
.../ethernet/marvell/octeontx2/af/rvu_rep.c | 3 +-
.../marvell/octeontx2/af/switch/rvu_sw.c | 48 ++
.../marvell/octeontx2/af/switch/rvu_sw.h | 14 +
.../marvell/octeontx2/af/switch/rvu_sw_fl.c | 294 ++++++++++
.../marvell/octeontx2/af/switch/rvu_sw_fl.h | 12 +
.../marvell/octeontx2/af/switch/rvu_sw_l2.c | 283 +++++++++
.../marvell/octeontx2/af/switch/rvu_sw_l2.h | 13 +
.../marvell/octeontx2/af/switch/rvu_sw_l3.c | 215 +++++++
.../marvell/octeontx2/af/switch/rvu_sw_l3.h | 11 +
.../ethernet/marvell/octeontx2/nic/Makefile | 13 +-
.../marvell/octeontx2/nic/otx2_txrx.h | 2 +
.../ethernet/marvell/octeontx2/nic/otx2_vf.c | 17 +
.../net/ethernet/marvell/octeontx2/nic/rep.c | 11 +
.../marvell/octeontx2/nic/switch/sw_fdb.c | 144 +++++
.../marvell/octeontx2/nic/switch/sw_fdb.h | 14 +
.../marvell/octeontx2/nic/switch/sw_fib.c | 132 +++++
.../marvell/octeontx2/nic/switch/sw_fib.h | 16 +
.../marvell/octeontx2/nic/switch/sw_fl.c | 546 ++++++++++++++++++
.../marvell/octeontx2/nic/switch/sw_fl.h | 15 +
.../marvell/octeontx2/nic/switch/sw_nb.c | 422 ++++++++++++++
.../marvell/octeontx2/nic/switch/sw_nb.h | 35 ++
.../marvell/octeontx2/nic/switch/sw_nb_v4.c | 335 +++++++++++
.../marvell/octeontx2/nic/switch/sw_nb_v4.h | 21 +
.../marvell/octeontx2/nic/switch/sw_nb_v6.c | 236 ++++++++
.../marvell/octeontx2/nic/switch/sw_nb_v6.h | 21 +
33 files changed, 3361 insertions(+), 11 deletions(-)
---
v2 -> v3: Addressed Pabolo comments.
https://lore.kernel.org/netdev/20260702045026.2914748-1-rkannoth@marvell.com/
v1 -> v2: Addressed Jakub comments
https://lore.kernel.org/netdev/20260630024715.4124281-1-rkannoth@marvell.com/
--
2.43.0
^ permalink raw reply
* [PATCH v3 net-next 2/9] octeontx2-af: switch: Add switch dev to AF mboxes
From: Ratheesh Kannoth @ 2026-07-14 1:53 UTC (permalink / raw)
To: linux-kernel, netdev
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, sgoutham,
Ratheesh Kannoth
In-Reply-To: <20260714015331.1801922-1-rkannoth@marvell.com>
The Marvell switch hardware runs on a Linux OS. Switch
needs various information from AF driver. These mboxes are defined
to query those from AF driver.
Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
---
.../ethernet/marvell/octeontx2/af/Makefile | 2 +-
.../net/ethernet/marvell/octeontx2/af/mbox.h | 126 ++++++++++++++++
.../net/ethernet/marvell/octeontx2/af/rvu.c | 139 ++++++++++++++++++
.../net/ethernet/marvell/octeontx2/af/rvu.h | 1 +
.../ethernet/marvell/octeontx2/af/rvu_nix.c | 7 +-
.../ethernet/marvell/octeontx2/af/rvu_npc.c | 100 +++++++++++++
.../marvell/octeontx2/af/rvu_npc_fs.c | 11 ++
.../marvell/octeontx2/af/switch/rvu_sw.c | 15 ++
.../marvell/octeontx2/af/switch/rvu_sw.h | 11 ++
9 files changed, 409 insertions(+), 3 deletions(-)
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/Makefile b/drivers/net/ethernet/marvell/octeontx2/af/Makefile
index 82dd387308c9..73f20a44f1a0 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/Makefile
+++ b/drivers/net/ethernet/marvell/octeontx2/af/Makefile
@@ -12,6 +12,6 @@ rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \
rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \
rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o \
- switch/rvu_sw_l2.o switch/rvu_sw_l3.o switch/rvu_sw_fl.o\
+ switch/rvu_sw.o switch/rvu_sw_l2.o switch/rvu_sw_l3.o switch/rvu_sw_fl.o \
rvu_rep.o cn20k/mbox_init.o cn20k/nix.o cn20k/debugfs.o \
cn20k/npa.o cn20k/npc.o
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index 2867da47d9f5..23bc66ed854e 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -172,6 +172,10 @@ M(FL_NOTIFY, 0x012, fl_notify, \
fl_notify_req, msg_rsp) \
M(FL_GET_STATS, 0x013, fl_get_stats, \
fl_get_stats_req, fl_get_stats_rsp) \
+M(IFACE_GET_INFO, 0x014, iface_get_info, msg_req, \
+ iface_get_info_rsp) \
+M(SWDEV2AF_NOTIFY, 0x015, swdev2af_notify, \
+ swdev2af_notify_req, msg_rsp) \
/* CGX mbox IDs (range 0x200 - 0x3FF) */ \
M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
@@ -317,6 +321,14 @@ M(NPC_MCAM_GET_DFT_RL_IDXS, 0x601e, npc_get_dft_rl_idxs, \
M(NPC_MCAM_GET_NPC_PFL_INFO, 0x601f, npc_get_pfl_info, \
msg_req, \
npc_get_pfl_info_rsp) \
+M(NPC_MCAM_FLOW_DEL_N_FREE, 0x6020, npc_flow_del_n_free, \
+ npc_flow_del_n_free_req, msg_rsp) \
+M(NPC_MCAM_GET_MUL_STATS, 0x6021, npc_mcam_mul_stats, \
+ npc_mcam_get_mul_stats_req, \
+ npc_mcam_get_mul_stats_rsp) \
+M(NPC_MCAM_GET_FEATURES, 0x6022, npc_mcam_get_features, \
+ msg_req, \
+ npc_mcam_get_features_rsp) \
/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
nix_lf_alloc_req, nix_lf_alloc_rsp) \
@@ -446,6 +458,12 @@ M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
#define MBOX_UP_REP_MESSAGES \
M(REP_EVENT_UP_NOTIFY, 0xEF0, rep_event_up_notify, rep_event, msg_rsp) \
+#define MBOX_UP_AF2SWDEV_MESSAGES \
+M(AF2SWDEV, 0xEF1, af2swdev_notify, af2swdev_notify_req, msg_rsp)
+
+#define MBOX_UP_AF2PF_FDB_REFRESH_MESSAGES \
+M(AF2PF_FDB_REFRESH, 0xEF2, af2pf_fdb_refresh, af2pf_fdb_refresh_req, msg_rsp)
+
enum {
#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
MBOX_MESSAGES
@@ -453,6 +471,8 @@ MBOX_UP_CGX_MESSAGES
MBOX_UP_CPT_MESSAGES
MBOX_UP_MCS_MESSAGES
MBOX_UP_REP_MESSAGES
+MBOX_UP_AF2SWDEV_MESSAGES
+MBOX_UP_AF2PF_FDB_REFRESH_MESSAGES
#undef M
};
@@ -1589,6 +1609,30 @@ struct npc_mcam_alloc_entry_rsp {
u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
};
+struct npc_flow_del_n_free_req {
+ struct mbox_msghdr hdr;
+ u16 cnt;
+ u16 entry[256]; /* Entry index to be freed */
+};
+
+struct npc_mcam_get_features_rsp {
+ struct mbox_msghdr hdr;
+ u64 rx_features;
+ u64 tx_features;
+};
+
+struct npc_mcam_get_mul_stats_req {
+ struct mbox_msghdr hdr;
+ u16 cnt;
+ u16 entry[256]; /* mcam entry */
+};
+
+struct npc_mcam_get_mul_stats_rsp {
+ struct mbox_msghdr hdr;
+ u16 cnt;
+ u64 stat[256]; /* counter stats */
+};
+
struct npc_mcam_free_entry_req {
struct mbox_msghdr hdr;
u16 entry; /* Entry index to be freed */
@@ -1914,6 +1958,88 @@ struct fl_get_stats_rsp {
u64 pkts_diff;
};
+struct af2swdev_notify_req {
+ struct mbox_msghdr hdr;
+ u64 flags;
+ u32 port_id;
+ u32 switch_id;
+ union {
+ struct {
+ u8 mac[6];
+ };
+ struct {
+ u8 cnt;
+ struct fib_entry entry[16];
+ };
+
+ struct {
+ u64 cookie;
+ u64 features;
+ struct fl_tuple tuple;
+ };
+ };
+};
+
+struct af2pf_fdb_refresh_req {
+ struct mbox_msghdr hdr;
+ u16 pcifunc;
+ u8 mac[6];
+};
+
+struct iface_info {
+ u8 is_vf : 1;
+ u8 is_sdp : 1;
+ u8 rsvd : 6;
+ u16 pcifunc;
+ u16 rx_chan_base;
+ u16 tx_chan_base;
+ u16 sq_cnt;
+ u16 cq_cnt;
+ u16 rq_cnt;
+ u8 rx_chan_cnt;
+ u8 tx_chan_cnt;
+ u8 tx_link;
+ u8 nix;
+};
+
+/* Max supported */
+#define IFACE_MAX (256 + 32) /* 32 PFs + 256 VFs */
+
+struct iface_get_info_rsp {
+ struct mbox_msghdr hdr;
+ u16 cnt;
+ u8 truncated;
+ u8 rsvd[5];
+ struct iface_info info[IFACE_MAX];
+};
+
+struct fl_info {
+ u64 cookie;
+ u16 mcam_idx[2];
+ u8 dis : 1;
+ u8 uni_di : 1;
+};
+
+struct swdev2af_notify_req {
+ struct mbox_msghdr hdr;
+ u64 msg_type;
+#define SWDEV2AF_MSG_TYPE_FW_STATUS BIT_ULL(0)
+#define SWDEV2AF_MSG_TYPE_REFRESH_FDB BIT_ULL(1)
+#define SWDEV2AF_MSG_TYPE_REFRESH_FL BIT_ULL(2)
+ u16 pcifunc;
+ union {
+ bool fw_up; // FW_STATUS message
+
+ u8 mac[ETH_ALEN]; // fdb refresh message
+
+ struct { // fl refresh message
+ u8 cnt;
+ u8 rsvd[7];
+ struct fl_info fl[64];
+ };
+ };
+};
+
struct flow_msg {
unsigned char dmac[6];
unsigned char smac[6];
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
index ffba56ee8a60..df4f1c05a2a0 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
@@ -1990,6 +1990,145 @@ int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req,
return 0;
}
+static bool rvu_iface_get_info_permitted(struct rvu *rvu, u16 pcifunc)
+{
+ if (rvu->rswitch.mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
+ return false;
+
+ return true;
+}
+
+int rvu_mbox_handler_iface_get_info(struct rvu *rvu, struct msg_req *req,
+ struct iface_get_info_rsp *rsp)
+{
+ struct iface_info *info;
+ bool truncated = false;
+ struct rvu_pfvf *pfvf;
+ int pf, vf, numvfs;
+ u16 pcifunc;
+ int tot = 0;
+ u64 cfg;
+
+ if (!rvu_iface_get_info_permitted(rvu, req->hdr.pcifunc))
+ return -EPERM;
+
+ memset(rsp, 0, sizeof(*rsp));
+ info = rsp->info;
+ for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
+ if (tot >= IFACE_MAX) {
+ truncated = true;
+ goto done;
+ }
+
+ cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
+ numvfs = (cfg >> 12) & 0xFF;
+
+ /* Skip not enabled PFs */
+ if (!(cfg & BIT_ULL(20)))
+ goto chk_vfs;
+
+ /* If Admin function, check on VFs */
+ if (cfg & BIT_ULL(21))
+ goto chk_vfs;
+
+ pcifunc = rvu_make_pcifunc(rvu->pdev, pf, 0);
+ pfvf = rvu_get_pfvf(rvu, pcifunc);
+
+ /* Populate iff at least one Tx channel */
+ if (!pfvf->tx_chan_cnt)
+ goto chk_vfs;
+
+ info->is_vf = 0;
+ info->pcifunc = pcifunc;
+ info->rx_chan_base = pfvf->rx_chan_base;
+ info->rx_chan_cnt = pfvf->rx_chan_cnt;
+ info->tx_chan_base = pfvf->tx_chan_base;
+ info->tx_chan_cnt = pfvf->tx_chan_cnt;
+ info->tx_link = nix_get_tx_link(rvu, pcifunc);
+ if (is_sdp_pfvf(rvu, pcifunc))
+ info->is_sdp = 1;
+
+ /* If interfaces are not UP, there are no queues */
+ info->sq_cnt = 0;
+ info->cq_cnt = 0;
+ info->rq_cnt = 0;
+
+ mutex_lock(&rvu->rsrc_lock);
+ if (pfvf->sq_bmap)
+ info->sq_cnt = bitmap_weight(pfvf->sq_bmap, BITS_PER_LONG * 16);
+
+ if (pfvf->cq_bmap)
+ info->cq_cnt = bitmap_weight(pfvf->cq_bmap, BITS_PER_LONG);
+
+ if (pfvf->rq_bmap)
+ info->rq_cnt = bitmap_weight(pfvf->rq_bmap, BITS_PER_LONG);
+ mutex_unlock(&rvu->rsrc_lock);
+
+ if (pfvf->nix_blkaddr == BLKADDR_NIX0)
+ info->nix = 0;
+ else
+ info->nix = 1;
+
+ info++;
+ tot++;
+
+chk_vfs:
+ for (vf = 0; vf < numvfs; vf++) {
+ if (tot >= IFACE_MAX) {
+ truncated = true;
+ goto done;
+ }
+
+ pcifunc = rvu_make_pcifunc(rvu->pdev, pf, vf + 1);
+ pfvf = rvu_get_pfvf(rvu, pcifunc);
+
+ if (!pfvf->tx_chan_cnt)
+ continue;
+
+ info->is_vf = 1;
+ info->pcifunc = pcifunc;
+ info->rx_chan_base = pfvf->rx_chan_base;
+ info->rx_chan_cnt = pfvf->rx_chan_cnt;
+ info->tx_chan_base = pfvf->tx_chan_base;
+ info->tx_chan_cnt = pfvf->tx_chan_cnt;
+ info->tx_link = nix_get_tx_link(rvu, pcifunc);
+ if (is_sdp_pfvf(rvu, pcifunc))
+ info->is_sdp = 1;
+
+ /* If interfaces are not UP, there are no queues */
+ info->sq_cnt = 0;
+ info->cq_cnt = 0;
+ info->rq_cnt = 0;
+
+ mutex_lock(&rvu->rsrc_lock);
+ if (pfvf->sq_bmap)
+ info->sq_cnt = bitmap_weight(pfvf->sq_bmap, BITS_PER_LONG * 16);
+
+ if (pfvf->cq_bmap)
+ info->cq_cnt = bitmap_weight(pfvf->cq_bmap, BITS_PER_LONG);
+
+ if (pfvf->rq_bmap)
+ info->rq_cnt = bitmap_weight(pfvf->rq_bmap, BITS_PER_LONG);
+
+ mutex_unlock(&rvu->rsrc_lock);
+
+ if (pfvf->nix_blkaddr == BLKADDR_NIX0)
+ info->nix = 0;
+ else
+ info->nix = 1;
+
+ info++;
+
+ tot++;
+ }
+ }
+done:
+ rsp->cnt = tot;
+ rsp->truncated = truncated;
+
+ return 0;
+}
+
int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req,
struct free_rsrcs_rsp *rsp)
{
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index c5610f242687..73d2329b5c26 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -1158,6 +1158,7 @@ void rvu_program_channels(struct rvu *rvu);
/* CN10K NIX */
void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw);
+int nix_get_tx_link(struct rvu *rvu, u16 pcifunc);
/* CN10K RVU - LMT*/
void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 78667a0977c0..67c9621dbc1d 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -32,7 +32,6 @@ static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc);
static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw,
u32 leaf_prof);
static const char *nix_get_ctx_name(int ctype);
-static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc);
enum mc_tbl_sz {
MC_TBL_SZ_256,
@@ -906,6 +905,8 @@ static void nix_setup_lso(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)
static void nix_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf)
{
+ mutex_lock(&rvu->rsrc_lock);
+
kfree(pfvf->rq_bmap);
kfree(pfvf->sq_bmap);
kfree(pfvf->cq_bmap);
@@ -931,6 +932,8 @@ static void nix_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf)
pfvf->rss_ctx = NULL;
pfvf->nix_qints_ctx = NULL;
pfvf->cq_ints_ctx = NULL;
+
+ mutex_unlock(&rvu->rsrc_lock);
}
static int nixlf_rss_ctx_init(struct rvu *rvu, int blkaddr,
@@ -2087,7 +2090,7 @@ static void nix_clear_tx_xoff(struct rvu *rvu, int blkaddr,
rvu_write64(rvu, blkaddr, reg, 0x0);
}
-static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc)
+int nix_get_tx_link(struct rvu *rvu, u16 pcifunc)
{
struct rvu_hwinfo *hw = rvu->hw;
int pf = rvu_get_pf(rvu->pdev, pcifunc);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
index 08b83de9beb4..b17da72250a3 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
@@ -3544,6 +3544,40 @@ int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu,
return rc;
}
+int rvu_mbox_handler_npc_flow_del_n_free(struct rvu *rvu,
+ struct npc_flow_del_n_free_req *mreq,
+ struct msg_rsp *rsp)
+{
+ struct npc_mcam_free_entry_req sreq = { 0 };
+ struct npc_delete_flow_req dreq = { 0 };
+ struct npc_delete_flow_rsp drsp = { 0 };
+ bool err = false;
+ int ret = 0, i;
+
+ sreq.hdr.pcifunc = mreq->hdr.pcifunc;
+ dreq.hdr.pcifunc = mreq->hdr.pcifunc;
+
+ if (!mreq->cnt || mreq->cnt > 256) {
+ dev_err(rvu->dev, "Invalid cnt=%u\n", mreq->cnt);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < mreq->cnt; i++) {
+ dreq.entry = mreq->entry[i];
+ rvu_mbox_handler_npc_delete_flow(rvu, &dreq, &drsp);
+
+ sreq.entry = mreq->entry[i];
+ ret = rvu_mbox_handler_npc_mcam_free_entry(rvu, &sreq, rsp);
+ if (ret) {
+ dev_err(rvu->dev, "free entry error for i=%d entry=%d\n",
+ i, mreq->entry[i]);
+ err = true;
+ }
+ }
+
+ return err ? -EINVAL : 0;
+}
+
int rvu_mbox_handler_npc_mcam_read_entry(struct rvu *rvu,
struct npc_mcam_read_entry_req *req,
struct npc_mcam_read_entry_rsp *rsp)
@@ -4398,6 +4432,72 @@ int rvu_mbox_handler_npc_mcam_entry_stats(struct rvu *rvu,
return 0;
}
+int rvu_mbox_handler_npc_mcam_mul_stats(struct rvu *rvu,
+ struct npc_mcam_get_mul_stats_req *req,
+ struct npc_mcam_get_mul_stats_rsp *rsp)
+{
+ struct npc_mcam *mcam = &rvu->hw->mcam;
+ u16 pcifunc = req->hdr.pcifunc;
+ int blkaddr, cnt = 0, i;
+ u16 index, cntr, entry;
+ u64 regval;
+ u32 bank;
+
+ if (!req->cnt || req->cnt > 256) {
+ dev_err(rvu->dev, "%s invalid request cnt=%u\n",
+ __func__, req->cnt);
+ return -EINVAL;
+ }
+
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
+ if (blkaddr < 0)
+ return NPC_MCAM_INVALID_REQ;
+
+ mutex_lock(&mcam->lock);
+
+ for (i = 0; i < req->cnt; i++) {
+ entry = npc_cn20k_vidx2idx(req->entry[i]);
+
+ if (npc_mcam_verify_entry(mcam, pcifunc, entry)) {
+ mutex_unlock(&mcam->lock);
+ dev_err(rvu->dev, "%s invalid mcam index=%d\n",
+ __func__, req->entry[i]);
+ return -EINVAL;
+ }
+
+ index = entry & (mcam->banksize - 1);
+ bank = npc_get_bank(mcam, entry);
+
+ if (is_cn20k(rvu->pdev)) {
+ regval = rvu_read64(rvu, blkaddr,
+ NPC_AF_CN20K_MCAMEX_BANKX_STAT_EXT(index,
+ bank));
+ rsp->stat[cnt] = regval;
+ cnt++;
+ continue;
+ }
+
+ /* read MCAM entry STAT_ACT register */
+ regval = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank));
+
+ if (!(regval & rvu->hw->npc_stat_ena)) {
+ rsp->stat[cnt] = 0;
+ cnt++;
+ continue;
+ }
+
+ cntr = regval & 0x1FF;
+
+ rsp->stat[cnt] = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(cntr));
+ rsp->stat[cnt] &= BIT_ULL(48) - 1;
+ cnt++;
+ }
+
+ rsp->cnt = cnt;
+ mutex_unlock(&mcam->lock);
+ return 0;
+}
+
void rvu_npc_clear_ucast_entry(struct rvu *rvu, int pcifunc, int nixlf)
{
struct npc_mcam *mcam = &rvu->hw->mcam;
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
index 91b5947dae06..09c7ee8571df 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
@@ -1926,6 +1926,17 @@ static int npc_delete_flow(struct rvu *rvu, struct rvu_npc_mcam_rule *rule,
return rvu_mbox_handler_npc_mcam_dis_entry(rvu, &dis_req, &dis_rsp);
}
+int rvu_mbox_handler_npc_mcam_get_features(struct rvu *rvu,
+ struct msg_req *req,
+ struct npc_mcam_get_features_rsp *rsp)
+{
+ struct npc_mcam *mcam = &rvu->hw->mcam;
+
+ rsp->rx_features = mcam->rx_features;
+ rsp->tx_features = mcam->tx_features;
+ return 0;
+}
+
int rvu_mbox_handler_npc_delete_flow(struct rvu *rvu,
struct npc_delete_flow_req *req,
struct npc_delete_flow_rsp *rsp)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
new file mode 100644
index 000000000000..fe143ad3f944
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell RVU Admin Function driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+
+#include "rvu.h"
+
+int rvu_mbox_handler_swdev2af_notify(struct rvu *rvu,
+ struct swdev2af_notify_req *req,
+ struct msg_rsp *rsp)
+{
+ return 0;
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h
new file mode 100644
index 000000000000..f28dba556d80
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Marvell RVU Admin Function driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+
+#ifndef RVU_SWITCH_H
+#define RVU_SWITCH_H
+
+#endif
--
2.43.0
^ permalink raw reply related
* [PATCH v3 net-next 4/9] octeontx2-af: switch: Representor for switch port
From: Ratheesh Kannoth @ 2026-07-14 1:53 UTC (permalink / raw)
To: linux-kernel, netdev
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, sgoutham,
Ratheesh Kannoth
In-Reply-To: <20260714015331.1801922-1-rkannoth@marvell.com>
Extends esw_cfg with a devlink-derived switch id, copies it into
rvu->rswitch on the AF, adds rvu_sw_port_id(), exports
rvu_rep_get_vlan_id().
Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
---
.../net/ethernet/marvell/octeontx2/af/mbox.h | 1 +
.../net/ethernet/marvell/octeontx2/af/rvu.h | 5 +++++
.../ethernet/marvell/octeontx2/af/rvu_rep.c | 3 ++-
.../marvell/octeontx2/af/switch/rvu_sw.c | 19 +++++++++++++++++++
.../marvell/octeontx2/af/switch/rvu_sw.h | 5 +++++
.../net/ethernet/marvell/octeontx2/nic/rep.c | 4 ++++
6 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index 23bc66ed854e..cdfb5a8bafb9 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -1834,6 +1834,7 @@ struct get_rep_cnt_rsp {
struct esw_cfg_req {
struct mbox_msghdr hdr;
u8 ena;
+ unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN];
u64 rsvd;
};
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 73d2329b5c26..8cf1ad9ec749 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -576,6 +576,10 @@ struct rvu_switch {
u16 *entry2pcifunc;
u16 mode;
u16 start_entry;
+ unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN];
+#define RVU_SWITCH_FLAG_FW_READY BIT_ULL(0)
+ u64 flags;
+ u16 pcifunc;
};
struct rep_evtq_ent {
@@ -1197,4 +1201,5 @@ int rvu_rep_install_mcam_rules(struct rvu *rvu);
void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena);
int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable);
int npc_mcam_verify_entry(struct npc_mcam *mcam, u16 pcifunc, int entry);
+u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc);
#endif /* RVU_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c
index a2781e0f504e..6bb6064b2391 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c
@@ -189,7 +189,7 @@ int rvu_mbox_handler_nix_lf_stats(struct rvu *rvu,
return 0;
}
-static u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc)
+u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc)
{
int id;
@@ -436,6 +436,7 @@ int rvu_mbox_handler_esw_cfg(struct rvu *rvu, struct esw_cfg_req *req,
return 0;
rvu->rep_mode = req->ena;
+ memcpy(rvu->rswitch.switch_id, req->switch_id, MAX_PHYS_ITEM_ID_LEN);
if (!rvu->rep_mode)
rvu_npc_free_mcam_entries(rvu, req->hdr.pcifunc, -1);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
index fe143ad3f944..403d57870efe 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
@@ -5,7 +5,26 @@
*
*/
+#include <linux/bitfield.h>
+
#include "rvu.h"
+#include "rvu_sw.h"
+
+u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc)
+{
+ u16 rep_id;
+
+ if (!rvu->rep2pfvf_map || !rvu->rep_cnt)
+ return RVU_SW_INVALID_PORT_ID;
+
+ rep_id = rvu_rep_get_vlan_id(rvu, pcifunc);
+ if (rep_id >= rvu->rep_cnt ||
+ rvu->rep2pfvf_map[rep_id] != pcifunc)
+ return RVU_SW_INVALID_PORT_ID;
+
+ return FIELD_PREP(GENMASK_ULL(31, 16), rep_id) |
+ FIELD_PREP(GENMASK_ULL(15, 0), pcifunc);
+}
int rvu_mbox_handler_swdev2af_notify(struct rvu *rvu,
struct swdev2af_notify_req *req,
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h
index f28dba556d80..e9ad32c84576 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h
@@ -8,4 +8,9 @@
#ifndef RVU_SWITCH_H
#define RVU_SWITCH_H
+/* RVU Switch */
+#define RVU_SW_INVALID_PORT_ID ((u32)~0U)
+
+u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc);
+
#endif
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c
index 0f5d5642d3f7..257a2ae6a53e 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c
@@ -399,8 +399,11 @@ static void rvu_rep_get_stats64(struct net_device *dev,
static int rvu_eswitch_config(struct otx2_nic *priv, u8 ena)
{
+ struct devlink_port_attrs attrs = {};
struct esw_cfg_req *req;
+ rvu_rep_devlink_set_switch_id(priv, &attrs.switch_id);
+
mutex_lock(&priv->mbox.lock);
req = otx2_mbox_alloc_msg_esw_cfg(&priv->mbox);
if (!req) {
@@ -408,6 +411,7 @@ static int rvu_eswitch_config(struct otx2_nic *priv, u8 ena)
return -ENOMEM;
}
req->ena = ena;
+ memcpy(req->switch_id, attrs.switch_id.id, attrs.switch_id.id_len);
otx2_sync_mbox_msg(&priv->mbox);
mutex_unlock(&priv->mbox.lock);
return 0;
--
2.43.0
^ permalink raw reply related
* [PATCH v3 net-next 1/9] octeontx2-af: switch: Add AF to switch mbox and skeleton files
From: Ratheesh Kannoth @ 2026-07-14 1:53 UTC (permalink / raw)
To: linux-kernel, netdev
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, sgoutham,
Ratheesh Kannoth
In-Reply-To: <20260714015331.1801922-1-rkannoth@marvell.com>
The Marvell switch hardware runs on a Linux OS. This OS receives
various messages, which are parsed to create flow rules that can be
installed on HW. The switch is capable of accelerating both L2 and
L3 flows.
This commit adds various mailbox messages used by the Linux OS
(on arm64) to send events to the switch hardware.
fdb messages: Linux bridge FDB messages
fib messages: Linux routing table messages
status messages: Packet status updates sent to Host
Linux to keep flows active
for connection-tracked flows.
Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
---
.../ethernet/marvell/octeontx2/af/Makefile | 3 +-
.../net/ethernet/marvell/octeontx2/af/mbox.h | 107 ++++++++++++++++++
.../marvell/octeontx2/af/switch/rvu_sw_fl.c | 21 ++++
.../marvell/octeontx2/af/switch/rvu_sw_fl.h | 11 ++
.../marvell/octeontx2/af/switch/rvu_sw_l2.c | 14 +++
.../marvell/octeontx2/af/switch/rvu_sw_l2.h | 11 ++
.../marvell/octeontx2/af/switch/rvu_sw_l3.c | 14 +++
.../marvell/octeontx2/af/switch/rvu_sw_l3.h | 11 ++
8 files changed, 191 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/Makefile b/drivers/net/ethernet/marvell/octeontx2/af/Makefile
index 91b7d6e96a61..82dd387308c9 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/Makefile
+++ b/drivers/net/ethernet/marvell/octeontx2/af/Makefile
@@ -3,7 +3,7 @@
# Makefile for Marvell's RVU Admin Function driver
#
-ccflags-y += -I$(src)
+ccflags-y += -I$(src) -I$(src)/switch/
obj-$(CONFIG_OCTEONTX2_MBOX) += rvu_mbox.o
obj-$(CONFIG_OCTEONTX2_AF) += rvu_af.o
@@ -12,5 +12,6 @@ rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \
rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \
rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o \
+ switch/rvu_sw_l2.o switch/rvu_sw_l3.o switch/rvu_sw_fl.o\
rvu_rep.o cn20k/mbox_init.o cn20k/nix.o cn20k/debugfs.o \
cn20k/npa.o cn20k/npc.o
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index f87cdf1b971d..2867da47d9f5 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -164,6 +164,14 @@ M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \
M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \
M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \
M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \
+M(FDB_NOTIFY, 0x010, fdb_notify, \
+ fdb_notify_req, msg_rsp) \
+M(FIB_NOTIFY, 0x011, fib_notify, \
+ fib_notify_req, msg_rsp) \
+M(FL_NOTIFY, 0x012, fl_notify, \
+ fl_notify_req, msg_rsp) \
+M(FL_GET_STATS, 0x013, fl_get_stats, \
+ fl_get_stats_req, fl_get_stats_rsp) \
/* CGX mbox IDs (range 0x200 - 0x3FF) */ \
M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
@@ -1807,6 +1815,105 @@ struct rep_event {
struct rep_evt_data evt_data;
};
+#define FDB_ADD BIT_ULL(0)
+#define FDB_DEL BIT_ULL(1)
+#define FIB_CMD BIT_ULL(2)
+#define FL_ADD BIT_ULL(3)
+#define FL_DEL BIT_ULL(4)
+#define DP_ADD BIT_ULL(5)
+
+struct fdb_notify_req {
+ struct mbox_msghdr hdr;
+ u64 flags;
+ u8 mac[ETH_ALEN];
+};
+
+struct fib_entry {
+ u64 cmd;
+ u64 gw_valid : 1;
+ u64 mac_valid : 1;
+ u64 vlan_valid: 1;
+ u64 host : 1;
+ u64 bridge : 1;
+ u64 ipv6 : 1;
+ __be16 vlan_tag;
+ u32 dst_len;
+ u8 dst6_plen;
+ u8 gw6_plen;
+ union {
+ __be32 dst;
+ __be32 dst6[4];
+ };
+ union {
+ __be32 gw;
+ __be32 gw6[4];
+ };
+ u16 port_id;
+ u8 nud_state;
+ u8 mac[ETH_ALEN];
+};
+
+struct fib_notify_req {
+ struct mbox_msghdr hdr;
+ u16 cnt;
+ u16 rsvd[3]; /* explicit padding for entry[] 8-byte alignment */
+ struct fib_entry entry[16];
+};
+
+struct fl_tuple {
+ __be32 ip4src;
+ __be32 m_ip4src;
+ __be32 ip4dst;
+ __be32 m_ip4dst;
+ __be16 sport;
+ __be16 m_sport;
+ __be16 dport;
+ __be16 m_dport;
+ __be16 eth_type;
+ __be16 m_eth_type;
+ u8 proto;
+ u8 smac[6];
+ u8 m_smac[6];
+ u8 dmac[6];
+ u8 m_dmac[6];
+ u64 is_xdev_br : 1;
+ u64 is_indev_br : 1;
+ u64 uni_di : 1;
+ u16 in_pf;
+ u16 xmit_pf;
+ u16 rsvd;
+ u64 features;
+ struct { /* FLOW_ACTION_MANGLE */
+ u8 offset;
+ u8 type;
+ u16 rsvd;
+ u32 mask;
+ u32 val;
+#define MANGLE_ARR_SZ 9
+ } mangle[MANGLE_ARR_SZ]; /* 2 for ETH, 1 for VLAN, 4 for IPv6, 2 for L4. */
+#define MANGLE_LAYER_CNT 4
+ u8 mangle_map[MANGLE_LAYER_CNT]; /* 1 for ETH, 1 for VLAN, 1 for L3, 1 for L4 */
+ u8 mangle_cnt;
+};
+
+struct fl_notify_req {
+ struct mbox_msghdr hdr;
+ u64 cookie;
+ u64 flags;
+ u64 features;
+ struct fl_tuple tuple;
+};
+
+struct fl_get_stats_req {
+ struct mbox_msghdr hdr;
+ u64 cookie;
+};
+
+struct fl_get_stats_rsp {
+ struct mbox_msghdr hdr;
+ u64 pkts_diff;
+};
+
struct flow_msg {
unsigned char dmac[6];
unsigned char smac[6];
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c
new file mode 100644
index 000000000000..1f8b82a84a5d
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell RVU Admin Function driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+#include "rvu.h"
+
+int rvu_mbox_handler_fl_get_stats(struct rvu *rvu,
+ struct fl_get_stats_req *req,
+ struct fl_get_stats_rsp *rsp)
+{
+ return 0;
+}
+
+int rvu_mbox_handler_fl_notify(struct rvu *rvu,
+ struct fl_notify_req *req,
+ struct msg_rsp *rsp)
+{
+ return 0;
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h
new file mode 100644
index 000000000000..cf3e5b884f77
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Marvell RVU Admin Function driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+
+#ifndef RVU_SW_FL_H
+#define RVU_SW_FL_H
+
+#endif
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c
new file mode 100644
index 000000000000..5f805bfa81ed
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell RVU Admin Function driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+#include "rvu.h"
+
+int rvu_mbox_handler_fdb_notify(struct rvu *rvu,
+ struct fdb_notify_req *req,
+ struct msg_rsp *rsp)
+{
+ return 0;
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h
new file mode 100644
index 000000000000..ff28612150c9
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Marvell RVU Admin Function driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+
+#ifndef RVU_SW_L2_H
+#define RVU_SW_L2_H
+
+#endif
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c
new file mode 100644
index 000000000000..2b798d5f0644
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell RVU Admin Function driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+#include "rvu.h"
+
+int rvu_mbox_handler_fib_notify(struct rvu *rvu,
+ struct fib_notify_req *req,
+ struct msg_rsp *rsp)
+{
+ return 0;
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h
new file mode 100644
index 000000000000..ac8c4f9ba5ac
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Marvell RVU Admin Function driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+
+#ifndef RVU_SW_L3_H
+#define RVU_SW_L3_H
+
+#endif
--
2.43.0
^ permalink raw reply related
* [PATCH v3 net-next 9/9] octeontx2: switch: add TC flow offload path for switch flows
From: Ratheesh Kannoth @ 2026-07-14 1:53 UTC (permalink / raw)
To: linux-kernel, netdev
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, sgoutham,
Ratheesh Kannoth
In-Reply-To: <20260714015331.1801922-1-rkannoth@marvell.com>
Register an ingress flow-table offload callback that translates TC
flower rules into fl_tuple state, resolves ingress and egress
pcifunc via FIB for accelerated ports, and notifies the RVU AF over
the PF mailbox. The AF forwards flow updates to switchdev and
keeps per-cookie packet counters in sync using NPC MCAM multi-stats
when the switch requests SWDEV2AF refresh.
Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
---
.../marvell/octeontx2/af/switch/rvu_sw.c | 13 +-
.../marvell/octeontx2/af/switch/rvu_sw_fl.c | 331 ++++++++
.../marvell/octeontx2/af/switch/rvu_sw_fl.h | 2 +
.../ethernet/marvell/octeontx2/nic/Makefile | 2 +-
.../marvell/octeontx2/nic/switch/sw_fl.c | 750 ++++++++++++++++++
.../marvell/octeontx2/nic/switch/sw_fl.h | 2 +
.../marvell/octeontx2/nic/switch/sw_trace.c | 11 +
.../marvell/octeontx2/nic/switch/sw_trace.h | 84 ++
8 files changed, 1193 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.h
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
index 6c70d1d727c4..f233fe7b2983 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
@@ -7,10 +7,10 @@
#include <linux/bitfield.h>
#include "rvu.h"
-#include "rvu_sw.h"
#include "rvu_sw_l2.h"
#include "rvu_sw_l3.h"
#include "rvu_sw_fl.h"
+#include "rvu_sw.h"
u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc)
{
@@ -65,6 +65,16 @@ int rvu_mbox_handler_swdev2af_notify(struct rvu *rvu,
case SWDEV2AF_MSG_TYPE_REFRESH_FDB:
rc = rvu_sw_l2_fdb_list_entry_add(rvu, req->pcifunc, req->mac);
break;
+
+ case SWDEV2AF_MSG_TYPE_REFRESH_FL:
+ if (req->cnt <= 0 || req->cnt > ARRAY_SIZE(req->fl))
+ return -EINVAL;
+ rc = rvu_sw_fl_stats_sync2db(rvu, req->fl, req->cnt);
+ break;
+
+ default:
+ rc = -EOPNOTSUPP;
+ break;
}
return rc;
@@ -74,4 +84,5 @@ void rvu_sw_shutdown(void)
{
rvu_sw_l2_shutdown();
rvu_sw_l3_shutdown();
+ rvu_sw_fl_shutdown();
}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c
index 1f8b82a84a5d..34e23d57e649 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c
@@ -4,12 +4,279 @@
* Copyright (C) 2026 Marvell.
*
*/
+
+#include <linux/bitfield.h>
#include "rvu.h"
+#include "rvu_sw.h"
+#include "rvu_sw_fl.h"
+
+#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
+static struct _req_type __maybe_unused \
+*otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \
+{ \
+ struct _req_type *req; \
+ \
+ req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
+ &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
+ sizeof(struct _rsp_type)); \
+ if (!req) \
+ return NULL; \
+ req->hdr.sig = OTX2_MBOX_REQ_SIG; \
+ req->hdr.id = _id; \
+ return req; \
+}
+
+MBOX_UP_AF2SWDEV_MESSAGES
+#undef M
+
+#define RVU_SW_FL_REFRESH_MAX \
+ ((int)ARRAY_SIZE(((struct swdev2af_notify_req *)0)->fl))
+
+struct fl_entry {
+ struct list_head list;
+ struct rvu *rvu;
+ u32 port_id;
+ unsigned long cookie;
+ struct fl_tuple tuple;
+ u64 flags;
+ u64 features;
+};
+
+static DEFINE_MUTEX(fl_offl_llock);
+static LIST_HEAD(fl_offl_lh);
+
+static struct workqueue_struct *sw_fl_offl_wq;
+static void sw_fl_offl_work_handler(struct work_struct *work);
+static DECLARE_DELAYED_WORK(fl_offl_work, sw_fl_offl_work_handler);
+
+struct sw_fl_stats_node {
+ struct list_head list;
+ unsigned long cookie;
+ u16 mcam_idx[2];
+ u64 opkts, npkts;
+ bool uni_di;
+};
+
+static LIST_HEAD(sw_fl_stats_lh);
+static DEFINE_MUTEX(sw_fl_stats_lock);
+
+static void rvu_sw_fl_queue_work(void)
+{
+ if (sw_fl_offl_wq)
+ queue_delayed_work(sw_fl_offl_wq, &fl_offl_work,
+ msecs_to_jiffies(10));
+}
+
+static int rvu_sw_fl_ensure_wq(void)
+{
+ if (sw_fl_offl_wq)
+ return 0;
+
+ sw_fl_offl_wq = alloc_workqueue("sw_af_fl_wq", 0, 0);
+ if (!sw_fl_offl_wq)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int
+rvu_sw_fl_stats_sync2db_one_entry(unsigned long cookie, u8 disabled,
+ u16 mcam_idx[2], bool uni_di, u64 pkts)
+{
+ struct sw_fl_stats_node *snode, *tmp;
+
+ mutex_lock(&sw_fl_stats_lock);
+ list_for_each_entry_safe(snode, tmp, &sw_fl_stats_lh, list) {
+ if (snode->cookie != cookie)
+ continue;
+
+ if (disabled) {
+ list_del_init(&snode->list);
+ mutex_unlock(&sw_fl_stats_lock);
+ kfree(snode);
+ return 0;
+ }
+
+ if (snode->uni_di != uni_di) {
+ snode->uni_di = uni_di;
+ snode->mcam_idx[1] = mcam_idx[1];
+ }
+
+ if (snode->opkts == pkts) {
+ mutex_unlock(&sw_fl_stats_lock);
+ return 0;
+ }
+
+ snode->npkts = pkts;
+ mutex_unlock(&sw_fl_stats_lock);
+ return 0;
+ }
+
+ if (disabled) {
+ mutex_unlock(&sw_fl_stats_lock);
+ return 0;
+ }
+
+ snode = kcalloc(1, sizeof(*snode), GFP_KERNEL);
+ if (!snode) {
+ mutex_unlock(&sw_fl_stats_lock);
+ return -ENOMEM;
+ }
+
+ snode->cookie = cookie;
+ snode->mcam_idx[0] = mcam_idx[0];
+ if (!uni_di)
+ snode->mcam_idx[1] = mcam_idx[1];
+
+ snode->npkts = pkts;
+ snode->uni_di = uni_di;
+ INIT_LIST_HEAD(&snode->list);
+
+ list_add_tail(&snode->list, &sw_fl_stats_lh);
+ mutex_unlock(&sw_fl_stats_lock);
+
+ return 0;
+}
+
+int rvu_sw_fl_stats_sync2db(struct rvu *rvu, struct fl_info *fl, int cnt)
+{
+ struct npc_mcam_get_mul_stats_req *req = NULL;
+ struct npc_mcam_get_mul_stats_rsp *rsp = NULL;
+ int i, idx;
+ int rc = 0;
+ u64 pkts;
+
+ if (cnt <= 0 || cnt > RVU_SW_FL_REFRESH_MAX)
+ return -EINVAL;
+
+ req = kcalloc(1, sizeof(*req), GFP_KERNEL);
+ if (!req) {
+ rc = -ENOMEM;
+ goto fail;
+ }
+
+ rsp = kcalloc(1, sizeof(*rsp), GFP_KERNEL);
+ if (!rsp) {
+ rc = -ENOMEM;
+ goto fail;
+ }
+
+ idx = 0;
+ for (i = 0; i < cnt; i++) {
+ req->entry[idx++] = fl[i].mcam_idx[0];
+ if (!fl[i].uni_di)
+ req->entry[idx++] = fl[i].mcam_idx[1];
+ }
+ req->cnt = idx;
+
+ if (idx > 256) {
+ rc = -EINVAL;
+ goto fail;
+ }
+
+ if (rvu_mbox_handler_npc_mcam_mul_stats(rvu, req, rsp)) {
+ dev_err(rvu->dev, "Error to get multiple stats\n");
+ rc = -EFAULT;
+ goto fail;
+ }
+
+ idx = 0;
+ for (i = 0; i < cnt; i++) {
+ pkts = rsp->stat[idx++];
+ if (!fl[i].uni_di)
+ pkts += rsp->stat[idx++];
+
+ rc |= rvu_sw_fl_stats_sync2db_one_entry(fl[i].cookie, fl[i].dis,
+ fl[i].mcam_idx,
+ fl[i].uni_di, pkts);
+ }
+
+fail:
+ kfree(req);
+ kfree(rsp);
+ return rc;
+}
+
+static int rvu_sw_fl_offl_rule_push(struct fl_entry *fl_entry)
+{
+ struct af2swdev_notify_req *req;
+ struct rvu *rvu;
+ int swdev_pf;
+
+ rvu = fl_entry->rvu;
+ swdev_pf = rvu_get_pf(rvu->pdev, rvu->rswitch.pcifunc);
+
+ mutex_lock(&rvu->mbox_lock);
+ req = otx2_mbox_alloc_msg_af2swdev_notify(rvu, swdev_pf);
+ if (!req) {
+ mutex_unlock(&rvu->mbox_lock);
+ return -ENOMEM;
+ }
+
+ req->tuple = fl_entry->tuple;
+ req->flags = fl_entry->flags;
+ req->cookie = fl_entry->cookie;
+ req->features = fl_entry->features;
+
+ if (!otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, swdev_pf)) {
+ mutex_unlock(&rvu->mbox_lock);
+ return -EBUSY;
+ }
+
+ otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, swdev_pf);
+
+ mutex_unlock(&rvu->mbox_lock);
+ return 0;
+}
+
+static void sw_fl_offl_work_handler(struct work_struct *work)
+{
+ struct fl_entry *fl_entry;
+
+ mutex_lock(&fl_offl_llock);
+ fl_entry = list_first_entry_or_null(&fl_offl_lh, struct fl_entry, list);
+ if (!fl_entry) {
+ mutex_unlock(&fl_offl_llock);
+ return;
+ }
+
+ list_del_init(&fl_entry->list);
+ mutex_unlock(&fl_offl_llock);
+
+ if (rvu_sw_fl_offl_rule_push(fl_entry)) {
+ mutex_lock(&fl_offl_llock);
+ list_add_tail(&fl_entry->list, &fl_offl_lh);
+ mutex_unlock(&fl_offl_llock);
+ if (sw_fl_offl_wq)
+ queue_delayed_work(sw_fl_offl_wq, &fl_offl_work,
+ msecs_to_jiffies(100));
+ return;
+ }
+
+ kfree(fl_entry);
+
+ mutex_lock(&fl_offl_llock);
+ if (!list_empty(&fl_offl_lh))
+ rvu_sw_fl_queue_work();
+ mutex_unlock(&fl_offl_llock);
+}
int rvu_mbox_handler_fl_get_stats(struct rvu *rvu,
struct fl_get_stats_req *req,
struct fl_get_stats_rsp *rsp)
{
+ struct sw_fl_stats_node *snode, *tmp;
+
+ mutex_lock(&sw_fl_stats_lock);
+ list_for_each_entry_safe(snode, tmp, &sw_fl_stats_lh, list) {
+ if (snode->cookie != req->cookie)
+ continue;
+
+ rsp->pkts_diff = snode->npkts - snode->opkts;
+ snode->opkts = snode->npkts;
+ break;
+ }
+ mutex_unlock(&sw_fl_stats_lock);
return 0;
}
@@ -17,5 +284,69 @@ int rvu_mbox_handler_fl_notify(struct rvu *rvu,
struct fl_notify_req *req,
struct msg_rsp *rsp)
{
+ struct fl_entry *fl_entry;
+ int rc;
+
+ if (!(rvu->rswitch.flags & RVU_SWITCH_FLAG_FW_READY))
+ return -EAGAIN;
+
+ fl_entry = kcalloc(1, sizeof(*fl_entry), GFP_KERNEL);
+ if (!fl_entry)
+ return -ENOMEM;
+
+ fl_entry->port_id = rvu_sw_port_id(rvu, req->hdr.pcifunc);
+ fl_entry->rvu = rvu;
+ INIT_LIST_HEAD(&fl_entry->list);
+ fl_entry->tuple = req->tuple;
+ fl_entry->cookie = req->cookie;
+ fl_entry->flags = req->flags;
+ fl_entry->features = req->features;
+
+ mutex_lock(&fl_offl_llock);
+ rc = rvu_sw_fl_ensure_wq();
+ if (rc) {
+ mutex_unlock(&fl_offl_llock);
+ kfree(fl_entry);
+ return rc;
+ }
+
+ list_add_tail(&fl_entry->list, &fl_offl_lh);
+ rvu_sw_fl_queue_work();
+ mutex_unlock(&fl_offl_llock);
+
return 0;
}
+
+void rvu_sw_fl_shutdown(void)
+{
+ struct sw_fl_stats_node *snode, *tmp;
+ struct workqueue_struct *wq;
+ struct fl_entry *entry;
+
+ mutex_lock(&sw_fl_stats_lock);
+ list_for_each_entry_safe(snode, tmp, &sw_fl_stats_lh, list) {
+ list_del_init(&snode->list);
+ kfree(snode);
+ }
+ mutex_unlock(&sw_fl_stats_lock);
+
+ if (!sw_fl_offl_wq)
+ return;
+
+ cancel_delayed_work_sync(&fl_offl_work);
+ wq = sw_fl_offl_wq;
+ sw_fl_offl_wq = NULL;
+ destroy_workqueue(wq);
+
+ mutex_lock(&fl_offl_llock);
+ while (1) {
+ entry = list_first_entry_or_null(&fl_offl_lh,
+ struct fl_entry, list);
+ if (!entry)
+ break;
+
+ list_del_init(&entry->list);
+ kfree(entry);
+ }
+ mutex_unlock(&fl_offl_llock);
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h
index cf3e5b884f77..f117a96fc33e 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h
@@ -7,5 +7,7 @@
#ifndef RVU_SW_FL_H
#define RVU_SW_FL_H
+int rvu_sw_fl_stats_sync2db(struct rvu *rvu, struct fl_info *fl, int cnt);
+void rvu_sw_fl_shutdown(void);
#endif
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile
index 02ab0634f58f..e4deead6d1e0 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_RVU_ESWITCH) += rvu_rep.o
rvu_nicpf-y := otx2_pf.o otx2_common.o otx2_txrx.o otx2_ethtool.o \
otx2_flows.o otx2_tc.o cn10k.o cn20k.o otx2_dmac_flt.o \
otx2_devlink.o qos_sq.o qos.o otx2_xsk.o \
- switch/sw_fdb.o switch/sw_fl.o
+ switch/sw_fdb.o switch/sw_fl.o switch/sw_trace.o
rvu_nicpf-$(CONFIG_OCTEONTX_SWITCH) += switch/sw_nb.o switch/sw_fib.o \
switch/sw_nb_v4.o
ifneq ($(CONFIG_IPV6),)
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c
index 36a2359a0a48..f4366cb97353 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c
@@ -4,13 +4,763 @@
* Copyright (C) 2026 Marvell.
*
*/
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/mutex.h>
+#include <linux/refcount.h>
+#include <net/switchdev.h>
+#include <net/netevent.h>
+#include <net/arp.h>
+#include <net/nexthop.h>
+#include <net/netfilter/nf_flow_table.h>
+
+#include "../otx2_reg.h"
+#include "../otx2_common.h"
+#include "../otx2_struct.h"
+#include "../cn10k.h"
+#include "sw_nb.h"
+#include "sw_trace.h"
#include "sw_fl.h"
+#if !IS_ENABLED(CONFIG_OCTEONTX_SWITCH)
+int sw_fl_setup_ft_block_ingress_cb(enum tc_setup_type type,
+ void *type_data, void *cb_priv)
+{
+ return -EOPNOTSUPP;
+}
+
+#else
+
+static DEFINE_SPINLOCK(sw_fl_lock);
+static LIST_HEAD(sw_fl_lh);
+
+struct sw_fl_list_entry {
+ struct list_head list;
+ u64 flags;
+ unsigned long cookie;
+ struct otx2_nic *pf;
+ netdevice_tracker dev_tracker;
+ struct fl_tuple tuple;
+};
+
+static struct workqueue_struct *sw_fl_wq;
+static struct work_struct sw_fl_work;
+
+struct sw_fl_ct_cb {
+ struct list_head list;
+ struct nf_flowtable *ft;
+ struct otx2_nic *nic;
+ refcount_t ref;
+};
+
+struct sw_fl_ct_cookie {
+ struct list_head list;
+ unsigned long cookie;
+ struct nf_flowtable *ft;
+ struct otx2_nic *nic;
+};
+
+static LIST_HEAD(sw_fl_ct_cb_list);
+static DEFINE_MUTEX(sw_fl_ct_cb_lock);
+static LIST_HEAD(sw_fl_ct_cookie_list);
+static DEFINE_MUTEX(sw_fl_ct_cookie_lock);
+
+static struct sw_fl_ct_cb *sw_fl_ct_cb_find(struct nf_flowtable *ft,
+ struct otx2_nic *nic)
+{
+ struct sw_fl_ct_cb *entry;
+
+ list_for_each_entry(entry, &sw_fl_ct_cb_list, list) {
+ if (entry->ft == ft && entry->nic == nic)
+ return entry;
+ }
+
+ return NULL;
+}
+
+static int sw_fl_ct_cb_get(struct nf_flowtable *ft, struct otx2_nic *nic)
+{
+ struct sw_fl_ct_cb *entry;
+ int err;
+
+ mutex_lock(&sw_fl_ct_cb_lock);
+ entry = sw_fl_ct_cb_find(ft, nic);
+ if (entry) {
+ refcount_inc(&entry->ref);
+ mutex_unlock(&sw_fl_ct_cb_lock);
+ return 0;
+ }
+
+ err = nf_flow_table_offload_add_cb(ft, sw_fl_setup_ft_block_ingress_cb, nic);
+ if (err && err != -EEXIST) {
+ mutex_unlock(&sw_fl_ct_cb_lock);
+ return err;
+ }
+
+ entry = kzalloc(sizeof(*entry), GFP_KERNEL);
+ if (!entry) {
+ if (!err)
+ nf_flow_table_offload_del_cb(ft,
+ sw_fl_setup_ft_block_ingress_cb,
+ nic);
+ mutex_unlock(&sw_fl_ct_cb_lock);
+ return -ENOMEM;
+ }
+
+ entry->ft = ft;
+ entry->nic = nic;
+ refcount_set(&entry->ref, 1);
+ list_add_tail(&entry->list, &sw_fl_ct_cb_list);
+ mutex_unlock(&sw_fl_ct_cb_lock);
+
+ return 0;
+}
+
+static void sw_fl_ct_cb_put(struct nf_flowtable *ft, struct otx2_nic *nic)
+{
+ struct sw_fl_ct_cb *entry;
+
+ mutex_lock(&sw_fl_ct_cb_lock);
+ entry = sw_fl_ct_cb_find(ft, nic);
+ if (!entry || !refcount_dec_and_test(&entry->ref)) {
+ mutex_unlock(&sw_fl_ct_cb_lock);
+ return;
+ }
+
+ list_del(&entry->list);
+ mutex_unlock(&sw_fl_ct_cb_lock);
+
+ nf_flow_table_offload_del_cb(ft, sw_fl_setup_ft_block_ingress_cb, nic);
+ kfree(entry);
+}
+
+static void sw_fl_ct_cookie_add(unsigned long cookie, struct nf_flowtable *ft,
+ struct otx2_nic *nic)
+{
+ struct sw_fl_ct_cookie *entry;
+
+ entry = kzalloc(sizeof(*entry), GFP_KERNEL);
+ if (!entry)
+ return;
+
+ entry->cookie = cookie;
+ entry->ft = ft;
+ entry->nic = nic;
+
+ mutex_lock(&sw_fl_ct_cookie_lock);
+ list_add_tail(&entry->list, &sw_fl_ct_cookie_list);
+ mutex_unlock(&sw_fl_ct_cookie_lock);
+}
+
+static void sw_fl_ct_cookie_put(unsigned long cookie)
+{
+ struct sw_fl_ct_cookie *entry, *tmp;
+
+ mutex_lock(&sw_fl_ct_cookie_lock);
+ list_for_each_entry_safe(entry, tmp, &sw_fl_ct_cookie_list, list) {
+ if (entry->cookie != cookie)
+ continue;
+
+ list_del(&entry->list);
+ mutex_unlock(&sw_fl_ct_cookie_lock);
+ sw_fl_ct_cb_put(entry->ft, entry->nic);
+ kfree(entry);
+ return;
+ }
+ mutex_unlock(&sw_fl_ct_cookie_lock);
+}
+
+static void sw_fl_ct_cb_flush(void)
+{
+ struct sw_fl_ct_cookie *cookie, *ctmp;
+ struct sw_fl_ct_cb *entry, *etmp;
+
+ mutex_lock(&sw_fl_ct_cookie_lock);
+ list_for_each_entry_safe(cookie, ctmp, &sw_fl_ct_cookie_list, list) {
+ list_del(&cookie->list);
+ kfree(cookie);
+ }
+ mutex_unlock(&sw_fl_ct_cookie_lock);
+
+ mutex_lock(&sw_fl_ct_cb_lock);
+ list_for_each_entry_safe(entry, etmp, &sw_fl_ct_cb_list, list) {
+ list_del(&entry->list);
+ nf_flow_table_offload_del_cb(entry->ft,
+ sw_fl_setup_ft_block_ingress_cb,
+ entry->nic);
+ kfree(entry);
+ }
+ mutex_unlock(&sw_fl_ct_cb_lock);
+}
+
+static int sw_fl_msg_send(struct otx2_nic *pf,
+ struct fl_tuple *tuple,
+ u64 flags,
+ unsigned long cookie)
+{
+ struct fl_notify_req *req;
+ int rc;
+
+ mutex_lock(&pf->mbox.lock);
+ req = otx2_mbox_alloc_msg_fl_notify(&pf->mbox);
+ if (!req) {
+ rc = -ENOMEM;
+ goto out;
+ }
+
+ req->tuple = *tuple;
+ req->flags = flags;
+ req->cookie = cookie;
+
+ rc = otx2_sync_mbox_msg(&pf->mbox);
+out:
+ mutex_unlock(&pf->mbox.lock);
+ return rc;
+}
+
+static void sw_fl_wq_handler(struct work_struct *work)
+{
+ struct sw_fl_list_entry *entry;
+ LIST_HEAD(tlist);
+
+ spin_lock_bh(&sw_fl_lock);
+ list_splice_init(&sw_fl_lh, &tlist);
+ spin_unlock_bh(&sw_fl_lock);
+
+ while ((entry =
+ list_first_entry_or_null(&tlist,
+ struct sw_fl_list_entry,
+ list)) != NULL) {
+ list_del_init(&entry->list);
+ if (sw_fl_msg_send(entry->pf, &entry->tuple,
+ entry->flags, entry->cookie)) {
+ netdev_err(entry->pf->netdev,
+ "Failed to notify flow update to AF, will retry\n");
+ spin_lock_bh(&sw_fl_lock);
+ if (sw_fl_wq) {
+ list_add_tail(&entry->list, &sw_fl_lh);
+ queue_work(sw_fl_wq, &sw_fl_work);
+ spin_unlock_bh(&sw_fl_lock);
+ continue;
+ }
+ spin_unlock_bh(&sw_fl_lock);
+ netdev_put(entry->pf->netdev, &entry->dev_tracker);
+ kfree(entry);
+ continue;
+ }
+ netdev_put(entry->pf->netdev, &entry->dev_tracker);
+ kfree(entry);
+ }
+
+ spin_lock_bh(&sw_fl_lock);
+ if (!list_empty(&sw_fl_lh) && sw_fl_wq)
+ queue_work(sw_fl_wq, &sw_fl_work);
+ spin_unlock_bh(&sw_fl_lock);
+}
+
+static int
+sw_fl_add_to_list(struct otx2_nic *pf, struct fl_tuple *tuple,
+ unsigned long cookie, bool add_fl)
+{
+ struct sw_fl_list_entry *entry;
+
+ entry = kcalloc(1, sizeof(*entry), GFP_ATOMIC);
+ if (!entry)
+ return -ENOMEM;
+
+ entry->pf = pf;
+ entry->flags = add_fl ? FL_ADD : FL_DEL;
+ if (add_fl)
+ entry->tuple = *tuple;
+ entry->cookie = cookie;
+ entry->tuple.uni_di = netif_is_ovs_port(pf->netdev);
+
+ spin_lock_bh(&sw_fl_lock);
+ if (!sw_fl_wq) {
+ spin_unlock_bh(&sw_fl_lock);
+ kfree(entry);
+ return -EINVAL;
+ }
+
+ netdev_hold(pf->netdev, &entry->dev_tracker, GFP_ATOMIC);
+ list_add_tail(&entry->list, &sw_fl_lh);
+ queue_work(sw_fl_wq, &sw_fl_work);
+ spin_unlock_bh(&sw_fl_lock);
+
+ return 0;
+}
+
+static int sw_fl_parse_actions(struct otx2_nic *nic,
+ struct flow_action *flow_action,
+ struct flow_cls_offload *f,
+ struct fl_tuple *tuple, u64 *op,
+ struct nf_flowtable **ct_ft)
+{
+ struct flow_action_entry *act;
+ struct otx2_nic *out_nic;
+ int used = 0;
+ int err;
+ int i;
+
+ if (!flow_action_has_entries(flow_action))
+ return -EINVAL;
+
+ flow_action_for_each(i, act, flow_action) {
+ if (used >= MANGLE_ARR_SZ) {
+ netdev_err(nic->netdev,
+ "%s: More entries than supported %u\n",
+ __func__, used);
+ return -ENOMEM;
+ }
+
+ switch (act->id) {
+ case FLOW_ACTION_REDIRECT:
+ if (!act->dev || !sw_nb_is_valid_dev(act->dev))
+ return -EOPNOTSUPP;
+ trace_sw_act_dump(__func__, "redirect to egress port", act->id);
+ tuple->in_pf = nic->pcifunc;
+ out_nic = netdev_priv(act->dev);
+ tuple->xmit_pf = out_nic->pcifunc;
+ *op |= BIT_ULL(FLOW_ACTION_REDIRECT);
+ break;
+
+ case FLOW_ACTION_CT:
+ trace_sw_act_dump(__func__, "register conntrack offload callback", act->id);
+ err = sw_fl_ct_cb_get(act->ct.flow_table, nic);
+ if (err) {
+ netdev_err(nic->netdev,
+ "%s: Error to offload flow, err=%d\n",
+ __func__, err);
+ return err;
+ }
+
+ if (ct_ft)
+ *ct_ft = act->ct.flow_table;
+ *op |= BIT_ULL(FLOW_ACTION_CT);
+ break;
+
+ case FLOW_ACTION_MANGLE:
+ trace_sw_act_dump(__func__, "header mangle action", act->id);
+ tuple->mangle[used].type = act->mangle.htype;
+ tuple->mangle[used].val = act->mangle.val;
+ tuple->mangle[used].mask = act->mangle.mask;
+ tuple->mangle[used].offset = act->mangle.offset;
+ tuple->mangle_map[act->mangle.htype] |= BIT(used);
+ used++;
+ break;
+
+ default:
+ trace_sw_act_dump(__func__, "unsupported flow action", act->id);
+ break;
+ }
+ }
+
+ tuple->mangle_cnt = used;
+
+ if (!*op && !used) {
+ netdev_dbg(nic->netdev, "%s: Op is not valid\n", __func__);
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
+static int sw_fl_get_route(struct net *net, struct fib_result *res, __be32 addr)
+{
+ struct flowi4 fl4;
+
+ memset(&fl4, 0, sizeof(fl4));
+ fl4.daddr = addr;
+ return fib_lookup(net, &fl4, res, 0);
+}
+
+static int sw_fl_get_pcifunc(struct otx2_nic *pf, __be32 dst, u16 *pcifunc,
+ struct fl_tuple *ftuple, bool is_in_dev)
+{
+ struct fib_nh_common *fib_nhc;
+ struct net_device *dev, *br;
+ struct fib_result res;
+ struct list_head *lh;
+ struct otx2_nic *nic;
+ int err;
+
+ rcu_read_lock();
+
+ err = sw_fl_get_route(dev_net(pf->netdev), &res, dst);
+ if (err) {
+ netdev_err(pf->netdev,
+ "%s: Failed to find route to dst %pI4\n",
+ __func__, &dst);
+ goto done;
+ }
+
+ if (res.fi->fib_type != RTN_UNICAST) {
+ netdev_err(pf->netdev,
+ "%s: Not unicast route to dst %pi4\n",
+ __func__, &dst);
+ err = -EFAULT;
+ goto done;
+ }
+
+ fib_nhc = fib_info_nhc(res.fi, 0);
+ if (!fib_nhc) {
+ err = -EINVAL;
+ netdev_err(pf->netdev,
+ "%s: Could not get fib_nhc for %pI4\n",
+ __func__, &dst);
+ goto done;
+ }
+
+ if (unlikely(netif_is_bridge_master(fib_nhc->nhc_dev))) {
+ br = fib_nhc->nhc_dev;
+
+ if (is_in_dev)
+ ftuple->is_indev_br = 1;
+ else
+ ftuple->is_xdev_br = 1;
+
+ lh = &br->adj_list.lower;
+ if (list_empty(lh)) {
+ netdev_err(pf->netdev,
+ "%s: Unable to find any slave device\n",
+ __func__);
+ err = -EINVAL;
+ goto done;
+ }
+ dev = netdev_next_lower_dev_rcu(br, &lh);
+
+ } else {
+ dev = fib_nhc->nhc_dev;
+ }
+
+ if (!dev || !sw_nb_is_valid_dev(dev)) {
+ netdev_err(pf->netdev,
+ "%s: flow acceleration support is only for cavium devices\n",
+ __func__);
+ err = -EOPNOTSUPP;
+ goto done;
+ }
+
+ nic = netdev_priv(dev);
+ *pcifunc = nic->pcifunc;
+
+done:
+ rcu_read_unlock();
+ return err;
+}
+
+static int sw_fl_parse_flow(struct otx2_nic *nic, struct flow_cls_offload *f,
+ struct fl_tuple *tuple, u64 *features)
+{
+ struct flow_rule *rule;
+ u8 ip_proto = 0;
+
+ *features = 0;
+
+ rule = flow_cls_offload_flow_rule(f);
+
+ if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
+ struct flow_match_basic match;
+
+ flow_rule_match_basic(rule, &match);
+
+ /* All EtherTypes can be matched, no hw limitation */
+
+ if (match.mask->n_proto) {
+ tuple->eth_type = match.key->n_proto;
+ tuple->m_eth_type = match.mask->n_proto;
+ *features |= BIT_ULL(NPC_ETYPE);
+ }
+
+ if (match.mask->ip_proto) {
+ if (match.key->ip_proto != IPPROTO_TCP &&
+ match.key->ip_proto != IPPROTO_UDP)
+ return -EOPNOTSUPP;
+
+ ip_proto = match.key->ip_proto;
+ if (ip_proto == IPPROTO_UDP)
+ *features |= BIT_ULL(NPC_IPPROTO_UDP);
+ else
+ *features |= BIT_ULL(NPC_IPPROTO_TCP);
+ }
+
+ tuple->proto = ip_proto;
+ }
+
+ if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
+ struct flow_match_eth_addrs match;
+
+ flow_rule_match_eth_addrs(rule, &match);
+
+ if (!is_zero_ether_addr(match.key->dst) &&
+ is_unicast_ether_addr(match.key->dst)) {
+ ether_addr_copy(tuple->dmac,
+ match.key->dst);
+
+ ether_addr_copy(tuple->m_dmac,
+ match.mask->dst);
+
+ *features |= BIT_ULL(NPC_DMAC);
+ }
+
+ if (!is_zero_ether_addr(match.key->src) &&
+ is_unicast_ether_addr(match.key->src)) {
+ ether_addr_copy(tuple->smac,
+ match.key->src);
+ ether_addr_copy(tuple->m_smac,
+ match.mask->src);
+ *features |= BIT_ULL(NPC_SMAC);
+ }
+ }
+
+ if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IPV4_ADDRS)) {
+ struct flow_match_ipv4_addrs match;
+
+ flow_rule_match_ipv4_addrs(rule, &match);
+
+ if (match.mask->dst) {
+ tuple->ip4dst = match.key->dst;
+ tuple->m_ip4dst = match.mask->dst;
+ *features |= BIT_ULL(NPC_DIP_IPV4);
+ }
+
+ if (match.mask->src) {
+ tuple->ip4src = match.key->src;
+ tuple->m_ip4src = match.mask->src;
+ *features |= BIT_ULL(NPC_SIP_IPV4);
+ }
+ }
+
+ if (!(*features & BIT_ULL(NPC_DMAC))) {
+ if (!tuple->m_ip4src || !tuple->m_ip4dst) {
+ netdev_err(nic->netdev,
+ "%s: Invalid src=%pI4 and dst=%pI4 addresses\n",
+ __func__, &tuple->ip4src, &tuple->ip4dst);
+ return -EINVAL;
+ }
+
+ if ((tuple->ip4src & tuple->m_ip4src) == (tuple->ip4dst & tuple->m_ip4dst)) {
+ netdev_err(nic->netdev,
+ "%s: Masked values are same; Invalid src=%pI4 and dst=%pI4 addresses\n",
+ __func__, &tuple->ip4src, &tuple->ip4dst);
+ return -EINVAL;
+ }
+ }
+
+ if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
+ struct flow_match_ports match;
+
+ flow_rule_match_ports(rule, &match);
+
+ if (ip_proto == IPPROTO_UDP) {
+ if (match.mask->dst)
+ *features |= BIT_ULL(NPC_DPORT_UDP);
+
+ if (match.mask->src)
+ *features |= BIT_ULL(NPC_SPORT_UDP);
+ } else if (ip_proto == IPPROTO_TCP) {
+ if (match.mask->dst)
+ *features |= BIT_ULL(NPC_DPORT_TCP);
+
+ if (match.mask->src)
+ *features |= BIT_ULL(NPC_SPORT_TCP);
+ }
+
+ if (match.mask->src) {
+ tuple->sport = match.key->src;
+ tuple->m_sport = match.mask->src;
+ }
+
+ if (match.mask->dst) {
+ tuple->dport = match.key->dst;
+ tuple->m_dport = match.mask->dst;
+ }
+ }
+
+ if (!(*features & (BIT_ULL(NPC_DMAC) |
+ BIT_ULL(NPC_SMAC) |
+ BIT_ULL(NPC_DIP_IPV4) |
+ BIT_ULL(NPC_SIP_IPV4) |
+ BIT_ULL(NPC_DIP_IPV6) |
+ BIT_ULL(NPC_SIP_IPV6) |
+ BIT_ULL(NPC_DPORT_UDP) |
+ BIT_ULL(NPC_SPORT_UDP) |
+ BIT_ULL(NPC_DPORT_TCP) |
+ BIT_ULL(NPC_SPORT_TCP)))) {
+ return -EINVAL;
+ }
+
+ tuple->features = *features;
+
+ return 0;
+}
+
+static int sw_fl_add(struct otx2_nic *nic, struct flow_cls_offload *f)
+{
+ struct nf_flowtable *ct_ft = NULL;
+ struct fl_tuple tuple = { 0 };
+ struct flow_rule *rule;
+ u64 features = 0;
+ u64 op = 0;
+ int rc;
+
+ rule = flow_cls_offload_flow_rule(f);
+
+ rc = sw_fl_parse_actions(nic, &rule->action, f, &tuple, &op, &ct_ft);
+ if (rc)
+ return rc;
+
+ if (op & BIT_ULL(FLOW_ACTION_CT)) {
+ if (ct_ft)
+ sw_fl_ct_cookie_add(f->cookie, ct_ft, nic);
+ return 0;
+ }
+
+ rc = sw_fl_parse_flow(nic, f, &tuple, &features);
+ if (rc) {
+ trace_sw_fl_dump(__func__, "flow key parse failed", &tuple);
+ return -EFAULT;
+ }
+
+ if (!netif_is_ovs_port(nic->netdev)) {
+ rc = sw_fl_get_pcifunc(nic, tuple.ip4src, &tuple.in_pf,
+ &tuple, true);
+ if (rc) {
+ trace_sw_fl_dump(__func__, "ingress pcifunc lookup failed", &tuple);
+ return rc;
+ }
+
+ rc = sw_fl_get_pcifunc(nic, tuple.ip4dst,
+ &tuple.xmit_pf, &tuple, false);
+ if (rc) {
+ trace_sw_fl_dump(__func__, "egress pcifunc lookup failed", &tuple);
+ return rc;
+ }
+ }
+
+ trace_sw_fl_dump(__func__, "offload flow add queued", &tuple);
+ return sw_fl_add_to_list(nic, &tuple, f->cookie, true);
+}
+
+static int sw_fl_del(struct otx2_nic *nic, struct flow_cls_offload *f)
+{
+ sw_fl_ct_cookie_put(f->cookie);
+ sw_fl_add_to_list(nic, NULL, f->cookie, false);
+ return 0;
+}
+
+static int sw_fl_stats(struct otx2_nic *nic, struct flow_cls_offload *f)
+{
+ struct fl_get_stats_req *req;
+ struct fl_get_stats_rsp *rsp;
+ u64 pkts_diff;
+ int rc = 0;
+
+ mutex_lock(&nic->mbox.lock);
+
+ req = otx2_mbox_alloc_msg_fl_get_stats(&nic->mbox);
+ if (!req) {
+ netdev_err(nic->netdev,
+ "%s: Error happened while mcam alloc req\n",
+ __func__);
+ rc = -ENOMEM;
+ goto fail;
+ }
+ req->cookie = f->cookie;
+
+ rc = otx2_sync_mbox_msg(&nic->mbox);
+ if (rc)
+ goto fail;
+
+ rsp = (struct fl_get_stats_rsp *)otx2_mbox_get_rsp
+ (&nic->mbox.mbox, 0, &req->hdr);
+ if (IS_ERR(rsp)) {
+ rc = PTR_ERR(rsp);
+ goto fail;
+ }
+ pkts_diff = rsp->pkts_diff;
+ mutex_unlock(&nic->mbox.lock);
+
+ if (pkts_diff) {
+ flow_stats_update(&f->stats, 0x0, pkts_diff,
+ 0x0, jiffies,
+ FLOW_ACTION_HW_STATS_IMMEDIATE);
+ }
+ return 0;
+fail:
+ mutex_unlock(&nic->mbox.lock);
+ return rc;
+}
+
+static bool init_done;
+
+int sw_fl_setup_ft_block_ingress_cb(enum tc_setup_type type,
+ void *type_data, void *cb_priv)
+{
+ struct flow_cls_offload *cls = type_data;
+ struct otx2_nic *nic = cb_priv;
+
+ if (!smp_load_acquire(&init_done))
+ return 0;
+
+ switch (cls->command) {
+ case FLOW_CLS_REPLACE:
+ return sw_fl_add(nic, cls);
+ case FLOW_CLS_DESTROY:
+ return sw_fl_del(nic, cls);
+ case FLOW_CLS_STATS:
+ return sw_fl_stats(nic, cls);
+ default:
+ break;
+ }
+
+ return -EOPNOTSUPP;
+}
+
int sw_fl_init(void)
{
+ INIT_WORK(&sw_fl_work, sw_fl_wq_handler);
+ sw_fl_wq = alloc_workqueue("sw_fl_wq", 0, 0);
+ if (!sw_fl_wq)
+ return -ENOMEM;
+
+ smp_store_release(&init_done, true);
return 0;
}
void sw_fl_deinit(void)
{
+ struct sw_fl_list_entry *entry;
+ struct workqueue_struct *wq;
+ LIST_HEAD(tlist);
+
+ smp_store_release(&init_done, false);
+
+ spin_lock_bh(&sw_fl_lock);
+ wq = sw_fl_wq;
+ sw_fl_wq = NULL;
+ spin_unlock_bh(&sw_fl_lock);
+
+ if (!wq)
+ return;
+
+ cancel_work_sync(&sw_fl_work);
+ destroy_workqueue(wq);
+
+ spin_lock_bh(&sw_fl_lock);
+ list_splice_init(&sw_fl_lh, &tlist);
+ spin_unlock_bh(&sw_fl_lock);
+
+ while ((entry =
+ list_first_entry_or_null(&tlist,
+ struct sw_fl_list_entry,
+ list)) != NULL) {
+ list_del_init(&entry->list);
+ netdev_put(entry->pf->netdev, &entry->dev_tracker);
+ kfree(entry);
+ }
+
+ sw_fl_ct_cb_flush();
}
+#endif
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h
index cd018d770a8a..8dd816eb17d2 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h
@@ -9,5 +9,7 @@
void sw_fl_deinit(void);
int sw_fl_init(void);
+int sw_fl_setup_ft_block_ingress_cb(enum tc_setup_type type,
+ void *type_data, void *cb_priv);
#endif // SW_FL_H
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.c
new file mode 100644
index 000000000000..672f3405de85
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell RVU Admin Function driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+
+#define CREATE_TRACE_POINTS
+#if IS_ENABLED(CONFIG_OCTEONTX_SWITCH)
+#include "sw_trace.h"
+#endif
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.h b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.h
new file mode 100644
index 000000000000..3c94f2d02001
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Marvell RVU Admin Function driver
+ *
+ * Copyright (C) 2026 Marvell.
+ *
+ */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM rvu_sw
+
+#if !defined(SW_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
+#define SW_TRACE_H
+
+#include <linux/types.h>
+#include <linux/tracepoint.h>
+#include <linux/byteorder/generic.h>
+
+#include "mbox.h"
+
+TRACE_EVENT(sw_fl_dump,
+ TP_PROTO(const char *fname, const char *info, struct fl_tuple *ftuple),
+ TP_ARGS(fname, info, ftuple),
+ TP_STRUCT__entry(__string(f, fname)
+ __string(info, info)
+ __array(u8, smac, ETH_ALEN)
+ __array(u8, dmac, ETH_ALEN)
+ __field_struct(__be16, eth_type)
+ __field_struct(__be32, sip)
+ __field_struct(__be32, dip)
+ __field(u8, ip_proto)
+ __field_struct(__be16, sport)
+ __field_struct(__be16, dport)
+ __field(u8, uni_di)
+ __field(u16, in_pf)
+ __field(u16, out_pf)
+ ),
+ TP_fast_assign(__assign_str(f);
+ __assign_str(info);
+ memcpy(__entry->smac, ftuple->smac, ETH_ALEN);
+ memcpy(__entry->dmac, ftuple->dmac, ETH_ALEN);
+ __entry->sip = ftuple->ip4src;
+ __entry->dip = ftuple->ip4dst;
+ __entry->eth_type = ftuple->eth_type;
+ __entry->ip_proto = ftuple->proto;
+ __entry->sport = ftuple->sport;
+ __entry->dport = ftuple->dport;
+ __entry->uni_di = ftuple->uni_di;
+ __entry->in_pf = ftuple->in_pf;
+ __entry->out_pf = ftuple->xmit_pf;
+ ),
+ TP_printk("[%s] %s: %pM %pI4:%u to %pM %pI4:%u eth_type=%#x proto=%u uni=%u in=%#x out=%#x",
+ __get_str(f), __get_str(info),
+ __entry->smac, &__entry->sip, __entry->sport,
+ __entry->dmac, &__entry->dip, __entry->dport,
+ __entry->eth_type, __entry->ip_proto, __entry->uni_di,
+ __entry->in_pf, __entry->out_pf)
+);
+
+TRACE_EVENT(sw_act_dump,
+ TP_PROTO(const char *fname, const char *info, u32 act),
+ TP_ARGS(fname, info, act),
+ TP_STRUCT__entry(__string(fname, fname)
+ __string(info, info)
+ __field(u32, act)
+ ),
+
+ TP_fast_assign(__assign_str(fname);
+ __assign_str(info);
+ __entry->act = act;
+ ),
+
+ TP_printk("[%s] %s: act=%u",
+ __get_str(fname), __get_str(info), __entry->act)
+);
+
+#endif
+
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH ../../drivers/net/ethernet/marvell/octeontx2/nic/switch/
+
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE sw_trace
+
+#include <trace/define_trace.h>
--
2.43.0
^ permalink raw reply related
* [PATCH v3 net-next 8/9] octeontx2: switch: offload host FIB updates to switch via AF mailbox
From: Ratheesh Kannoth @ 2026-07-14 1:53 UTC (permalink / raw)
To: linux-kernel, netdev
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, sgoutham,
Ratheesh Kannoth
In-Reply-To: <20260714015331.1801922-1-rkannoth@marvell.com>
Queue IPv4/IPv6 FIB-derived updates from the switch notifier path
and handle fib_notify in the RVU AF by batching fib_entry
structures and sending them to the switch PF through the
AF-to-switchdev FIB_CMD. Require the switch firmware to
be ready before accepting offload work.
Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
---
.../marvell/octeontx2/af/switch/rvu_sw.c | 22 +-
.../marvell/octeontx2/af/switch/rvu_sw_l3.c | 245 ++++++++++++++++++
.../marvell/octeontx2/af/switch/rvu_sw_l3.h | 1 +
.../marvell/octeontx2/nic/switch/sw_fib.c | 189 ++++++++++++++
.../marvell/octeontx2/nic/switch/sw_fib.h | 10 +
.../marvell/octeontx2/nic/switch/sw_nb.c | 11 +-
.../marvell/octeontx2/nic/switch/sw_nb_v4.c | 141 +++++-----
.../marvell/octeontx2/nic/switch/sw_nb_v6.c | 15 +-
.../marvell/octeontx2/nic/switch/sw_nb_v6.h | 31 ++-
9 files changed, 574 insertions(+), 91 deletions(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
index b9cd7c7524b9..6c70d1d727c4 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
@@ -6,26 +6,23 @@
*/
#include <linux/bitfield.h>
-
#include "rvu.h"
#include "rvu_sw.h"
#include "rvu_sw_l2.h"
+#include "rvu_sw_l3.h"
#include "rvu_sw_fl.h"
u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc)
{
+ u32 port_id;
u16 rep_id;
- if (!rvu->rep2pfvf_map || !rvu->rep_cnt)
- return RVU_SW_INVALID_PORT_ID;
+ rep_id = rvu_rep_get_vlan_id(rvu, pcifunc);
- rep_id = rvu_rep_get_vlan_id(rvu, pcifunc);
- if (rep_id >= rvu->rep_cnt ||
- rvu->rep2pfvf_map[rep_id] != pcifunc)
- return RVU_SW_INVALID_PORT_ID;
+ port_id = FIELD_PREP(GENMASK_ULL(31, 16), rep_id) |
+ FIELD_PREP(GENMASK_ULL(15, 0), pcifunc);
- return FIELD_PREP(GENMASK_ULL(31, 16), rep_id) |
- FIELD_PREP(GENMASK_ULL(15, 0), pcifunc);
+ return port_id;
}
static bool rvu_sw_swdev2af_msg_valid(u64 msg_type)
@@ -54,7 +51,7 @@ int rvu_mbox_handler_swdev2af_notify(struct rvu *rvu,
struct swdev2af_notify_req *req,
struct msg_rsp *rsp)
{
- int rc;
+ int rc = 0;
rc = rvu_sw_swdev2af_sender_check(rvu, req, req->msg_type);
if (rc)
@@ -68,10 +65,6 @@ int rvu_mbox_handler_swdev2af_notify(struct rvu *rvu,
case SWDEV2AF_MSG_TYPE_REFRESH_FDB:
rc = rvu_sw_l2_fdb_list_entry_add(rvu, req->pcifunc, req->mac);
break;
-
- default:
- rc = -EOPNOTSUPP;
- break;
}
return rc;
@@ -80,4 +73,5 @@ int rvu_mbox_handler_swdev2af_notify(struct rvu *rvu,
void rvu_sw_shutdown(void)
{
rvu_sw_l2_shutdown();
+ rvu_sw_l3_shutdown();
}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c
index 2b798d5f0644..b9ba5ea1aaef 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c
@@ -4,11 +4,256 @@
* Copyright (C) 2026 Marvell.
*
*/
+
+#include <linux/bitfield.h>
#include "rvu.h"
+#include "rvu_sw.h"
+#include "rvu_sw_l3.h"
+
+#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
+static struct _req_type __maybe_unused \
+*otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \
+{ \
+ struct _req_type *req; \
+ \
+ req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
+ &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
+ sizeof(struct _rsp_type)); \
+ if (!req) \
+ return NULL; \
+ req->hdr.sig = OTX2_MBOX_REQ_SIG; \
+ req->hdr.id = _id; \
+ return req; \
+}
+
+MBOX_UP_AF2SWDEV_MESSAGES
+#undef M
+
+#define RVU_SW_L3_BATCH_MAX \
+ ((int)(sizeof_field(struct af2swdev_notify_req, entry) / \
+ sizeof(struct fib_entry)))
+
+struct l3_entry {
+ struct list_head list;
+ /* Always this AF driver's rvu; stored for clarity only (single RVU). */
+ struct rvu *rvu;
+ u32 port_id;
+ int cnt;
+ struct fib_entry entry[];
+};
+
+static DEFINE_MUTEX(l3_offl_llock);
+/*
+ * Pending FIB updates from host PFs on this RVU. The list is per-AF-module
+ * (one octeontx2-af instance / one RVU chip), not shared across RVU devices.
+ */
+static LIST_HEAD(l3_offl_lh);
+
+static struct workqueue_struct *sw_l3_offl_wq;
+static void sw_l3_offl_work_handler(struct work_struct *work);
+static DECLARE_DELAYED_WORK(l3_offl_work, sw_l3_offl_work_handler);
+
+/*
+ * FIB offload to the switch ASIC: one octeontx2 AF driver instance, one
+ * switch PF (switchdev), and one sw_l3_offl_wq per SoC.
+ */
+
+static void rvu_sw_l3_drain_list(struct list_head *lh)
+{
+ struct l3_entry *entry;
+
+ while ((entry = list_first_entry_or_null(lh, struct l3_entry, list))) {
+ list_del(&entry->list);
+ kfree(entry);
+ }
+}
+
+static void rvu_sw_l3_queue_work(void)
+{
+ if (sw_l3_offl_wq)
+ queue_delayed_work(sw_l3_offl_wq, &l3_offl_work,
+ msecs_to_jiffies(10));
+}
+
+static int rvu_sw_l3_ensure_wq(void)
+{
+ if (sw_l3_offl_wq)
+ return 0;
+
+ sw_l3_offl_wq = alloc_workqueue("sw_af_fib_wq", 0, 0);
+ if (!sw_l3_offl_wq)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int rvu_sw_l3_offl_rule_push(struct list_head *lh)
+{
+ struct af2swdev_notify_req *req;
+ struct fib_entry *entry, *dst;
+ struct l3_entry *l3_entry;
+ struct rvu *rvu;
+ int tot_cnt = 0;
+ int swdev_pf;
+ int sz, cnt, i;
+ bool rc;
+
+ BUILD_BUG_ON(sizeof_field(struct af2swdev_notify_req, entry) !=
+ sizeof(struct fib_entry) * RVU_SW_L3_BATCH_MAX);
+
+ l3_entry = list_first_entry_or_null(lh, struct l3_entry, list);
+ if (!l3_entry)
+ return 0;
+
+ /*
+ * Octeontx2 has a single AF (one struct rvu) per RVU chip. All queued
+ * entries therefore share the same rvu and the same switch PF below.
+ * Host PF identity is carried per fib_entry (port_id), not by picking
+ * a different switch PF here.
+ */
+ rvu = l3_entry->rvu;
+ swdev_pf = rvu_get_pf(rvu->pdev, rvu->rswitch.pcifunc);
+
+ mutex_lock(&rvu->mbox_lock);
+ req = otx2_mbox_alloc_msg_af2swdev_notify(rvu, swdev_pf);
+ if (!req) {
+ mutex_unlock(&rvu->mbox_lock);
+ return -ENOMEM;
+ }
+
+ dst = &req->entry[0];
+ /*
+ * Batch fib_entry records from multiple host PF notifies into one
+ * af2swdev message. Safe on octeontx2: every l3_entry targets the
+ * same switch PF; egress port is encoded in each fib_entry.port_id.
+ */
+ while ((l3_entry =
+ list_first_entry_or_null(lh,
+ struct l3_entry, list)) != NULL) {
+ entry = l3_entry->entry;
+ cnt = l3_entry->cnt;
+
+ /* af2swdev_notify_req.entry[] holds RVU_SW_L3_BATCH_MAX slots;
+ * stop before copying the next l3_entry when the mbox buffer
+ * would overflow. Leftovers stay on lh and are re-queued.
+ */
+ if (tot_cnt + cnt > RVU_SW_L3_BATCH_MAX)
+ break;
+
+ sz = sizeof(*entry) * cnt;
+
+ memcpy(dst, entry, sz);
+ for (i = 0; i < cnt; i++)
+ dst[i].port_id = l3_entry->port_id;
+ tot_cnt += cnt;
+ dst += cnt;
+
+ list_del_init(&l3_entry->list);
+ kfree(l3_entry);
+ }
+ if (!tot_cnt) {
+ mutex_unlock(&rvu->mbox_lock);
+ return -EINVAL;
+ }
+
+ req->flags = FIB_CMD;
+ req->cnt = tot_cnt;
+
+ rc = otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, swdev_pf);
+ if (rc)
+ otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, swdev_pf);
+
+ mutex_unlock(&rvu->mbox_lock);
+ return rc ? 0 : -EFAULT;
+}
+
+static void sw_l3_offl_work_handler(struct work_struct *work)
+{
+ struct list_head l3lh;
+
+ INIT_LIST_HEAD(&l3lh);
+
+ mutex_lock(&l3_offl_llock);
+ if (list_empty(&l3_offl_lh)) {
+ mutex_unlock(&l3_offl_llock);
+ return;
+ }
+ list_splice_init(&l3_offl_lh, &l3lh);
+ mutex_unlock(&l3_offl_llock);
+
+ if (rvu_sw_l3_offl_rule_push(&l3lh))
+ pr_err("%s: Error to push rules\n", __func__);
+
+ /* rvu_sw_l3_offl_rule_push() may leave entries when a batch is full. */
+ if (!list_empty(&l3lh)) {
+ mutex_lock(&l3_offl_llock);
+ list_splice_tail(&l3lh, &l3_offl_lh);
+ mutex_unlock(&l3_offl_llock);
+ if (sw_l3_offl_wq)
+ queue_delayed_work(sw_l3_offl_wq, &l3_offl_work,
+ msecs_to_jiffies(100));
+ return;
+ }
+
+ mutex_lock(&l3_offl_llock);
+ if (!list_empty(&l3_offl_lh))
+ rvu_sw_l3_queue_work();
+ mutex_unlock(&l3_offl_llock);
+}
int rvu_mbox_handler_fib_notify(struct rvu *rvu,
struct fib_notify_req *req,
struct msg_rsp *rsp)
{
+ struct l3_entry *l3_entry;
+ int sz, rc;
+
+ if (!(rvu->rswitch.flags & RVU_SWITCH_FLAG_FW_READY))
+ return -EAGAIN;
+
+ /* Reject single notifies larger than af2swdev_notify_req.entry[]. */
+ if (!req->cnt || req->cnt > RVU_SW_L3_BATCH_MAX)
+ return -EINVAL;
+
+ sz = req->cnt * sizeof(struct fib_entry);
+
+ l3_entry = kcalloc(1, sizeof(*l3_entry) + sz, GFP_KERNEL);
+ if (!l3_entry)
+ return -ENOMEM;
+
+ l3_entry->port_id = rvu_sw_port_id(rvu, req->hdr.pcifunc);
+ l3_entry->rvu = rvu;
+ l3_entry->cnt = req->cnt;
+ INIT_LIST_HEAD(&l3_entry->list);
+ memcpy(l3_entry->entry, req->entry, sz);
+
+ /* Host PFs on this RVU share one AF and one switch PF offload path. */
+ mutex_lock(&l3_offl_llock);
+ rc = rvu_sw_l3_ensure_wq();
+ if (rc) {
+ mutex_unlock(&l3_offl_llock);
+ kfree(l3_entry);
+ return rc;
+ }
+
+ list_add_tail(&l3_entry->list, &l3_offl_lh);
+ if (sw_l3_offl_wq)
+ rvu_sw_l3_queue_work();
+ mutex_unlock(&l3_offl_llock);
+
return 0;
}
+
+void rvu_sw_l3_shutdown(void)
+{
+ if (!sw_l3_offl_wq)
+ return;
+
+ cancel_delayed_work_sync(&l3_offl_work);
+ destroy_workqueue(sw_l3_offl_wq);
+ sw_l3_offl_wq = NULL;
+
+ mutex_lock(&l3_offl_llock);
+ rvu_sw_l3_drain_list(&l3_offl_lh);
+ mutex_unlock(&l3_offl_llock);
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h
index ac8c4f9ba5ac..153f1415466d 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h
@@ -8,4 +8,5 @@
#ifndef RVU_SW_L3_H
#define RVU_SW_L3_H
+void rvu_sw_l3_shutdown(void);
#endif
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c
index 12ddf8119372..1c1f23d5d136 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c
@@ -4,13 +4,202 @@
* Copyright (C) 2026 Marvell.
*
*/
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/switchdev.h>
+#include <net/netevent.h>
+#include <net/arp.h>
+#include <net/route.h>
+
+#include "../otx2_reg.h"
+#include "../otx2_common.h"
+#include "../otx2_struct.h"
+#include "../cn10k.h"
+#include "sw_nb.h"
#include "sw_fib.h"
+#if IS_ENABLED(CONFIG_OCTEONTX_SWITCH)
+
+#define SW_FIB_BATCH_MAX 16
+
+/*
+ * One switch PF registers notifiers via sw_nb_register(); a second call
+ * returns -EBUSY. A single sw_fib_wq therefore serves the one switchdev
+ * instance on octeontx2, matching the FDB offload path.
+ */
+static DEFINE_SPINLOCK(sw_fib_llock);
+static LIST_HEAD(sw_fib_lh);
+
+static struct workqueue_struct *sw_fib_wq;
+static void sw_fib_work_handler(struct work_struct *work);
+static DECLARE_DELAYED_WORK(sw_fib_work, sw_fib_work_handler);
+
+struct sw_fib_list_entry {
+ struct list_head lh;
+ struct otx2_nic *pf;
+ netdevice_tracker dev_tracker;
+ int cnt;
+ struct fib_entry *entry;
+};
+
+static int sw_fib_notify(struct otx2_nic *pf,
+ int cnt,
+ struct fib_entry *entry)
+{
+ struct fib_notify_req *req;
+ int rc;
+
+ if (cnt > SW_FIB_BATCH_MAX)
+ return -EINVAL;
+
+ mutex_lock(&pf->mbox.lock);
+ req = otx2_mbox_alloc_msg_fib_notify(&pf->mbox);
+ if (!req) {
+ rc = -ENOMEM;
+ goto out;
+ }
+
+ req->cnt = cnt;
+ memcpy(req->entry, entry, sizeof(*entry) * cnt);
+
+ rc = otx2_sync_mbox_msg(&pf->mbox);
+out:
+ mutex_unlock(&pf->mbox.lock);
+ return rc;
+}
+
+static void sw_fib_work_handler(struct work_struct *work)
+{
+ struct sw_fib_list_entry *lentry;
+ LIST_HEAD(tlist);
+
+ spin_lock_bh(&sw_fib_llock);
+ list_splice_init(&sw_fib_lh, &tlist);
+ spin_unlock_bh(&sw_fib_llock);
+
+ while ((lentry =
+ list_first_entry_or_null(&tlist,
+ struct sw_fib_list_entry, lh)) != NULL) {
+ list_del_init(&lentry->lh);
+ if (sw_fib_notify(lentry->pf, lentry->cnt, lentry->entry)) {
+ netdev_err(lentry->pf->netdev,
+ "Failed to notify FIB update to AF, will retry\n");
+ spin_lock_bh(&sw_fib_llock);
+ if (sw_fib_wq) {
+ list_add_tail(&lentry->lh, &sw_fib_lh);
+ queue_delayed_work(sw_fib_wq, &sw_fib_work,
+ msecs_to_jiffies(100));
+ spin_unlock_bh(&sw_fib_llock);
+ continue;
+ }
+ spin_unlock_bh(&sw_fib_llock);
+ netdev_put(lentry->pf->netdev, &lentry->dev_tracker);
+ kfree(lentry->entry);
+ kfree(lentry);
+ continue;
+ }
+ netdev_put(lentry->pf->netdev, &lentry->dev_tracker);
+ kfree(lentry->entry);
+ kfree(lentry);
+ }
+
+ spin_lock_bh(&sw_fib_llock);
+ if (!list_empty(&sw_fib_lh) && sw_fib_wq)
+ queue_delayed_work(sw_fib_wq, &sw_fib_work,
+ msecs_to_jiffies(10));
+ spin_unlock_bh(&sw_fib_llock);
+}
+
+int sw_fib_add_to_list(struct net_device *dev,
+ struct fib_entry *entry, int cnt)
+{
+ struct otx2_nic *pf = netdev_priv(dev);
+ struct sw_fib_list_entry *lentry;
+ struct workqueue_struct *wq;
+
+ if (cnt <= 0 || cnt > SW_FIB_BATCH_MAX) {
+ kfree(entry);
+ return -EINVAL;
+ }
+
+ spin_lock_bh(&sw_fib_llock);
+ if (!sw_fib_wq) {
+ spin_unlock_bh(&sw_fib_llock);
+ kfree(entry);
+ return -EINVAL;
+ }
+ spin_unlock_bh(&sw_fib_llock);
+
+ lentry = kcalloc(1, sizeof(*lentry), GFP_ATOMIC);
+ if (!lentry) {
+ kfree(entry);
+ return -ENOMEM;
+ }
+
+ lentry->pf = pf;
+ lentry->cnt = cnt;
+ lentry->entry = entry;
+ INIT_LIST_HEAD(&lentry->lh);
+ netdev_hold(dev, &lentry->dev_tracker, GFP_ATOMIC);
+
+ spin_lock_bh(&sw_fib_llock);
+ wq = sw_fib_wq;
+ if (wq) {
+ list_add_tail(&lentry->lh, &sw_fib_lh);
+ queue_delayed_work(wq, &sw_fib_work,
+ msecs_to_jiffies(10));
+ }
+ spin_unlock_bh(&sw_fib_llock);
+
+ if (!wq) {
+ netdev_put(dev, &lentry->dev_tracker);
+ kfree(lentry);
+ kfree(entry);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
int sw_fib_init(void)
{
+ sw_fib_wq = alloc_workqueue("sw_pf_fib_wq", 0, 0);
+ if (!sw_fib_wq)
+ return -ENOMEM;
+
return 0;
}
void sw_fib_deinit(void)
{
+ struct sw_fib_list_entry *lentry;
+ struct workqueue_struct *wq;
+ LIST_HEAD(tlist);
+
+ spin_lock_bh(&sw_fib_llock);
+ wq = sw_fib_wq;
+ sw_fib_wq = NULL;
+ spin_unlock_bh(&sw_fib_llock);
+
+ if (!wq)
+ return;
+
+ cancel_delayed_work_sync(&sw_fib_work);
+ destroy_workqueue(wq);
+
+ spin_lock_bh(&sw_fib_llock);
+ list_splice_init(&sw_fib_lh, &tlist);
+ spin_unlock_bh(&sw_fib_llock);
+
+ while ((lentry =
+ list_first_entry_or_null(&tlist,
+ struct sw_fib_list_entry, lh)) != NULL) {
+ list_del_init(&lentry->lh);
+ netdev_put(lentry->pf->netdev, &lentry->dev_tracker);
+ kfree(lentry->entry);
+ kfree(lentry);
+ }
}
+
+#endif /* CONFIG_OCTEONTX_SWITCH */
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h
index 9b72e95f2dd3..2e0e7a80c40c 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h
@@ -9,10 +9,20 @@
#include <linux/kconfig.h>
+struct fib_entry;
+struct net_device;
+
#if IS_ENABLED(CONFIG_OCTEONTX_SWITCH)
+int sw_fib_add_to_list(struct net_device *dev,
+ struct fib_entry *entry, int cnt);
void sw_fib_deinit(void);
int sw_fib_init(void);
#else
+static inline int sw_fib_add_to_list(struct net_device *dev,
+ struct fib_entry *entry, int cnt)
+{
+ return 0;
+}
static inline void sw_fib_deinit(void) {}
static inline int sw_fib_init(void) { return 0; }
#endif
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c
index 8aa357e9db21..971af268ae93 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c
@@ -140,6 +140,7 @@ static int sw_nb_fdb_event(struct notifier_block *unused,
{
struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
struct switchdev_notifier_fdb_info *fdb_info = ptr;
+ int rc = 0;
if (!sw_nb_is_valid_dev(dev))
return NOTIFY_DONE;
@@ -148,19 +149,22 @@ static int sw_nb_fdb_event(struct notifier_block *unused,
case SWITCHDEV_FDB_ADD_TO_DEVICE:
if (fdb_info->is_local)
break;
- sw_fdb_add_to_list(dev, (u8 *)fdb_info->addr, true);
+ rc = sw_fdb_add_to_list(dev, (u8 *)fdb_info->addr, true);
break;
case SWITCHDEV_FDB_DEL_TO_DEVICE:
if (fdb_info->is_local)
break;
- sw_fdb_add_to_list(dev, (u8 *)fdb_info->addr, false);
+ rc = sw_fdb_add_to_list(dev, (u8 *)fdb_info->addr, false);
break;
default:
return NOTIFY_DONE;
}
+ if (rc)
+ netdev_err(dev, "%s: Error to add to list\n", __func__);
+
return NOTIFY_DONE;
}
@@ -329,8 +333,8 @@ static int sw_nb_netdev_event(struct notifier_block *unused,
if (idev)
sw_nb_v4_netdev_event(unused, event, ptr);
-#if IS_ENABLED(CONFIG_IPV6)
i6dev = __in6_dev_get(dev);
+#if IS_ENABLED(CONFIG_IPV6)
if (i6dev)
sw_nb_v6_netdev_event(unused, event, ptr);
#endif
@@ -407,6 +411,7 @@ int sw_nb_register(struct net_device *netdev)
{
int err;
+ /* One switch PF / switchdev instance registers system-wide notifiers. */
if (sw_nb_registered)
return -EBUSY;
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v4.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v4.c
index 0e7006e507fd..c1e50bb0fbd3 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v4.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v4.c
@@ -38,6 +38,9 @@ int sw_nb_v4_netdev_event(struct notifier_block *unused,
if (!idev || !idev->ifa_list)
return NOTIFY_DONE;
+ if (!sw_nb_is_valid_dev(dev))
+ return NOTIFY_DONE;
+
ifa = rtnl_dereference(idev->ifa_list);
entry = kcalloc(1, sizeof(*entry), GFP_KERNEL);
@@ -73,7 +76,7 @@ int sw_nb_v4_netdev_event(struct notifier_block *unused,
netdev_dbg(dev, "%s: pushing netdev event from HOST interface address %pI4, %pM, dev=%s\n",
__func__, &entry->dst, entry->mac, dev->name);
- kfree(entry);
+ sw_fib_add_to_list(pf_dev, entry, 1);
return NOTIFY_DONE;
}
@@ -136,7 +139,7 @@ int sw_nb_v4_inetaddr_event(struct notifier_block *nb,
netdev_dbg(dev, "%s: pushing inetaddr event from HOST interface address %pI4, %pM, %s\n",
__func__, &entry->dst, entry->mac, dev->name);
- kfree(entry);
+ sw_fib_add_to_list(pf_dev, entry, 1);
return NOTIFY_DONE;
}
@@ -144,16 +147,18 @@ int sw_nb_v4_fib_event(struct notifier_block *nb,
unsigned long event, void *ptr)
{
struct fib_entry_notifier_info *fen_info = ptr;
- struct net_device *dev, *pf_dev = NULL;
- struct fib_entry *entries, *iter;
+ struct net_device *host_pf_dev = NULL;
struct netdev_hw_addr *dev_addr;
+ struct net_device *nh_pf_dev;
struct neighbour *neigh;
+ struct fib_entry *entry;
+ struct net_device *dev;
struct fib_nh *fib_nh;
struct fib_info *fi;
struct otx2_nic *pf;
__be32 *haddr;
int hcnt = 0;
- int cnt, i;
+ int i, cnt;
/* Process only UNICAST routes add or del */
if (fen_info->type != RTN_UNICAST)
@@ -173,17 +178,10 @@ int sw_nb_v4_fib_event(struct notifier_block *nb,
return NOTIFY_DONE;
}
- entries = kcalloc(fi->fib_nhs, sizeof(*entries), GFP_ATOMIC);
- if (!entries)
- return NOTIFY_DONE;
-
haddr = kcalloc(fi->fib_nhs, sizeof(*haddr), GFP_ATOMIC);
- if (!haddr) {
- kfree(entries);
+ if (!haddr)
return NOTIFY_DONE;
- }
- iter = entries;
fib_nh = fi->fib_nh;
for (i = 0; i < fi->fib_nhs; i++, fib_nh++) {
dev = fib_nh->fib_nh_dev;
@@ -197,37 +195,39 @@ int sw_nb_v4_fib_event(struct notifier_block *nb,
if (!sw_nb_is_valid_dev(dev))
continue;
- iter->cmd = sw_nb_fib_event_to_otx2_event(event, dev);
- iter->dst = (__force __be32)fen_info->dst;
- iter->dst_len = fen_info->dst_len;
- iter->gw = fib_nh->fib_nh_gw4;
+ nh_pf_dev = sw_nb_resolve_pf_dev(dev);
+ if (!nh_pf_dev)
+ continue;
- netdev_dbg(dev, "%s: FIB route Rule cmd=%llu dst=%pI4 dst_len=%u gw=%pI4\n",
- __func__, iter->cmd, &iter->dst, iter->dst_len, &iter->gw);
+ entry = kcalloc(1, sizeof(*entry), GFP_ATOMIC);
+ if (!entry)
+ break;
- pf_dev = sw_nb_resolve_pf_dev(dev);
- if (!pf_dev) {
- iter++;
- continue;
- }
+ entry->cmd = sw_nb_fib_event_to_otx2_event(event, dev);
+ entry->dst = (__force __be32)fen_info->dst;
+ entry->dst_len = fen_info->dst_len;
+ entry->gw = fib_nh->fib_nh_gw4;
if (netif_is_bridge_master(dev)) {
- iter->bridge = 1;
+ entry->bridge = 1;
} else if (is_vlan_dev(dev)) {
- iter->vlan_valid = 1;
- iter->vlan_tag = cpu_to_be16(vlan_dev_vlan_id(dev));
+ entry->vlan_valid = 1;
+ entry->vlan_tag = cpu_to_be16(vlan_dev_vlan_id(dev));
}
- pf = netdev_priv(pf_dev);
- iter->port_id = pf->pcifunc;
+ pf = netdev_priv(nh_pf_dev);
+ entry->port_id = pf->pcifunc;
if (!fib_nh->fib_nh_gw4) {
- if (iter->dst || iter->dst_len)
- iter++;
-
+ if (!entry->dst && !entry->dst_len) {
+ kfree(entry);
+ continue;
+ }
+ sw_fib_add_to_list(nh_pf_dev, entry, 1);
continue;
}
- iter->gw_valid = 1;
+
+ entry->gw_valid = 1;
if (fib_nh->nh_saddr)
haddr[hcnt++] = fib_nh->nh_saddr;
@@ -236,61 +236,63 @@ int sw_nb_v4_fib_event(struct notifier_block *nb,
neigh = ip_neigh_gw4(fib_nh->fib_nh_dev, fib_nh->fib_nh_gw4);
if (!neigh) {
rcu_read_unlock();
- iter++;
+ kfree(entry);
continue;
}
if (is_valid_ether_addr(neigh->ha)) {
- iter->mac_valid = 1;
- neigh_ha_snapshot(iter->mac, neigh, fib_nh->fib_nh_dev);
+ entry->mac_valid = 1;
+ neigh_ha_snapshot(entry->mac, neigh, fib_nh->fib_nh_dev);
}
-
- iter++;
rcu_read_unlock();
- }
- cnt = iter - entries;
- if (!cnt) {
- kfree(entries);
- kfree(haddr);
- return NOTIFY_DONE;
+ netdev_dbg(dev, "%s: FIB route Rule cmd=%llu dst=%pI4 dst_len=%u gw=%pI4\n",
+ __func__, entry->cmd, &entry->dst, entry->dst_len,
+ &entry->gw);
+ sw_fib_add_to_list(nh_pf_dev, entry, 1);
}
- if (pf_dev)
- netdev_dbg(pf_dev, "pf_dev is %s cnt=%d\n", pf_dev->name, cnt);
- kfree(entries);
-
if (!hcnt) {
kfree(haddr);
return NOTIFY_DONE;
}
- entries = kcalloc(hcnt, sizeof(*entries), GFP_ATOMIC);
- if (!entries) {
- kfree(haddr);
- return NOTIFY_DONE;
- }
+ for (i = 0; i < hcnt; i++) {
+ fib_nh = fi->fib_nh;
+ for (cnt = 0; cnt < fi->fib_nhs; cnt++, fib_nh++) {
+ if (fib_nh->nh_saddr == haddr[i]) {
+ host_pf_dev = sw_nb_resolve_pf_dev(fib_nh->fib_nh_dev);
+ break;
+ }
+ }
+
+ if (!host_pf_dev)
+ continue;
- iter = entries;
+ entry = kcalloc(1, sizeof(*entry), GFP_ATOMIC);
+ if (!entry)
+ break;
- for (i = 0; i < hcnt; i++, iter++) {
- iter->cmd = sw_nb_fib_event_to_otx2_event(event, pf_dev);
- iter->dst = haddr[i];
- iter->dst_len = 32;
- iter->mac_valid = 1;
- iter->host = 1;
- iter->port_id = pf->pcifunc;
+ pf = netdev_priv(host_pf_dev);
+ entry->cmd = sw_nb_fib_event_to_otx2_event(event, host_pf_dev);
+ entry->dst = haddr[i];
+ entry->dst_len = 32;
+ entry->mac_valid = 1;
+ entry->host = 1;
+ entry->port_id = pf->pcifunc;
- for_each_dev_addr(pf_dev, dev_addr) {
- ether_addr_copy(iter->mac, dev_addr->addr);
+ for_each_dev_addr(host_pf_dev, dev_addr) {
+ ether_addr_copy(entry->mac, dev_addr->addr);
break;
}
- netdev_dbg(pf_dev, "%s: FIB host Rule cmd=%llu dst=%pI4 dst_len=%u gw=%pI4 %s\n",
- __func__, iter->cmd, &iter->dst, iter->dst_len, &iter->gw,
- pf_dev->name);
+ netdev_dbg(host_pf_dev,
+ "%s: FIB host Rule cmd=%llu dst=%pI4 dst_len=%u gw=%pI4 %s\n",
+ __func__, entry->cmd, &entry->dst, entry->dst_len,
+ &entry->gw, host_pf_dev->name);
+ sw_fib_add_to_list(host_pf_dev, entry, 1);
}
- kfree(entries);
+
kfree(haddr);
return NOTIFY_DONE;
}
@@ -306,6 +308,9 @@ int sw_nb_net_v4_neigh_update(struct notifier_block *nb,
if (n->tbl != &arp_tbl)
return NOTIFY_DONE;
+ if (!sw_nb_is_valid_dev(n->dev))
+ return NOTIFY_DONE;
+
entry = kcalloc(1, sizeof(*entry), GFP_ATOMIC);
if (!entry)
return NOTIFY_DONE;
@@ -333,6 +338,6 @@ int sw_nb_net_v4_neigh_update(struct notifier_block *nb,
pf = netdev_priv(pf_dev);
entry->port_id = pf->pcifunc;
- kfree(entry);
+ sw_fib_add_to_list(pf_dev, entry, 1);
return NOTIFY_DONE;
}
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v6.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v6.c
index 0d29c5526df8..0d94c33c53a6 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v6.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v6.c
@@ -45,6 +45,9 @@ int sw_nb_v6_netdev_event(struct notifier_block *unused,
if (!i6dev)
return NOTIFY_DONE;
+ if (!sw_nb_is_valid_dev(dev))
+ return NOTIFY_DONE;
+
rcu_read_lock();
ifp = list_first_entry_or_null(&i6dev->addr_list,
struct inet6_ifaddr, if_list);
@@ -89,15 +92,15 @@ int sw_nb_v6_netdev_event(struct notifier_block *unused,
netdev_dbg(dev, "netdev event addr=%pI6c plen=%u mac=%pM\n",
&addr, prefix_len, entry->mac);
- kfree(entry);
+ sw_fib_add_to_list(pf_dev, entry, 1);
return NOTIFY_DONE;
}
int sw_nb_v6_fib_event(struct notifier_block *nb,
unsigned long event, void *ptr)
{
- struct fib6_entry_notifier_info *f6_eni;
struct fib_notifier_info *info = ptr;
+ struct fib6_entry_notifier_info *f6_eni;
struct net_device *fib_dev, *pf_dev;
struct fib_entry *entry;
struct fib6_info *f6i;
@@ -174,8 +177,8 @@ int sw_nb_v6_fib_event(struct notifier_block *nb,
netdev_dbg(fib_dev, "fib found MAC=%pM\n", entry->mac);
}
+ sw_fib_add_to_list(pf_dev, entry, 1);
rcu_read_unlock();
- kfree(entry);
return NOTIFY_DONE;
}
@@ -216,9 +219,10 @@ int sw_nb_net_v6_neigh_update(struct notifier_block *nb,
entry->mac_valid = 1;
entry->port_id = pf->pcifunc;
+ sw_fib_add_to_list(pf_dev, entry, 1);
+
netdev_dbg(n->dev, "v6 neigh update %pI6c mac=%pM plen=%u\n",
n->primary_key, entry->mac, n->tbl->key_len * 8);
- kfree(entry);
return NOTIFY_DONE;
}
@@ -274,9 +278,10 @@ int sw_nb_v6_inetaddr_event(struct notifier_block *nb,
break;
}
+ sw_fib_add_to_list(pf_dev, entry, 1);
+
netdev_dbg(dev, "inetaddr addr=%pI6c len=%u %pM\n",
&ifa6->addr, ifa6->prefix_len, entry->mac);
- kfree(entry);
return NOTIFY_DONE;
}
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v6.h b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v6.h
index f73efc98c311..78c0df5eb880 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v6.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb_v6.h
@@ -7,6 +7,9 @@
#ifndef SW_NB_V6_H_
#define SW_NB_V6_H_
+#include <linux/kconfig.h>
+
+#if IS_ENABLED(CONFIG_IPV6)
int sw_nb_v6_fib_event(struct notifier_block *nb,
unsigned long event, void *ptr);
@@ -18,4 +21,30 @@ int sw_nb_v6_inetaddr_event(struct notifier_block *nb,
int sw_nb_v6_netdev_event(struct notifier_block *unused,
unsigned long event, void *ptr);
-#endif // SW_NB_V6_H__
+#else
+static inline int sw_nb_v6_fib_event(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ return NOTIFY_DONE;
+}
+
+static inline int sw_nb_net_v6_neigh_update(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ return NOTIFY_DONE;
+}
+
+static inline int sw_nb_v6_inetaddr_event(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ return NOTIFY_DONE;
+}
+
+static inline int sw_nb_v6_netdev_event(struct notifier_block *unused,
+ unsigned long event, void *ptr)
+{
+ return NOTIFY_DONE;
+}
+#endif
+
+#endif /* SW_NB_V6_H_ */
--
2.43.0
^ permalink raw reply related
* [PATCH v3 net-next 7/9] octeontx2: switch: plumb bridge FDB updates through AF and switchdev
From: Ratheesh Kannoth @ 2026-07-14 1:53 UTC (permalink / raw)
To: linux-kernel, netdev
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, sgoutham,
Ratheesh Kannoth
In-Reply-To: <20260714015331.1801922-1-rkannoth@marvell.com>
Handle switchdev FDB add and delete notifications on the PF by queuing
work that sends fdb_notify mailbox messages to the AF. The AF queues
those updates and pushes L2 rules toward the switchdev image with
af2swdev notify messages when firmware is ready.
Teach the AF swdev2af path to initialize L2 offload workqueues on
firmware up/down and to accept refresh requests that enqueue FDB
entries for AF to PF mailbox delivery. Add an AF to PF (and VF) upstream
message for FDB refresh, handle it in the VF driver, and treat it like
the CGX link event when acknowledging mailbox completion in the AF.
On refresh, invoke the switchdev notifier so the host bridge can learn
the updated FDB entry.
Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
---
.../net/ethernet/marvell/octeontx2/af/mbox.h | 2 +
.../net/ethernet/marvell/octeontx2/af/rvu.c | 2 +
.../marvell/octeontx2/af/switch/rvu_sw.c | 51 +-
.../marvell/octeontx2/af/switch/rvu_sw.h | 1 +
.../marvell/octeontx2/af/switch/rvu_sw_l2.c | 486 ++++++++++++++++++
.../marvell/octeontx2/af/switch/rvu_sw_l2.h | 3 +
.../ethernet/marvell/octeontx2/nic/otx2_pf.c | 2 +
.../ethernet/marvell/octeontx2/nic/otx2_vf.c | 44 ++
.../marvell/octeontx2/nic/switch/sw_fdb.c | 218 ++++++++
.../marvell/octeontx2/nic/switch/sw_fdb.h | 1 +
.../marvell/octeontx2/nic/switch/sw_nb.c | 2 +
.../marvell/octeontx2/nic/switch/sw_nb.h | 8 +-
12 files changed, 815 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index bf8edab569b1..e8cc7b68ad75 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -1996,6 +1996,7 @@ struct af2pf_fdb_refresh_req {
struct mbox_msghdr hdr;
u16 pcifunc;
u8 mac[6];
+ u64 flags;
};
struct iface_info {
@@ -2035,6 +2036,7 @@ struct fl_info {
struct swdev2af_notify_req {
struct mbox_msghdr hdr;
u64 msg_type;
+/* Mutually exclusive message selectors (not a combinable bitmask). */
#define SWDEV2AF_MSG_TYPE_FW_STATUS BIT_ULL(0)
#define SWDEV2AF_MSG_TYPE_REFRESH_FDB BIT_ULL(1)
#define SWDEV2AF_MSG_TYPE_REFRESH_FL BIT_ULL(2)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
index 532c2b69fb85..217ce85033ac 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
@@ -23,6 +23,7 @@
#include "cn20k/reg.h"
#include "cn20k/api.h"
#include "cn20k/npc.h"
+#include "switch/rvu_sw.h"
#define DRV_NAME "rvu_af"
#define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver"
@@ -3859,6 +3860,7 @@ static void rvu_remove(struct pci_dev *pdev)
rvu_cgx_exit(rvu);
rvu_fwdata_exit(rvu);
rvu_mcs_exit(rvu);
+ rvu_sw_shutdown();
rvu_mbox_destroy(&rvu->afpf_wq_info);
rvu_disable_sriov(rvu);
rvu_reset_all_blocks(rvu);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
index 403d57870efe..b9cd7c7524b9 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c
@@ -9,6 +9,8 @@
#include "rvu.h"
#include "rvu_sw.h"
+#include "rvu_sw_l2.h"
+#include "rvu_sw_fl.h"
u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc)
{
@@ -26,9 +28,56 @@ u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc)
FIELD_PREP(GENMASK_ULL(15, 0), pcifunc);
}
+static bool rvu_sw_swdev2af_msg_valid(u64 msg_type)
+{
+ return msg_type == SWDEV2AF_MSG_TYPE_FW_STATUS ||
+ msg_type == SWDEV2AF_MSG_TYPE_REFRESH_FDB ||
+ msg_type == SWDEV2AF_MSG_TYPE_REFRESH_FL;
+}
+
+static int rvu_sw_swdev2af_sender_check(struct rvu *rvu,
+ struct swdev2af_notify_req *req,
+ u64 msg_type)
+{
+ u16 sender = req->hdr.pcifunc;
+
+ if (!rvu_sw_swdev2af_msg_valid(msg_type))
+ return -EINVAL;
+
+ if (!rvu_is_switch_pcifunc(rvu, sender))
+ return -EPERM;
+
+ return 0;
+}
+
int rvu_mbox_handler_swdev2af_notify(struct rvu *rvu,
struct swdev2af_notify_req *req,
struct msg_rsp *rsp)
{
- return 0;
+ int rc;
+
+ rc = rvu_sw_swdev2af_sender_check(rvu, req, req->msg_type);
+ if (rc)
+ return rc;
+
+ switch (req->msg_type) {
+ case SWDEV2AF_MSG_TYPE_FW_STATUS:
+ rc = rvu_sw_l2_init_offl_wq(rvu, req->hdr.pcifunc, req->fw_up);
+ break;
+
+ case SWDEV2AF_MSG_TYPE_REFRESH_FDB:
+ rc = rvu_sw_l2_fdb_list_entry_add(rvu, req->pcifunc, req->mac);
+ break;
+
+ default:
+ rc = -EOPNOTSUPP;
+ break;
+ }
+
+ return rc;
+}
+
+void rvu_sw_shutdown(void)
+{
+ rvu_sw_l2_shutdown();
}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h
index e9ad32c84576..a0cb2a9ce7ab 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h
@@ -12,5 +12,6 @@
#define RVU_SW_INVALID_PORT_ID ((u32)~0U)
u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc);
+void rvu_sw_shutdown(void);
#endif
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c
index 5f805bfa81ed..f61b2d15768b 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c
@@ -4,11 +4,497 @@
* Copyright (C) 2026 Marvell.
*
*/
+
+#include <linux/bitfield.h>
#include "rvu.h"
+#include "rvu_sw.h"
+#include "rvu_sw_l2.h"
+
+#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
+static struct _req_type __maybe_unused \
+*otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \
+{ \
+ struct _req_type *req; \
+ \
+ req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
+ &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
+ sizeof(struct _rsp_type)); \
+ if (!req) \
+ return NULL; \
+ req->hdr.sig = OTX2_MBOX_REQ_SIG; \
+ req->hdr.id = _id; \
+ return req; \
+}
+MBOX_UP_AF2SWDEV_MESSAGES
+MBOX_UP_AF2PF_FDB_REFRESH_MESSAGES
+#undef M
+
+#define RVU_SW_L2_LIST_MAX 4096
+
+struct l2_entry {
+ struct list_head list;
+ u64 flags;
+ u32 port_id;
+ u8 mac[ETH_ALEN];
+};
+
+static DEFINE_MUTEX(l2_offl_list_lock);
+static LIST_HEAD(l2_offl_lh);
+static atomic_t l2_offl_list_cnt = ATOMIC_INIT(0);
+
+static DEFINE_MUTEX(fdb_refresh_list_lock);
+static LIST_HEAD(fdb_refresh_lh);
+static atomic_t fdb_refresh_list_cnt = ATOMIC_INIT(0);
+
+struct rvu_sw_l2_work {
+ struct rvu *rvu;
+ struct work_struct work;
+};
+
+/* Work queue for switchdev message handling. There is only
+ * one switch HW per SoC, so one instance of each type of
+ * workqueue is enough.
+ */
+static struct rvu_sw_l2_work l2_offl_work;
+static struct workqueue_struct *rvu_sw_l2_offl_wq;
+
+static struct rvu_sw_l2_work fdb_refresh_work;
+static struct workqueue_struct *fdb_refresh_wq;
+
+static bool fw_is_up;
+static DEFINE_SPINLOCK(rvu_sw_l2_state_lock);
+
+static void rvu_sw_l2_list_cnt_warn(struct device *dev, atomic_t *cnt,
+ const char *name)
+{
+ int n = atomic_read(cnt);
+
+ if (n < 0)
+ dev_warn(dev, "L2 %s list count underflow: %d\n", name, n);
+ else if (n > RVU_SW_L2_LIST_MAX)
+ dev_warn(dev, "L2 %s list count overflow: %d (max %d)\n",
+ name, n, RVU_SW_L2_LIST_MAX);
+}
+
+static void rvu_sw_l2_list_cnt_inc(struct device *dev, atomic_t *cnt,
+ const char *name)
+{
+ atomic_inc(cnt);
+ rvu_sw_l2_list_cnt_warn(dev, cnt, name);
+}
+
+static void rvu_sw_l2_list_cnt_dec(struct device *dev, atomic_t *cnt,
+ const char *name)
+{
+ atomic_dec(cnt);
+ rvu_sw_l2_list_cnt_warn(dev, cnt, name);
+}
+
+static void rvu_sw_l2_destroy_wqs(struct rvu *rvu)
+{
+ struct workqueue_struct *offl_wq, *refresh_wq;
+ struct l2_entry *entry;
+
+ spin_lock_bh(&rvu_sw_l2_state_lock);
+ rvu->rswitch.flags &= ~RVU_SWITCH_FLAG_FW_READY;
+ rvu->rswitch.pcifunc = 0;
+ fw_is_up = false;
+ offl_wq = rvu_sw_l2_offl_wq;
+ refresh_wq = fdb_refresh_wq;
+ rvu_sw_l2_offl_wq = NULL;
+ fdb_refresh_wq = NULL;
+ spin_unlock_bh(&rvu_sw_l2_state_lock);
+
+ if (refresh_wq) {
+ cancel_work_sync(&fdb_refresh_work.work);
+ destroy_workqueue(refresh_wq);
+
+ mutex_lock(&fdb_refresh_list_lock);
+ rvu_sw_l2_list_cnt_warn(rvu->dev, &fdb_refresh_list_cnt,
+ "fdb refresh");
+ while (1) {
+ entry = list_first_entry_or_null(&fdb_refresh_lh,
+ struct l2_entry, list);
+ if (!entry)
+ break;
+
+ list_del_init(&entry->list);
+ kfree(entry);
+ }
+ atomic_set(&fdb_refresh_list_cnt, 0);
+ mutex_unlock(&fdb_refresh_list_lock);
+ }
+
+ if (offl_wq) {
+ cancel_work_sync(&l2_offl_work.work);
+ destroy_workqueue(offl_wq);
+
+ mutex_lock(&l2_offl_list_lock);
+ rvu_sw_l2_list_cnt_warn(rvu->dev, &l2_offl_list_cnt, "offload");
+ while (1) {
+ entry = list_first_entry_or_null(&l2_offl_lh,
+ struct l2_entry, list);
+ if (!entry)
+ break;
+
+ list_del_init(&entry->list);
+ kfree(entry);
+ }
+ atomic_set(&l2_offl_list_cnt, 0);
+ mutex_unlock(&l2_offl_list_lock);
+ }
+}
+
+/* High-frequency link state transitions or aggressive FDB
+ * aging intervals can induce rapid fdb churn. To prevent
+ * thrashing, inhibit hardware offloading of these transient
+ * forwarding states to the switching ASIC. When processing an ADD,
+ * drop a queued DELETE for the same MAC that has not yet been sent to
+ * hardware; the ADD reflects the desired final state and supersedes it.
+ */
+static void rvu_sw_l2_offl_drop_pending_del(u8 *mac)
+{
+ struct l2_entry *entry, *tmp;
+
+ mutex_lock(&l2_offl_list_lock);
+ list_for_each_entry_safe(entry, tmp, &l2_offl_lh, list) {
+ if (!ether_addr_equal(mac, entry->mac))
+ continue;
+
+ if (!(entry->flags & FDB_DEL))
+ continue;
+
+ list_del_init(&entry->list);
+ rvu_sw_l2_list_cnt_dec(l2_offl_work.rvu->dev, &l2_offl_list_cnt,
+ "offload");
+ kfree(entry);
+ break;
+ }
+ mutex_unlock(&l2_offl_list_lock);
+}
+
+static int rvu_sw_l2_offl_rule_push(struct rvu *rvu, struct l2_entry *l2_entry)
+{
+ struct af2swdev_notify_req *req;
+ int swdev_pf;
+
+ swdev_pf = rvu_get_pf(rvu->pdev, rvu->rswitch.pcifunc);
+
+ mutex_lock(&rvu->mbox_lock);
+ req = otx2_mbox_alloc_msg_af2swdev_notify(rvu, swdev_pf);
+ if (!req) {
+ mutex_unlock(&rvu->mbox_lock);
+ return -ENOMEM;
+ }
+
+ ether_addr_copy(req->mac, l2_entry->mac);
+ req->flags = l2_entry->flags;
+ req->port_id = l2_entry->port_id;
+
+ otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, swdev_pf);
+ otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, swdev_pf);
+
+ mutex_unlock(&rvu->mbox_lock);
+ return 0;
+}
+
+static int rvu_sw_l2_fdb_refresh_send(struct rvu *rvu, u16 pcifunc, u8 *mac)
+{
+ struct af2pf_fdb_refresh_req *req;
+ int pf, vidx;
+
+ if (!is_pf_func_valid(rvu, pcifunc))
+ return -EINVAL;
+
+ pf = rvu_get_pf(rvu->pdev, pcifunc);
+
+ mutex_lock(&rvu->mbox_lock);
+
+ if (pf) {
+ if (pf >= rvu->afpf_wq_info.mbox_up.ndevs) {
+ mutex_unlock(&rvu->mbox_lock);
+ return -EINVAL;
+ }
+
+ req = otx2_mbox_alloc_msg_af2pf_fdb_refresh(rvu, pf);
+ if (!req) {
+ mutex_unlock(&rvu->mbox_lock);
+ return -ENOMEM;
+ }
+
+ req->hdr.pcifunc = pcifunc;
+ ether_addr_copy(req->mac, mac);
+ req->pcifunc = pcifunc;
+ req->flags = FDB_ADD;
+
+ otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pf);
+ otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pf);
+ } else {
+ vidx = pcifunc - 1;
+
+ if (vidx < 0 || vidx >= rvu->afvf_wq_info.mbox_up.ndevs) {
+ mutex_unlock(&rvu->mbox_lock);
+ return -EINVAL;
+ }
+
+ req = (struct af2pf_fdb_refresh_req *)
+ otx2_mbox_alloc_msg_rsp(&rvu->afvf_wq_info.mbox_up, vidx,
+ sizeof(*req), sizeof(struct msg_rsp));
+ if (!req) {
+ mutex_unlock(&rvu->mbox_lock);
+ return -ENOMEM;
+ }
+ req->hdr.sig = OTX2_MBOX_REQ_SIG;
+ req->hdr.id = MBOX_MSG_AF2PF_FDB_REFRESH;
+
+ req->hdr.pcifunc = pcifunc;
+ ether_addr_copy(req->mac, mac);
+ req->pcifunc = pcifunc;
+ req->flags = FDB_ADD;
+
+ otx2_mbox_wait_for_zero(&rvu->afvf_wq_info.mbox_up, vidx);
+ otx2_mbox_msg_send_up(&rvu->afvf_wq_info.mbox_up, vidx);
+ }
+
+ mutex_unlock(&rvu->mbox_lock);
+
+ return 0;
+}
+
+static void rvu_sw_l2_fdb_refresh_wq_handler(struct work_struct *work)
+{
+ struct rvu_sw_l2_work *fdb_work;
+ struct l2_entry *l2_entry;
+
+ fdb_work = container_of(work, struct rvu_sw_l2_work, work);
+
+ while (1) {
+ mutex_lock(&fdb_refresh_list_lock);
+ l2_entry = list_first_entry_or_null(&fdb_refresh_lh,
+ struct l2_entry, list);
+ if (!l2_entry) {
+ mutex_unlock(&fdb_refresh_list_lock);
+ return;
+ }
+
+ list_del_init(&l2_entry->list);
+ rvu_sw_l2_list_cnt_dec(fdb_work->rvu->dev, &fdb_refresh_list_cnt,
+ "fdb refresh");
+ mutex_unlock(&fdb_refresh_list_lock);
+
+ rvu_sw_l2_fdb_refresh_send(fdb_work->rvu, l2_entry->port_id,
+ l2_entry->mac);
+ kfree(l2_entry);
+ }
+}
+
+static void rvu_sw_l2_offl_rule_wq_handler(struct work_struct *work)
+{
+ struct rvu_sw_l2_work *offl_work;
+ struct l2_entry *l2_entry;
+ int budget = 16;
+ bool add_fdb;
+
+ offl_work = container_of(work, struct rvu_sw_l2_work, work);
+
+ while (budget--) {
+ mutex_lock(&l2_offl_list_lock);
+ l2_entry = list_first_entry_or_null(&l2_offl_lh, struct l2_entry, list);
+ if (!l2_entry) {
+ mutex_unlock(&l2_offl_list_lock);
+ return;
+ }
+
+ list_del_init(&l2_entry->list);
+ rvu_sw_l2_list_cnt_dec(offl_work->rvu->dev, &l2_offl_list_cnt,
+ "offload");
+ mutex_unlock(&l2_offl_list_lock);
+
+ add_fdb = !!(l2_entry->flags & FDB_ADD);
+
+ if (add_fdb)
+ rvu_sw_l2_offl_drop_pending_del(l2_entry->mac);
+
+ if (rvu_sw_l2_offl_rule_push(offl_work->rvu, l2_entry))
+ dev_err(offl_work->rvu->dev,
+ "%s: Error to push l2 rule\n",
+ __func__);
+ kfree(l2_entry);
+ }
+
+ spin_lock_bh(&rvu_sw_l2_state_lock);
+ if (rvu_sw_l2_offl_wq && atomic_read(&l2_offl_list_cnt))
+ queue_work(rvu_sw_l2_offl_wq, &l2_offl_work.work);
+ spin_unlock_bh(&rvu_sw_l2_state_lock);
+}
+
+int rvu_sw_l2_init_offl_wq(struct rvu *rvu, u16 pcifunc, bool fw_up)
+{
+ struct rvu_switch *rswitch = &rvu->rswitch;
+
+ if (!fw_up) {
+ rvu_sw_l2_destroy_wqs(rvu);
+ return 0;
+ }
+
+ spin_lock_bh(&rvu_sw_l2_state_lock);
+ if (fw_is_up && rvu_sw_l2_offl_wq && fdb_refresh_wq) {
+ rswitch->pcifunc = pcifunc;
+ rswitch->flags |= RVU_SWITCH_FLAG_FW_READY;
+ spin_unlock_bh(&rvu_sw_l2_state_lock);
+ return 0;
+ }
+ spin_unlock_bh(&rvu_sw_l2_state_lock);
+
+ if (rvu_sw_l2_offl_wq || fdb_refresh_wq)
+ rvu_sw_l2_destroy_wqs(rvu);
+
+ l2_offl_work.rvu = rvu;
+ INIT_WORK(&l2_offl_work.work, rvu_sw_l2_offl_rule_wq_handler);
+ rvu_sw_l2_offl_wq = alloc_workqueue("swdev_rvu_sw_l2_offl_wq", 0, 0);
+ if (!rvu_sw_l2_offl_wq) {
+ dev_err(rvu->dev, "L2 offl workqueue allocation failed\n");
+ return -ENOMEM;
+ }
+
+ fdb_refresh_work.rvu = rvu;
+ INIT_WORK(&fdb_refresh_work.work, rvu_sw_l2_fdb_refresh_wq_handler);
+ fdb_refresh_wq = alloc_workqueue("swdev_fdb_refresh_wq", 0, 0);
+ if (!fdb_refresh_wq) {
+ dev_err(rvu->dev, "fdb refresh workqueue allocation failed\n");
+ destroy_workqueue(rvu_sw_l2_offl_wq);
+ rvu_sw_l2_offl_wq = NULL;
+ return -ENOMEM;
+ }
+
+ spin_lock_bh(&rvu_sw_l2_state_lock);
+ fw_is_up = true;
+ rswitch->pcifunc = pcifunc;
+ rswitch->flags |= RVU_SWITCH_FLAG_FW_READY;
+ spin_unlock_bh(&rvu_sw_l2_state_lock);
+
+ return 0;
+}
+
+int rvu_sw_l2_fdb_list_entry_add(struct rvu *rvu, u16 pcifunc, u8 *mac)
+{
+ struct workqueue_struct *wq;
+ struct l2_entry *l2_entry;
+
+ if (!is_pf_func_valid(rvu, pcifunc))
+ return -EINVAL;
+
+ spin_lock_bh(&rvu_sw_l2_state_lock);
+ if (!fdb_refresh_wq) {
+ spin_unlock_bh(&rvu_sw_l2_state_lock);
+ return -EINVAL;
+ }
+ spin_unlock_bh(&rvu_sw_l2_state_lock);
+
+ if (atomic_read(&fdb_refresh_list_cnt) >= RVU_SW_L2_LIST_MAX) {
+ rvu_sw_l2_list_cnt_warn(rvu->dev, &fdb_refresh_list_cnt,
+ "fdb refresh");
+ return -ENOMEM;
+ }
+
+ l2_entry = kcalloc(1, sizeof(*l2_entry), GFP_KERNEL);
+ if (!l2_entry)
+ return -ENOMEM;
+
+ l2_entry->port_id = pcifunc;
+ ether_addr_copy(l2_entry->mac, mac);
+
+ mutex_lock(&fdb_refresh_list_lock);
+ if (atomic_read(&fdb_refresh_list_cnt) >= RVU_SW_L2_LIST_MAX) {
+ rvu_sw_l2_list_cnt_warn(rvu->dev, &fdb_refresh_list_cnt,
+ "fdb refresh");
+ mutex_unlock(&fdb_refresh_list_lock);
+ kfree(l2_entry);
+ return -ENOMEM;
+ }
+ list_add_tail(&l2_entry->list, &fdb_refresh_lh);
+ rvu_sw_l2_list_cnt_inc(rvu->dev, &fdb_refresh_list_cnt, "fdb refresh");
+ mutex_unlock(&fdb_refresh_list_lock);
+
+ spin_lock_bh(&rvu_sw_l2_state_lock);
+ wq = fdb_refresh_wq;
+ if (wq)
+ queue_work(wq, &fdb_refresh_work.work);
+ spin_unlock_bh(&rvu_sw_l2_state_lock);
+
+ if (!wq) {
+ mutex_lock(&fdb_refresh_list_lock);
+ list_del_init(&l2_entry->list);
+ rvu_sw_l2_list_cnt_dec(rvu->dev, &fdb_refresh_list_cnt,
+ "fdb refresh");
+ mutex_unlock(&fdb_refresh_list_lock);
+ kfree(l2_entry);
+ return -EINVAL;
+ }
+
+ return 0;
+}
int rvu_mbox_handler_fdb_notify(struct rvu *rvu,
struct fdb_notify_req *req,
struct msg_rsp *rsp)
{
+ struct workqueue_struct *wq;
+ struct l2_entry *l2_entry;
+
+ spin_lock_bh(&rvu_sw_l2_state_lock);
+ if (!(rvu->rswitch.flags & RVU_SWITCH_FLAG_FW_READY) ||
+ !rvu_sw_l2_offl_wq) {
+ spin_unlock_bh(&rvu_sw_l2_state_lock);
+ return 0;
+ }
+ spin_unlock_bh(&rvu_sw_l2_state_lock);
+
+ if (atomic_read(&l2_offl_list_cnt) >= RVU_SW_L2_LIST_MAX) {
+ rvu_sw_l2_list_cnt_warn(rvu->dev, &l2_offl_list_cnt, "offload");
+ return -ENOMEM;
+ }
+
+ l2_entry = kcalloc(1, sizeof(*l2_entry), GFP_KERNEL);
+ if (!l2_entry)
+ return -ENOMEM;
+
+ l2_entry->port_id = rvu_sw_port_id(rvu, req->hdr.pcifunc);
+ ether_addr_copy(l2_entry->mac, req->mac);
+ l2_entry->flags = req->flags;
+
+ mutex_lock(&l2_offl_list_lock);
+ if (atomic_read(&l2_offl_list_cnt) >= RVU_SW_L2_LIST_MAX) {
+ rvu_sw_l2_list_cnt_warn(rvu->dev, &l2_offl_list_cnt, "offload");
+ mutex_unlock(&l2_offl_list_lock);
+ kfree(l2_entry);
+ return -ENOMEM;
+ }
+ list_add_tail(&l2_entry->list, &l2_offl_lh);
+ rvu_sw_l2_list_cnt_inc(rvu->dev, &l2_offl_list_cnt, "offload");
+ mutex_unlock(&l2_offl_list_lock);
+
+ spin_lock_bh(&rvu_sw_l2_state_lock);
+ wq = rvu_sw_l2_offl_wq;
+ if (wq)
+ queue_work(wq, &l2_offl_work.work);
+ spin_unlock_bh(&rvu_sw_l2_state_lock);
+
+ if (!wq) {
+ mutex_lock(&l2_offl_list_lock);
+ list_del_init(&l2_entry->list);
+ rvu_sw_l2_list_cnt_dec(rvu->dev, &l2_offl_list_cnt, "offload");
+ mutex_unlock(&l2_offl_list_lock);
+ kfree(l2_entry);
+ }
+
return 0;
}
+
+void rvu_sw_l2_shutdown(void)
+{
+ if (!fdb_refresh_wq && !rvu_sw_l2_offl_wq)
+ return;
+
+ rvu_sw_l2_destroy_wqs(l2_offl_work.rvu);
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h
index ff28612150c9..6685431d60a2 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h
@@ -8,4 +8,7 @@
#ifndef RVU_SW_L2_H
#define RVU_SW_L2_H
+int rvu_sw_l2_init_offl_wq(struct rvu *rvu, u16 pcifunc, bool fw_up);
+int rvu_sw_l2_fdb_list_entry_add(struct rvu *rvu, u16 pcifunc, u8 *mac);
+void rvu_sw_l2_shutdown(void);
#endif
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
index 2e33b33ec993..0cd6049c637e 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
@@ -28,6 +28,7 @@
#include <rvu_trace.h>
#include "cn10k_ipsec.h"
#include "otx2_xsk.h"
+#include "switch/sw_nb.h"
#define DRV_NAME "rvu_nicpf"
#define DRV_STRING "Marvell RVU NIC Physical Function Driver"
@@ -993,6 +994,7 @@ static int otx2_process_mbox_msg_up(struct otx2_nic *pf,
MBOX_UP_CGX_MESSAGES
MBOX_UP_MCS_MESSAGES
MBOX_UP_REP_MESSAGES
+MBOX_UP_AF2PF_FDB_REFRESH_MESSAGES
#undef M
break;
default:
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
index b022f52c6845..6f2fc4caf70c 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
@@ -9,6 +9,7 @@
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/net_tstamp.h>
+#include <net/switchdev.h>
#include "otx2_common.h"
#include "otx2_reg.h"
@@ -114,6 +115,33 @@ static void otx2vf_vfaf_mbox_handler(struct work_struct *work)
}
}
+#if IS_ENABLED(CONFIG_OCTEONTX_SWITCH)
+static int otx2vf_mbox_af2pf_fdb_refresh(struct otx2_nic *vf,
+ struct af2pf_fdb_refresh_req *req,
+ struct msg_rsp *rsp)
+{
+ struct switchdev_notifier_fdb_info item = {0};
+
+ item.addr = req->mac;
+ item.info.dev = vf->netdev;
+ if (req->flags & FDB_DEL)
+ call_switchdev_notifiers(SWITCHDEV_FDB_DEL_TO_BRIDGE,
+ item.info.dev, &item.info, NULL);
+ else
+ call_switchdev_notifiers(SWITCHDEV_FDB_ADD_TO_BRIDGE,
+ item.info.dev, &item.info, NULL);
+
+ return 0;
+}
+#else
+static int otx2vf_mbox_af2pf_fdb_refresh(struct otx2_nic *vf,
+ struct af2pf_fdb_refresh_req *req,
+ struct msg_rsp *rsp)
+{
+ return 0;
+}
+#endif
+
static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf,
struct mbox_msghdr *req)
{
@@ -141,6 +169,22 @@ static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf,
err = otx2_mbox_up_handler_cgx_link_event(
vf, (struct cgx_link_info_msg *)req, rsp);
return err;
+
+ case MBOX_MSG_AF2PF_FDB_REFRESH:
+ rsp = (struct msg_rsp *)otx2_mbox_alloc_msg(&vf->mbox.mbox_up, 0,
+ sizeof(struct msg_rsp));
+ if (!rsp)
+ return -ENOMEM;
+
+ rsp->hdr.id = MBOX_MSG_AF2PF_FDB_REFRESH;
+ rsp->hdr.sig = OTX2_MBOX_RSP_SIG;
+ rsp->hdr.pcifunc = req->pcifunc;
+ rsp->hdr.rc = 0;
+ err = otx2vf_mbox_af2pf_fdb_refresh(vf,
+ (struct af2pf_fdb_refresh_req *)req,
+ rsp);
+ return err;
+
default:
otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id);
return -ENODEV;
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c
index 6842c8d91ffc..eb5e2ce44ca2 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c
@@ -4,13 +4,231 @@
* Copyright (C) 2026 Marvell.
*
*/
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/switchdev.h>
+#include <net/netevent.h>
+#include <net/arp.h>
+
+#include "../otx2_reg.h"
+#include "../otx2_common.h"
+#include "../otx2_struct.h"
+#include "../cn10k.h"
+#include "sw_nb.h"
#include "sw_fdb.h"
+#if !IS_ENABLED(CONFIG_OCTEONTX_SWITCH)
+
+int otx2_mbox_up_handler_af2pf_fdb_refresh(struct otx2_nic *pf,
+ struct af2pf_fdb_refresh_req *req,
+ struct msg_rsp *rsp)
+{
+ return 0;
+}
+
+#else
+
+#define SW_FDB_LIST_MAX 4096
+
+static DEFINE_SPINLOCK(sw_fdb_llock);
+static LIST_HEAD(sw_fdb_lh);
+static atomic_t sw_fdb_list_cnt = ATOMIC_INIT(0);
+
+struct sw_fdb_list_entry {
+ struct list_head list;
+ u64 flags;
+ struct otx2_nic *pf;
+ netdevice_tracker dev_tracker;
+ u8 mac[ETH_ALEN];
+ bool add_fdb;
+};
+
+static struct workqueue_struct *sw_fdb_wq;
+static struct work_struct sw_fdb_work;
+
+static void sw_fdb_list_cnt_warn(struct net_device *netdev)
+{
+ int n = atomic_read(&sw_fdb_list_cnt);
+
+ if (n < 0)
+ netdev_warn(netdev, "FDB list count underflow: %d\n", n);
+ else if (n > SW_FDB_LIST_MAX)
+ netdev_warn(netdev, "FDB list count overflow: %d (max %d)\n",
+ n, SW_FDB_LIST_MAX);
+}
+
+static int sw_fdb_list_count(void)
+{
+ return atomic_read(&sw_fdb_list_cnt);
+}
+
+static void sw_fdb_list_cnt_inc(struct net_device *netdev)
+{
+ atomic_inc(&sw_fdb_list_cnt);
+ sw_fdb_list_cnt_warn(netdev);
+}
+
+static void sw_fdb_list_cnt_dec(struct net_device *netdev)
+{
+ atomic_dec(&sw_fdb_list_cnt);
+ sw_fdb_list_cnt_warn(netdev);
+}
+
+static int sw_fdb_add_or_del(struct otx2_nic *pf,
+ const unsigned char *addr,
+ bool add_fdb)
+{
+ struct fdb_notify_req *req;
+ int rc;
+
+ mutex_lock(&pf->mbox.lock);
+ req = otx2_mbox_alloc_msg_fdb_notify(&pf->mbox);
+ if (!req) {
+ rc = -ENOMEM;
+ goto out;
+ }
+
+ ether_addr_copy(req->mac, addr);
+ req->flags = add_fdb ? FDB_ADD : FDB_DEL;
+
+ rc = otx2_sync_mbox_msg(&pf->mbox);
+out:
+ mutex_unlock(&pf->mbox.lock);
+ return rc;
+}
+
+static void sw_fdb_wq_handler(struct work_struct *work)
+{
+ struct sw_fdb_list_entry *entry;
+ struct workqueue_struct *wq;
+ LIST_HEAD(tlist);
+
+ spin_lock_bh(&sw_fdb_llock);
+ list_splice_init(&sw_fdb_lh, &tlist);
+ spin_unlock_bh(&sw_fdb_llock);
+
+ while ((entry =
+ list_first_entry_or_null(&tlist,
+ struct sw_fdb_list_entry,
+ list)) != NULL) {
+ list_del_init(&entry->list);
+ sw_fdb_list_cnt_dec(entry->pf->netdev);
+ if (sw_fdb_add_or_del(entry->pf, entry->mac, entry->add_fdb))
+ netdev_err(entry->pf->netdev,
+ "Error to add/del fdb %pM entry\n",
+ entry->mac);
+ netdev_put(entry->pf->netdev, &entry->dev_tracker);
+ kfree(entry);
+ }
+
+ spin_lock_bh(&sw_fdb_llock);
+ wq = sw_fdb_wq;
+ if (wq && !list_empty(&sw_fdb_lh))
+ queue_work(wq, &sw_fdb_work);
+ spin_unlock_bh(&sw_fdb_llock);
+}
+
+int sw_fdb_add_to_list(struct net_device *dev, u8 *mac, bool add_fdb)
+{
+ struct otx2_nic *pf = netdev_priv(dev);
+ struct sw_fdb_list_entry *entry;
+ struct workqueue_struct *wq;
+
+ spin_lock_bh(&sw_fdb_llock);
+ if (!sw_fdb_wq) {
+ spin_unlock_bh(&sw_fdb_llock);
+ return -EINVAL;
+ }
+ spin_unlock_bh(&sw_fdb_llock);
+
+ if (sw_fdb_list_count() >= SW_FDB_LIST_MAX)
+ return -ENOMEM;
+
+ entry = kcalloc(1, sizeof(*entry), GFP_ATOMIC);
+ if (!entry)
+ return -ENOMEM;
+
+ ether_addr_copy(entry->mac, mac);
+ entry->add_fdb = add_fdb;
+ entry->pf = pf;
+ netdev_hold(dev, &entry->dev_tracker, GFP_ATOMIC);
+
+ spin_lock_bh(&sw_fdb_llock);
+ wq = sw_fdb_wq;
+ if (wq) {
+ list_add_tail(&entry->list, &sw_fdb_lh);
+ sw_fdb_list_cnt_inc(dev);
+ queue_work(wq, &sw_fdb_work);
+ }
+ spin_unlock_bh(&sw_fdb_llock);
+
+ if (!wq) {
+ netdev_put(dev, &entry->dev_tracker);
+ kfree(entry);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
int sw_fdb_init(void)
{
+ INIT_WORK(&sw_fdb_work, sw_fdb_wq_handler);
+ sw_fdb_wq = alloc_workqueue("sw_fdb_wq", 0, 0);
+ if (!sw_fdb_wq)
+ return -ENOMEM;
+
return 0;
}
void sw_fdb_deinit(void)
{
+ struct sw_fdb_list_entry *entry;
+ struct workqueue_struct *wq;
+ LIST_HEAD(tlist);
+
+ spin_lock_bh(&sw_fdb_llock);
+ wq = sw_fdb_wq;
+ sw_fdb_wq = NULL;
+ spin_unlock_bh(&sw_fdb_llock);
+
+ if (!wq)
+ return;
+
+ cancel_work_sync(&sw_fdb_work);
+ destroy_workqueue(wq);
+
+ spin_lock_bh(&sw_fdb_llock);
+ list_splice_init(&sw_fdb_lh, &tlist);
+ spin_unlock_bh(&sw_fdb_llock);
+
+ while ((entry =
+ list_first_entry_or_null(&tlist,
+ struct sw_fdb_list_entry,
+ list)) != NULL) {
+ list_del_init(&entry->list);
+ sw_fdb_list_cnt_dec(entry->pf->netdev);
+ netdev_put(entry->pf->netdev, &entry->dev_tracker);
+ kfree(entry);
+ }
+}
+
+int otx2_mbox_up_handler_af2pf_fdb_refresh(struct otx2_nic *pf,
+ struct af2pf_fdb_refresh_req *req,
+ struct msg_rsp *rsp)
+{
+ struct switchdev_notifier_fdb_info item = {0};
+
+ item.addr = req->mac;
+ item.info.dev = pf->netdev;
+ if (req->flags & FDB_DEL)
+ call_switchdev_notifiers(SWITCHDEV_FDB_DEL_TO_BRIDGE,
+ item.info.dev, &item.info, NULL);
+ else
+ call_switchdev_notifiers(SWITCHDEV_FDB_ADD_TO_BRIDGE,
+ item.info.dev, &item.info, NULL);
+
+ return 0;
}
+#endif
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h
index d4314d6d3ee4..3b06a77e6b56 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h
@@ -7,6 +7,7 @@
#ifndef SW_FDB_H_
#define SW_FDB_H_
+int sw_fdb_add_to_list(struct net_device *dev, u8 *mac, bool add_fdb);
void sw_fdb_deinit(void);
int sw_fdb_init(void);
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c
index bffe2af003c7..8aa357e9db21 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c
@@ -148,11 +148,13 @@ static int sw_nb_fdb_event(struct notifier_block *unused,
case SWITCHDEV_FDB_ADD_TO_DEVICE:
if (fdb_info->is_local)
break;
+ sw_fdb_add_to_list(dev, (u8 *)fdb_info->addr, true);
break;
case SWITCHDEV_FDB_DEL_TO_DEVICE:
if (fdb_info->is_local)
break;
+ sw_fdb_add_to_list(dev, (u8 *)fdb_info->addr, false);
break;
default:
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h
index e995c0e6046b..a701574de1e4 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h
@@ -14,6 +14,10 @@ struct otx2_nic;
struct af2pf_fdb_refresh_req;
struct msg_rsp;
+int otx2_mbox_up_handler_af2pf_fdb_refresh(struct otx2_nic *pf,
+ struct af2pf_fdb_refresh_req *req,
+ struct msg_rsp *rsp);
+
#if IS_ENABLED(CONFIG_OCTEONTX_SWITCH)
enum {
OTX2_DEV_UP = 1,
@@ -32,10 +36,6 @@ int sw_nb_unregister(struct net_device *netdev);
bool sw_nb_is_valid_dev(struct net_device *netdev);
struct net_device *sw_nb_resolve_pf_dev(struct net_device *dev);
-int otx2_mbox_up_handler_af2pf_fdb_refresh(struct otx2_nic *pf,
- struct af2pf_fdb_refresh_req *req,
- struct msg_rsp *rsp);
-
bool sw_nb_is_cavium_dev(struct net_device *netdev);
int sw_nb_fib_event_to_otx2_event(int event, struct net_device *netdev);
int sw_nb_inetaddr_event_to_otx2_event(int event, struct net_device *netdev);
--
2.43.0
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