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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771343040; bh=XBoj7jEee6VfITY4FrVhLwIQfn3xCXCky7dYUphWrbg=; h=Date:Subject:Cc:To:From:References:In-Reply-To:From; b=sVWscTb/mAJvi7p5NHrL9Wyzu+Rbk2HYWjeFQebqQWPkAr1bjPIMBBT56d2CZSSdz cAgLZNdUAvB7tfhy2u8UghAK8GizWwcQyoVzjmERGfr8fA4VEC5XyQ/PsKEfpcccd3 8MdOarGwt7ySv6rGm89MXnQfsscQdlOT2rCSc0Qkt3rQNUtV/8paUxq70iU2a9A6OW 9UeGTWVFCZr5POebt+DowX4SfTlmeuhtLBAZY3/AgcUfJp0Wb0gTjn7kGtWeuuvsWX hI9x6xae/QMMPgGk7G/9jUbZ/aUT2F/7mfF3s0y5o/uMm+C1qtWoFH9Fsvo+U1YGZd MFLcJ1Uv++RUA== Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 17 Feb 2026 16:43:54 +0100 Message-Id: Subject: Re: [PATCH v4 17/33] gpu: nova-core: Hopper/Blackwell: add FSP falcon EMEM operations To: "John Hubbard" From: "Danilo Krummrich" References: <20260210024601.593248-1-jhubbard@nvidia.com> <20260210024601.593248-18-jhubbard@nvidia.com> In-Reply-To: Message-ID-Hash: UHBGQL2JJPKOHG5J7QT7U4LBBQRO4NSY X-Message-ID-Hash: UHBGQL2JJPKOHG5J7QT7U4LBBQRO4NSY X-MailFrom: dakr@kernel.org X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation CC: Alexandre Courbot , Joel Fernandes , Alistair Popple , Eliot Courtney , Zhi Wang , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, LKML X-Mailman-Version: 3.3.8 Precedence: list List-Id: Nouveau development list Archived-At: Archived-At: List-Archive: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: On Thu Feb 12, 2026 at 3:09 AM CET, John Hubbard wrote: > On 2/11/26 2:57 AM, Danilo Krummrich wrote: >> On Tue Feb 10, 2026 at 3:45 AM CET, John Hubbard wrote: > ... >>> + #[expect(unused)] >>> + pub(crate) fn read_emem(&self, bar: &Bar0, offset: u32, data: &mut= [u8]) -> Result { >>> + // TODO: replace with `is_multiple_of` once the MSRV is >=3D 1= .82. >>> + if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { >>> + return Err(EINVAL); >>> + } >>> + >>> + regs::NV_PFALCON_FALCON_EMEM_CTL::default() >>> + .set_rd_mode(true) >>> + .set_offset(offset) >>> + .write(bar, &Fsp::ID); >>> + >>> + for chunk in data.chunks_exact_mut(4) { >>> + let word =3D regs::NV_PFALCON_FALCON_EMEM_DATA::read(bar, = &Fsp::ID).data(); >>> + chunk.copy_from_slice(&word.to_le_bytes()); >>> + } >>> + >>> + Ok(()) >>> + } >>> +} >>=20 >> Technically, we could represent this as a separate I/O backend and use I= oView / >> IoSlice (once we have it). >>=20 >> So, you could have Falcon::emem(), which returns an &Emem that impl= ements >> Io [1]. >>=20 >> This way we would get IoView and register!() for free on top of it. IoVi= ew will >> allow you to modify fields of the FSP structures similar to what we have= for DMA >> with dma_read!() and dma_write!(). >>=20 >> I just briefly glanced at the subsequent patches, but it looks like this= could >> save quite some code. >>=20 >> We may not get the full potential right away, as IoView is still WIP, bu= t I >> think it makes sense to consider it for a follow-up. >>=20 > > Yes, let's keep this in mind. Just to clarify, I mean we should implement Io and IoCapable right away, bu= t leave the rest as follow-up.