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Thu, 4 Jun 2026 04:44:55 -0700 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [PATCH 8/9] gpu: nova-core: set RMSetSriovMode when NVIDIA vGPU is enabled Date: Thu, 4 Jun 2026 14:43:38 +0300 Message-ID: <20260604114339.1565660-9-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260604114339.1565660-1-zhiw@nvidia.com> References: <20260604114339.1565660-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: nova-gpu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|DM4PR12MB6206:EE_ X-MS-Office365-Filtering-Correlation-Id: d087ad3a-c173-4e8b-6efe-08dec22ec6b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|7416014|1800799024|18002099003|22082099003|6133799003|3023799007|56012099006|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1G//XljhsWmJZIvdxDj0cYjj24IidGVb3M5c1s4DhPT5mYarbo2lPz0ti0omuy6xx6N/oLKAu1u2Rr6tqBxxSL8+AxdpyPxmddbEUfkFdcaVShwNSRASdn432/5Osr6FfkAF+zwscwED29B+tQlZGcaFnNwmPHl0V9bhNN75SaYuB8OecdOx5MT53VATuW9f/EuqgPNWFrdqx0Ix17HaG7SdLr/FO+sESyiKaKA4oYkZRggCsuGYkfu5wI4KVrC4oNfSaXtEmDD3hj/aZFrykSX3FBmxo+JCphWBp5vh3gtLd+ufnkCofje8nTn1A+l+kaGu1MNBe5kyAeCXrRdBvc6Ak+XF1LshEsyKw/iT4VxUx6UxhmpyW7qFMmbAB2pp79yahyeRgnxHZgdHQ5EwmNFl9P7u5G976xiN8fDZZhI9TMRIMJSe9oAagBR55IlH X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:45:28.9662 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d087ad3a-c173-4e8b-6efe-08dec22ec6b5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6206 The registry object "RMSetSriovMode" is required to be set when vGPU is enabled. Convert SetRegistry to use KVec for dynamic construction, allowing entries to be added conditionally at runtime. Set "RMSetSriovMode" to 1 when nova-core is loading the GSP firmware and initialize the GSP registry objects, if vGPU is enabled. Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/gsp/boot.rs | 2 +- drivers/gpu/nova-core/gsp/commands.rs | 93 ++++++++++++++++++--------- drivers/gpu/nova-core/gsp/fw.rs | 4 ++ 3 files changed, 67 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/boot.rs index 6e170401d616..2981d02d15ad 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -139,7 +139,7 @@ pub(crate) fn boot( self.cmdq .send_command_no_wait(ctx.bar, commands::SetSystemInfo::new(ctx.pdev, ctx.chipset))?; self.cmdq - .send_command_no_wait(ctx.bar, commands::SetRegistry::new())?; + .send_command_no_wait(ctx.bar, commands::SetRegistry::new(ctx.vgpu_requested.get())?)?; hal.post_boot(&self, ctx, &gsp_fw)?; diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs index f84de9f4f045..6171c60f6de0 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -29,6 +29,10 @@ }, fw::{ self, + commands::{ + PackedRegistryEntry, + PackedRegistryTable, // + }, MsgFunction, // }, }, @@ -65,38 +69,62 @@ struct RegistryEntry { } /// The `SetRegistry` command. +/// +/// Registry entries are built dynamically at runtime based on the current +/// configuration (e.g. whether vGPU is enabled). pub(crate) struct SetRegistry { - entries: [RegistryEntry; Self::NUM_ENTRIES], + entries: KVec, } impl SetRegistry { - // For now we hard-code the registry entries. Future work will allow others to - // be added as module parameters. - const NUM_ENTRIES: usize = 3; - - /// Creates a new `SetRegistry` command, using a set of hardcoded entries. - pub(crate) fn new() -> Self { - Self { - entries: [ - // RMSecBusResetEnable - enables PCI secondary bus reset - RegistryEntry { - key: "RMSecBusResetEnable", - value: 1, - }, - // RMForcePcieConfigSave - forces GSP-RM to preserve PCI configuration registers on - // any PCI reset. - RegistryEntry { - key: "RMForcePcieConfigSave", - value: 1, - }, - // RMDevidCheckIgnore - allows GSP-RM to boot even if the PCI dev ID is not found - // in the internal product name database. + /// Creates a new `SetRegistry` command. + /// + /// The base set of registry entries is always included. Additional entries + /// are appended dynamically based on runtime conditions (e.g. vGPU). + pub(crate) fn new(vgpu_requested: bool) -> Result { + let mut entries = KVec::new(); + + // RMSecBusResetEnable - enables PCI secondary bus reset + entries.push( + RegistryEntry { + key: "RMSecBusResetEnable", + value: 1, + }, + GFP_KERNEL, + )?; + + // RMForcePcieConfigSave - forces GSP-RM to preserve PCI configuration registers on + // any PCI reset. + entries.push( + RegistryEntry { + key: "RMForcePcieConfigSave", + value: 1, + }, + GFP_KERNEL, + )?; + + // RMDevidCheckIgnore - allows GSP-RM to boot even if the PCI dev ID is not found + // in the internal product name database. + entries.push( + RegistryEntry { + key: "RMDevidCheckIgnore", + value: 1, + }, + GFP_KERNEL, + )?; + + // RMSetSriovMode - required when vGPU is enabled. + if vgpu_requested { + entries.push( RegistryEntry { - key: "RMDevidCheckIgnore", + key: "RMSetSriovMode", value: 1, }, - ], + GFP_KERNEL, + )?; } + + Ok(Self { entries }) } } @@ -107,28 +135,31 @@ impl CommandToGsp for SetRegistry { type InitError = Infallible; fn init(&self) -> impl Init { - Self::Command::init(Self::NUM_ENTRIES as u32, self.variable_payload_len() as u32) + PackedRegistryTable::init( + self.entries.len() as u32, + self.variable_payload_len() as u32, + ) } fn variable_payload_len(&self) -> usize { let mut key_size = 0; - for i in 0..Self::NUM_ENTRIES { - key_size += self.entries[i].key.len() + 1; // +1 for NULL terminator + for entry in self.entries.iter() { + key_size += entry.key.len() + 1; // +1 for NULL terminator } - Self::NUM_ENTRIES * size_of::() + key_size + self.entries.len() * size_of::() + key_size } fn init_variable_payload( &self, dst: &mut SBufferIter>, ) -> Result { - let string_data_start_offset = size_of::() - + Self::NUM_ENTRIES * size_of::(); + let string_data_start_offset = size_of::() + + self.entries.len() * size_of::(); // Array for string data. let mut string_data = KVec::new(); - for entry in self.entries.iter().take(Self::NUM_ENTRIES) { + for entry in self.entries.iter() { dst.write_all( fw::commands::PackedRegistryEntry::new( (string_data_start_offset + string_data.len()) as u32, diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw.rs index 4db0cfa4dc4d..14424a2c2d83 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -299,6 +299,7 @@ pub(crate) enum MsgFunction { OsErrorLog = bindings::NV_VGPU_MSG_EVENT_OS_ERROR_LOG, PostEvent = bindings::NV_VGPU_MSG_EVENT_POST_EVENT, RcTriggered = bindings::NV_VGPU_MSG_EVENT_RC_TRIGGERED, + GpuacctPerfmonUtilSamples = bindings::NV_VGPU_MSG_EVENT_GPUACCT_PERFMON_UTIL_SAMPLES, UcodeLibOsPrint = bindings::NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT, } @@ -348,6 +349,9 @@ fn try_from(value: u32) -> Result { bindings::NV_VGPU_MSG_EVENT_OS_ERROR_LOG => Ok(MsgFunction::OsErrorLog), bindings::NV_VGPU_MSG_EVENT_POST_EVENT => Ok(MsgFunction::PostEvent), bindings::NV_VGPU_MSG_EVENT_RC_TRIGGERED => Ok(MsgFunction::RcTriggered), + bindings::NV_VGPU_MSG_EVENT_GPUACCT_PERFMON_UTIL_SAMPLES => { + Ok(MsgFunction::GpuacctPerfmonUtilSamples) + } bindings::NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT => Ok(MsgFunction::UcodeLibOsPrint), _ => Err(EINVAL), } -- 2.51.0