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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?jGy25KAZl2VGJNliXiszfEUjQ7JJ9VKR+GyNt6GOhVjeTIFV00CPqQlqjF5M?= =?us-ascii?Q?wzQdWp/kBxr7Fw0Q95XpB6zWRlMq4jNmKyggrb2WB32dSLLyazs16OhoL60d?= =?us-ascii?Q?XyIDjce/8DhOXX+K4fri/zWdJafwnMTebnzP6qhe3efhHby/5drJbWVR//1D?= =?us-ascii?Q?U9AsLuB440c+CoeuRnEfia8CBylc2fhW8hvfbH/Gk3V0C2H1OieAvIQuEBLu?= =?us-ascii?Q?/7hebqYKmG/1d5FyxfYISrpUjmpnFbWG2NQkWNSlkuwT3PLq4v6mLlQl+CYO?= =?us-ascii?Q?3RS0ze5MsK9kICZ0x67D7BjVp/OoOJRiCK+2W1VfPKUs8JYUghRe1VkNdc+n?= =?us-ascii?Q?KOqNEt5WS6erqoLmHVaVN1r8GlVCzbJOc/bqbGed/WGTpBmjCBiKxa9nfPU/?= =?us-ascii?Q?EHIAjkZLygPPOF6hFTZJjKH3rebNG3hchZ/6wGvGX/tRDcFQGLRbG47YFcMv?= =?us-ascii?Q?jXWPT2FGwsvvhGxKazc/C9T+9awXZ28neXittBL3/qlItiK2lptU23Lr9cQ1?= =?us-ascii?Q?oannCYocOIE7X7yvGmCcvqD09dIiIIh9jRuFoRJonWq8qGPYKslkIfVs2xY7?= =?us-ascii?Q?tNxwkTx/Sf1/CU9jYYnL1W8/k1KejGdJtZaMpGvKPkRn8bgg+cHuBUE42ar5?= =?us-ascii?Q?KL14NJv62IY9G6F1D5ldduUTsIDtjVzb99lPI02j/nEEjmQ+Qwnc5td7+cuU?= =?us-ascii?Q?hc0a/Xc2VhYBdyvMNWzr7mAK/bZmylL/K+KvDrhCXL8SxRfdR3BQ1Bii2eoC?= =?us-ascii?Q?0X0r4MX4aSpQs5IN4LzymtaVoZZiB1tTYYgucSmV8cuocrG38Fua42h+yIsh?= =?us-ascii?Q?bm5kEK+q8u8cfnwm2sHhvFQp26O7adlNSHNCv6XIbMUo09ZKgOfIpZ+mWKxO?= =?us-ascii?Q?a6VLCGI0m8UmsasyopmpJwZJ8icE9QY4bBI8lNuSTcGmAHpHj60zDenrEJ/D?= =?us-ascii?Q?Yh6nzONu7rFVcpu+GY8eqr7Zt9mIhY4mUiwsAtj8Cqw78yj48Q3qywbVMKYy?= =?us-ascii?Q?ftL4VYFnw4jFR7JXOViZkhN2aVNOayWyaYcAtuV1xXnNf5lMWsSFzoqpGaLK?= =?us-ascii?Q?QFrQKfpiDbb3ewUY8uLLqEgK8Vgz/wVdJlcT/dTYczYRjCJfkCfJHXG5/xxc?= =?us-ascii?Q?hemNDmwH39FYMeJuNXUOLtUE0V4xjN/ptraZSRJ1arQXMIE2FhDkKmY7oKHu?= =?us-ascii?Q?NdyuVUkAW6sU3df7MOxyRPhctaZX94xF5K/JlZfdlQqwg+r2PNztFwXsNkeu?= =?us-ascii?Q?JwZNBCknltdqbkfFnxzCBBIOGXrq+0A0djluyBJFskfsv9BaRuA8OpiR6Nrm?= =?us-ascii?Q?lJPCg1HXHtLFTL/E6odxTyMG6vQwbn49goEZPpZieDEX/5/y9Y0xKC7mXz9E?= =?us-ascii?Q?eXU7roEybcLbot73mgGc3TVfuaZvEAojA0/SpBXJQ498UnUpUSXn+AZPinZG?= =?us-ascii?Q?rCL1sdvWzDY59Uqj9UptVNfra+6/c+pw0DaF6VAKHZh4jeNkJ7qX+DZjfiu9?= =?us-ascii?Q?7T2FWKv7+0siYgoLse3Jv6pMbsgpJe0+l+dPqE5KYhMBY/HYRtdnSm+xsHgk?= =?us-ascii?Q?ISr+kiTM/5U1trhebeSRtgrMuqvFBo2gphtRlRjJC7KtL4m/+BXNzMLn/HEN?= =?us-ascii?Q?91t6uIv1qsDfqV4B9kWRWrRH6PdwjkEtBmk6usyGmwhDYD0ak1VK7+jhNmDX?= =?us-ascii?Q?acQYBTFrfGdda8JE1EAOrjl1Q7/MA/Sh8KvaUFOxSKYjqvZhQejVsezEjs1H?= =?us-ascii?Q?mSEpI4CDDA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3bba2e89-57b5-4efb-b5be-08dec7576d65 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2026 01:19:04.7982 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: P2ZMjtOaEmLsROz/WFF0FIyuvfOOdUhlaEoguMFyc5DqOo1YEa1wKtxA++X8Gw7CkoJMQcLN4xnu+WdPZmZLQA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6060 The GB20x sysmem flush registers were defined relative to an Fbhub0Base register window, but there is exactly one FBHUB0 base, so expressing them as base-plus-offset only adds indirection. Rename these to FBHUB0 and give them their fixed absolute addresses, dropping the base struct and its RegisterBase impl. No functional changes. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fb/hal/gb202.rs | 26 +++++++------------------- drivers/gpu/nova-core/regs.rs | 19 ++++++++----------- 2 files changed, 15 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/nova-core/fb/hal/gb202.rs b/drivers/gpu/nova-core/fb/hal/gb202.rs index 038d1278c634..6747ba6c9c13 100644 --- a/drivers/gpu/nova-core/fb/hal/gb202.rs +++ b/drivers/gpu/nova-core/fb/hal/gb202.rs @@ -4,13 +4,7 @@ //! Blackwell GB20x framebuffer HAL. use kernel::{ - io::{ - register::{ - RegisterBase, - WithBase, // - }, - Io, // - }, + io::Io, num::Bounded, prelude::*, sizes::SizeConstants, // @@ -24,17 +18,13 @@ struct Gb202; -impl RegisterBase for Gb202 { - const BASE: usize = 0x008a_0000; -} - fn read_sysmem_flush_page_gb202(bar: Bar0<'_>) -> u64 { let lo = u64::from( - bar.read(regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::of::()) + bar.read(regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO) .adr(), ); let hi = u64::from( - bar.read(regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::of::()) + bar.read(regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI) .adr(), ); @@ -44,15 +34,13 @@ fn read_sysmem_flush_page_gb202(bar: Bar0<'_>) -> u64 { /// Write the sysmem flush page address through the GB20x FBHUB0 registers. fn write_sysmem_flush_page_gb202(bar: Bar0<'_>, addr: Bounded) { // Write HI first. The hardware will trigger the flush on the LO write. - bar.write( - regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::of::(), - regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::zeroed() + bar.write_reg( + regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI::zeroed() .with_adr(addr.shr::<32, 20>().cast::()), ); - bar.write( - regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::of::(), + bar.write_reg( // CAST: lower 32 bits. Hardware ignores bits 7:0. - regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::zeroed().with_adr(*addr as u32), + regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO::zeroed().with_adr(*addr as u32), ); } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 73339a0cff99..5ab7ccfb9855 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -153,11 +153,6 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> kernel::fmt::Result { /// The base is provided by the GB10x framebuffer HAL. pub(crate) struct Hshub0Base(()); -/// Base of the GB20x FBHUB0 register window (`NV_FBHUB0_PRI_BASE` in Open RM). -/// -/// The base is provided by the GB20x framebuffer HAL. -pub(crate) struct Fbhub0Base(()); - register! { // GB10x sysmem flush registers, relative to the HSHUB0 base. GB10x routes sysmembar // through a primary and an EG (egress) pair that must both be programmed to the same @@ -178,16 +173,18 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> kernel::fmt::Result { pub(crate) NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Hshub0Base + 0x000006c4 { 19:0 adr; } +} - // GB20x sysmem flush registers, relative to the FBHUB0 base. Unlike the older - // NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers which encode the address with an 8-bit - // right-shift, these take the raw address split into lower and upper halves. Hardware - // ignores bits 7:0 of the LO register. - pub(crate) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Fbhub0Base + 0x00001d58 { +register! { + // GB20x FBHUB0 sysmem flush registers. Unlike the older + // NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers, which encode the address with an + // 8-bit right-shift, these take the raw address split into lower and upper + // halves. Hardware ignores bits 7:0 of the LO register. + pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x008a1d58 { 31:0 adr => u32; } - pub(crate) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Fbhub0Base + 0x00001d5c { + pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x008a1d5c { 19:0 adr; } } -- 2.54.0