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Thu, 9 Jul 2026 08:02:08 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [PATCH v4 0/6] gpu: nova-core: boot GSP with vGPU enabled Date: Thu, 9 Jul 2026 18:02:00 +0300 Message-ID: <20260709150206.1046839-1-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: nova-gpu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3A:EE_|SAWPR12MB999163:EE_ X-MS-Office365-Filtering-Correlation-Id: cf0e83ef-a3f5-48e8-3da1-08deddcb215f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|7416014|36860700016|376014|82310400026|13003099007|18002099003|6133799003|5023799004|3023799007|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: /KGNN8d4e94ssvU9dh25GcqTkFS/2esd9mUzuKUNorDev1hrHTchHjfyBC8ociwe43UMWAB/QM0VSS6SXVcOjL3ez8lq107by7naVy3rR2FNhKEcwNFx7wXX5zAzqvLKQ15GUvhoxYfdd3i1qdoHFZOqCdboltqE5uoEZogFkCjjiUdJ91cnNfxtACuip/dm2d/Nb4Ig6ja3noL3JXMLUpEovVBRNXTgS3bJouRQ8nVzYYKIeS6mLoJlXFIpOCnmypD9+wvgrZQSXjOFXPk5DNCbQpkMScY4MdloNVUB0bYYVWLiiU7QZBJsNT13n9gKcka1SFSz+fOL4A518ra+mgd3kKWhaUHqLIndFNdXUxaoXLsdE2s03LMhXV3/v4M18FEu6g6V0tONKOW/MEgHB+H1IjjWu6xmOuP0sQc6PCBiwn9TAjqjZB9xch+qi8FCHp54zJJBxpRcv/2XemIyjiFARNgiGioOaYXycr9aLXt/vJzrUHuyQjk5EpzMhGiCE50NAwFRaOaCPvD3n4HGAMcfKKRyvKM5l6KiU7a9cTAlLEitUVpFIlaJ16jO/nflEVoxDMHsfqmppXHwsbXJFhWoEzd0kfLLIYczG3td8pa8Pida82bqfZMqKk74oWuBIsHdj4p7bBOhOhdp8DVtDE23yq3a9IMgNOwYVX6g57TW9MEQOH8o28P6XcSqbnU/7Z6TbzLOszrLFjWSln13Sg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(23010399003)(7416014)(36860700016)(376014)(82310400026)(13003099007)(18002099003)(6133799003)(5023799004)(3023799007)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UjSyWkA/8aCTRWZpfhmX1MbIBXadCCznW7AuMPad6nu4ym3I4t0OViciEsy4Plxho9SlFtNeSiwIXfW9e1aOgMFTbPBV7n5nO80jMjv1uihJHSP9Tv1m+6VgbrbtsXRREDfiZRf/7xNi3UZ0rbA0NSPrgLyydx/ICOsoRdV1irt31MjCdUCi+5J/aGDviGEg9YU0RCU+sa9xFFiw1Wxc7mL0M5fcM943CE3adOXtFvSeBlbC/L3qWDFPpP4/qTBuefhJXBp5XS8H5igj+H7bT3hdx/qFw7zXe042mT/ssl/p10+iocOs82f6w/Zd3a4BMW4fJUgEdsrRDthK6dkWdrvkE9OhjHrze+LcX4qwQv7GHnOrSFNnJTr3uilFKT0PBn3AxsCCYl65sZFLwjDjjHdUxeDK3uFEW+9ZErdb4ZoyykYZEklthXiIPAsDnbcq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2026 15:02:44.0045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf0e83ef-a3f5-48e8-3da1-08deddcb215f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SAWPR12MB999163 Booting GSP with vGPU enabled is part of the first milestone (M1) together with the Rust fwctl abstraction [1] and the nova-core fwctl driver [2] for upstream vGPU support. It allows us to validate the basic GSP boot flow with vGPU enabled and upload vGPU types even before the remaining nova-core dependencies are ready. The nova-vGPU WIP patches for all milestones can be found at [3]. This version is based on drm-rust-next plus Alexandre's v6 GSP boot process consolidation series [4]. The FSP response header rename and dynamic SetRegistry conversion from v3 have since been pushed to drm-rust-next, so this series now contains six patches. Changes in v4: - Rebase on the latest drm-rust-next and Alexandre's v6 GSP boot process consolidation series. - Add a conditional C helper for pci_sriov_get_totalvfs() so the Rust abstraction also builds when CONFIG_PCI_IOV is disabled. - Return Option> from the Rust SR-IOV helper so callers must handle the unavailable-SR-IOV case explicitly. - Derive Debug for VgpuState and log the complete state when VgpuManager is constructed. - Warn and fall back to VgpuState::Disabled when the optional vGPU state cannot be detected, so a detection failure does not prevent a bare-metal probe. - Document vGPU state detection, split the vGPU HAL implementations into per-chip modules, and call the HAL method directly through the exposed trait and selector. v3: - Split the FSP response header rename from the FSP PRC vGPU mode query into a separate patch. - Change pci_sriov_get_totalvfs() to return unsigned int on the C side while keeping the Rust helper as u16. - Move the vGPU capability gate into a dedicated vgpu::hal module. - Represent detected vGPU state as VgpuState instead of separate enabled/total_vfs accessors. - Keep total_vfs values below 2 on the disabled path, with an explicit comment for the current single-VF limitation. - Use the generated 570.144 GSP_FW_HEAP_SIZE_VGPU_DEFAULT binding for vGPU WPR2 heap sizing, and keep unsupported 0/1-VF states out of the vGPU heap path through VgpuState. v2: - Rebase on top of Alexandre's GSP boot process consolidation series. - Drop the FSP response, FSP documentation, and GspBootContext patches that are already in drm-rust-next or superseded by the prerequisite boot consolidation series. - Change pci_sriov_get_totalvfs() to return u16 and update existing C callers accordingly. - Make the Rust sriov_get_totalvfs() helper return u16 directly. - Rework the FSP PRC vGPU mode query to use typed subcommand, object ID, flags, request, and response structures. - Move vGPU state detection before GSP boot into a read-only VgpuManager, avoiding Mutex/Cell based mutation during boot. - Add a HAL method for the vGPU capability gate. - Split the SetRegistry changes into a dynamic-entry refactor and the RMSetSriovMode functional change. - Rework WPR2 heap sizing to consume VgpuManager, keep the vGPU heap-size helper in gsp/fw.rs, and drop the 1VM heap-size special case. [1] https://lore.kernel.org/rust-for-linux/20260217204909.211793-1-zhiw@nvidia.com/ [2] https://lore.kernel.org/rust-for-linux/20260305190936.398590-1-zhiw@nvidia.com/ [3] https://github.com/zhiwang-nvidia/nova-core/tree/zhi/nova-vgpu-wip [4] https://lore.kernel.org/all/20260709-nova-bootcontext-v6-0-520cbf8b9b50@nvidia.com/ Zhi Wang (6): PCI/IOV: Return unsigned int from pci_sriov_get_totalvfs() rust: pci: add sriov_get_totalvfs() helper gpu: nova-core: read vGPU mode from FSP via PRC protocol gpu: nova-core: add vGPU preludes gpu: nova-core: set RMSetSriovMode for vGPU gpu: nova-core: reserve vGPU WPR2 heap drivers/gpu/nova-core/fb.rs | 25 ++- drivers/gpu/nova-core/fsp.rs | 172 ++++++++++++++++++ drivers/gpu/nova-core/gpu.rs | 7 + drivers/gpu/nova-core/gsp.rs | 2 + drivers/gpu/nova-core/gsp/boot.rs | 4 +- drivers/gpu/nova-core/gsp/commands.rs | 14 +- drivers/gpu/nova-core/gsp/fw.rs | 5 + .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 1 + drivers/gpu/nova-core/mctp.rs | 2 + drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/vgpu.rs | 90 +++++++++ drivers/gpu/nova-core/vgpu/hal.rs | 25 +++ drivers/gpu/nova-core/vgpu/hal/gb202.rs | 15 ++ drivers/gpu/nova-core/vgpu/hal/tu102.rs | 15 ++ drivers/pci/iov.c | 2 +- include/linux/pci.h | 4 +- rust/helpers/pci.c | 8 + rust/kernel/pci.rs | 13 ++ 18 files changed, 394 insertions(+), 11 deletions(-) create mode 100644 drivers/gpu/nova-core/vgpu.rs create mode 100644 drivers/gpu/nova-core/vgpu/hal.rs create mode 100644 drivers/gpu/nova-core/vgpu/hal/gb202.rs create mode 100644 drivers/gpu/nova-core/vgpu/hal/tu102.rs base-commit: d85845b64c0020b2812243a22fa79d57cc1c1e38 prerequisite-patch-id: f0a0ce0462acc6881b0255d041605544baf85636 prerequisite-patch-id: 7f0350ec963632f62c0c11f3f31331fc61bf3d30 prerequisite-patch-id: 49215f9c00b0f49a63066e3f64f87c2d89467907 prerequisite-patch-id: 952b67f6cd6c4c32ad141a83476067761d96facd prerequisite-patch-id: 04f4e5dfde6f418544eae9d44737521bb1ca571b prerequisite-patch-id: 33740a010f5ebdf7da99338b809bc84e6477a887 prerequisite-patch-id: 21f6c58981b5644bf060ce927643243f9d22b476 prerequisite-patch-id: 0bd4a3c41b8f8947ee2fb02e181f37f7b7774f88 prerequisite-patch-id: dfefdb3c87a4022b93a1003ebe566f1945a735d1 prerequisite-patch-id: 329ac78d2f0e13b20781e1859a6976cda4db2cf6 prerequisite-patch-id: 92004c279388e29ec036dfa4e69ebfccebab80fd prerequisite-patch-id: dfd10bc2d272d344b6746ce3a05c73773b743696 prerequisite-patch-id: 1cfa743488bce0038da31b14dbe57297ca6381b9 -- 2.51.0