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Wed, 22 Jul 2026 00:39:55 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [PATCH v5 5/6] gpu: nova-core: set RMSetSriovMode for vGPU Date: Wed, 22 Jul 2026 10:39:12 +0300 Message-ID: <20260722073913.1807677-6-zhiw@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260722073913.1807677-1-zhiw@nvidia.com> References: <20260722073913.1807677-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: nova-gpu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE1A:EE_|SA0PR12MB4383:EE_ X-MS-Office365-Filtering-Correlation-Id: 75651c3c-cfbe-4523-f6d3-08dee7c4778a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|23010399003|1800799024|82310400026|36860700016|22082099003|18002099003|3023799007|10067099003|11063799006|56012099006|6133799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PMdNslMeR2bCEzeL35nf+UcP3GqoF7z3eEMNEDbUj1pcJE2ao3Y9vAck1PCuoFfevyiRSsvhRl8+/hH+pznug0akaHahfr1UYZE6vnJqSI+3ktDDHFqVEQckWwOyy7INQhscOO4xRDWr3uzCDMteVRL+lTekqdEav2ikAd6XaUY+Dhe/4z6/ruBxzxBRoErkPT4r8CPzrcF2NGi8WIEbruAtKstZGcTf3rFahupAtrdo9dj4TR+++VymwsoZ50mvCcMQPyXKAFF776iQWKsEAbTh0CAqNjDECtRV7ct/2YJCnTS51OctVqGmi1ahGOjMg1v2YwOEqa1MjWyKD5tr3opXOw/ycyDY1qt++iUlb+dj7pWjs3o53O4JuGTatiBckLraYVHhbYqQh/sT15tNwEjkax5uoxo32LDyBjwi8Ed9nKcdcYqG9euuxdB0MD3n X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jul 2026 07:40:13.7936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 75651c3c-cfbe-4523-f6d3-08dee7c4778a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4383 The GSP registry setup needs to advertise SR-IOV mode when nova-core boots GSP for an enabled vGPU configuration. Without the registry entry, GSP-RM is not told to initialize in the mode required by NVIDIA vGPU. Append RMSetSriovMode to the SetRegistry command when the vGPU state detected before GSP boot is enabled. Keep the existing registry entries unchanged for non-vGPU boots. Cc: Alexandre Courbot Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/gsp.rs | 1 - drivers/gpu/nova-core/gsp/boot.rs | 2 +- drivers/gpu/nova-core/gsp/commands.rs | 14 +++++++++++++- drivers/gpu/nova-core/vgpu.rs | 1 - 4 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 0480881d437f..70123dc54981 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -70,7 +70,6 @@ pub(crate) struct GspBootContext<'ctx, 'gpu> { pub(crate) gsp_falcon: &'ctx Falcon<'gpu, GspFalcon>, pub(crate) sec2_falcon: &'ctx Falcon<'gpu, Sec2Falcon>, pub(crate) fsp: Option<&'ctx mut Fsp<'gpu>>, - #[expect(dead_code)] pub(crate) vgpu: &'ctx VgpuManager, } diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/boot.rs index 6b7d00205000..a2e8342e7760 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -89,7 +89,7 @@ pub(crate) fn boot( self.cmdq .send_command_no_wait(bar, commands::SetSystemInfo::new(pdev, chipset))?; self.cmdq - .send_command_no_wait(bar, commands::SetRegistry::new()?)?; + .send_command_no_wait(bar, commands::SetRegistry::new(ctx.vgpu.state())?)?; hal.post_boot(&self, ctx, &gsp_fw)?; diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs index 08380de39048..134f34b19174 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -34,6 +34,7 @@ }, }, sbuffer::SBufferIter, + vgpu::VgpuState, // }; /// The `GspSetSystemInfo` command. @@ -72,7 +73,7 @@ pub(crate) struct SetRegistry { impl SetRegistry { /// Creates a new `SetRegistry` command, using a set of hardcoded entries. - pub(crate) fn new() -> Result { + pub(crate) fn new(vgpu_state: VgpuState) -> Result { let mut entries = KVec::new(); // RMSecBusResetEnable - enables PCI secondary bus reset @@ -104,6 +105,17 @@ pub(crate) fn new() -> Result { GFP_KERNEL, )?; + if matches!(vgpu_state, VgpuState::Enabled { .. }) { + // RMSetSriovMode - required when vGPU is enabled. + entries.push( + RegistryEntry { + key: "RMSetSriovMode", + value: 1, + }, + GFP_KERNEL, + )?; + } + Ok(Self { entries }) } } diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs index 71fd0fe879c2..5359847e2eb9 100644 --- a/drivers/gpu/nova-core/vgpu.rs +++ b/drivers/gpu/nova-core/vgpu.rs @@ -86,7 +86,6 @@ fn detect_state( } /// Returns the detected vGPU state for this boot. - #[expect(dead_code)] pub(crate) fn state(&self) -> VgpuState { self.state } -- 2.53.0