[PATCH v3 00/10] gpu: nova-core: add PRAMIN window support

[Eliot Courtney <ecourtney@nvidia.com>]

This series adds support for the PRAMIN window, plus some documentation.
Some of these patches were originally written by Joel Fernandes [1]. I
have updated them with changelog notes in each patch. For example, I
updated them for the newer IO machinery from Gary Guo.

This series adds a Pramin structure which deals with updating the PRAMIN
window and handing out typed MMIO views. The PRAMIN window is a method
that lets arbitrary VRAM be written over BAR0 by configuring a 1 MiB
window through GPU registers. That 1 MiB window can point anywhere in
VRAM. This is useful for bootstrapping e.g. GPU side page tables.

The Pramin structure hands out typed MMIO views to do writes through
rather than letting callers write directly through it. A follow up
series will add support for GPU side page table entry writing through
this mechanism. This abstraction is important for later since we will
eventually want to write the PTEs via BAR2 not PRAMIN - using a view
that we grab from the Pramin structure can abstract this out.

This is based on next-20260817 (e6664f2b33db), with Gary's register IO
projection  v3 series [2] applied on top.

[1]: https://lore.kernel.org/all/20260518180342.2387845-1-joelagnelf@nvidia.com/
[2]: https://patch.msgid.link/20260819-typed_register-v3-0-3699a75fadf1@garyguo.net

Signed-off-by: Eliot Courtney <ecourtney@nvidia.com>
---
Changes in v3:
- Dropped first three Bounded patches which are merged now
- Rebase on v3 of IO reg projections
- Carry Gary's Io::cast patch which was dropped in the v3 since we use
  it.
- Link to v2: https://patch.msgid.link/20260810-pramin-split-v2-0-65a00b3c7309@nvidia.com

Changes in v2:
- Rebase onto Gary's IO register projection series
- Drop Region::try_subregion patch in favour of Gary's reg projection
- Convert Pramin code to use Gary's reg projection
- Fix const {assert!} -> const_assert! (Gary)
- Add #[inline] to shr_exact (Sashiko, Alex)
- Link to v1: https://patch.msgid.link/20260805-pramin-split-v1-0-ff3e84a75dac@nvidia.com

---
Eliot Courtney (3):
      gpu: nova-core: mm: Implement Alignable and Debug for VramAddress
      gpu: nova-core: mm: Add the memory management HAL
      gpu: nova-core: Add self-test assertion macros and config option

Gary Guo (1):
      rust: io: add static `cast()` method for views

Joel Fernandes (6):
      gpu: nova-core: mm: Add VramAddress type
      gpu: nova-core: mm: Add PRAMIN window registers
      gpu: nova-core: mm: Add support to use PRAMIN windows to write to VRAM
      docs: gpu: nova-core: Document the PRAMIN aperture mechanism
      gpu: nova-core: mm: Add GpuMm centralized memory manager
      gpu: nova-core: mm: Add PRAMIN aperture self-tests

 Documentation/gpu/nova/core/pramin.rst   | 128 +++++++++++++
 Documentation/gpu/nova/index.rst         |   1 +
 drivers/gpu/nova-core/Kconfig            |   9 +
 drivers/gpu/nova-core/driver.rs          |   3 +
 drivers/gpu/nova-core/gpu.rs             |  30 ++-
 drivers/gpu/nova-core/gsp/commands.rs    |   4 +
 drivers/gpu/nova-core/gsp/fw/commands.rs |   5 +
 drivers/gpu/nova-core/mm.rs              | 163 ++++++++++++++++
 drivers/gpu/nova-core/mm/hal.rs          |  56 ++++++
 drivers/gpu/nova-core/mm/hal/gb100.rs    |  35 ++++
 drivers/gpu/nova-core/mm/hal/gh100.rs    |  35 ++++
 drivers/gpu/nova-core/mm/hal/tu102.rs    |  37 ++++
 drivers/gpu/nova-core/mm/pramin.rs       | 312 +++++++++++++++++++++++++++++++
 drivers/gpu/nova-core/mm/regs.rs         |  70 +++++++
 drivers/gpu/nova-core/nova_core.rs       |   3 +
 drivers/gpu/nova-core/selftest.rs        |  64 +++++++
 rust/kernel/io.rs                        |  39 ++++
 17 files changed, 993 insertions(+), 1 deletion(-)
---
base-commit: e6664f2b33db9b6811eb4cec109f06cb2b4f458d
change-id: 20260804-pramin-split-950e210b6e3f
prerequisite-change-id: 20260721-typed_register-176eab3abee7:v3
prerequisite-patch-id: 9d08451e181409e33cda3549dd2f6a18ad742a38
prerequisite-patch-id: 35e98efa10cce8cdd6c9df954c34d778a8b57e97
prerequisite-patch-id: 9dc002f047fb0c688c0ccce751535161fde8c216
prerequisite-patch-id: 551843cf854964cd9ef49378aa99000c8af73710
prerequisite-patch-id: 798405871b568af61cb6b9f0bf035c03b50eafe7
prerequisite-patch-id: fd9f266b3d8c80cc7ef4a3d59e302c25af9bb145
prerequisite-patch-id: 131291b0a4dc1ee7e43dd038f6f99fc5dc0eb99b
prerequisite-patch-id: 7c66eb2438e79edc6566b9e977ee33137d3e7fa1
prerequisite-patch-id: 8224018b7cfec0b00cce46b238abd9f68240e187
prerequisite-patch-id: cc910d5993c190268077d2dd56d787abd984465d
prerequisite-patch-id: 9590fa1a5c856c952eec73b630949a50e90ab4e8
prerequisite-patch-id: 511ce76481fe20bb1c498f020a5151bb008525f1
prerequisite-patch-id: 127be60ba6331574f6784cc8a5013d4f91b47df4
prerequisite-patch-id: d2faa8292625cbdc43f262f3773a1c5cc1f90935
prerequisite-patch-id: c447b4c47960e45497bd75bea84e6f1aea30eb74
prerequisite-patch-id: 5051a948fa965dd94348da1ec2f93bee8ff86106

Best regards,
--  
Eliot Courtney <ecourtney@nvidia.com>