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This does not provide sufficient ordering for DMA operations on AArch64. Fix this to be using the newly introduced `dma_mb(Ordering)` API. Also, there is an incorrect placement of barrier, which is also fixed. --- Changes in v4: - Moved barriers to pointer accessor/updater. This does mean unnecessary barrier in failed polling path but the code path is not critical. I mentioned about providing full acq/rel semantics, but ended up not doing it because LOAD->LOAD barrier is sufficient for the GSP->CPU messaging path, so it's best to still mention about the actually needed ordering only. - Link to v3: https://patch.msgid.link/20260819-rust-barrier-v3-0-d5b7bd7e6624@garyguo.net Changes in v3: - Drop abstraction changes which are already picked. - Improve ordering comment messages. - Replace control dependency reliance with explicit barrier. - Link to v2: https://patch.msgid.link/20260609-rust-barrier-v2-0-30fcc48e1cd0@garyguo.net Changes in v2: - Dropped `Acquire` and `Release` aliases of `Full` (Joel) - Use macros to implement most `MemoryBarrier` - Split Nova change to GSP->CPU commit and CPU->GSP commit (Joel) - Link to v1: https://patch.msgid.link/20260402152443.1059634-2-gary@kernel.org To: Danilo Krummrich To: Alice Ryhl To: Alexandre Courbot To: David Airlie To: Simona Vetter Cc: nova-gpu@lists.linux.dev Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org --- Gary Guo (2): gpu: nova-core: fix barrier usage in CPU->GSP messaging path gpu: nova-core: fix barrier usage in GSP->CPU messaging path drivers/gpu/nova-core/gsp/cmdq.rs | 41 ++++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 16 deletions(-) --- base-commit: 89c07d98716a13454ec3fd9f97689e812cc71bd4 change-id: 20260609-rust-barrier-63078ea76216 Best regards, -- Gary Guo