[PATCH v3 11/14] gpu: nova-core: add the falcon interrupt status and routing registers

[John Hubbard <jhubbard@nvidia.com>]

A falcon latches every interrupt cause in IRQSTAT, whichever target the
cause is routed to. On a RISC-V falcon each cause goes either to the
core itself or to the host, and PRISCV_RISCV_IRQMASK and
PRISCV_RISCV_IRQDEST select between them. Open RM intersects the three
registers to get the causes pending for the host.

A falcon signals the interrupt tree on a transition of the causes routed
to the host, so a handler that clears the tree leaf while a cause is
still latched leaves no transition behind. INTR_RETRIGGER supplies one,
and Turing falcons do not implement it.

Add all four, ahead of the GSP event handler that reads them. GA102
moved the routing pair and GA100 kept the Turing offsets, so those two
go in per-chip register modules rather than the common one.

Assisted-by: Cursor:claude-opus-5
Reviewed-by: Will Pierce <wpierce@nvidia.com>
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
---
 drivers/gpu/nova-core/regs.rs | 66 +++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 3422b49df7a7..502712e9c161 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -120,6 +120,14 @@ pub(crate) fn usable_fb_size(self) -> u64 {
         4:4     halt => bool;
     }
 
+    /// Interrupt causes latched at the falcon, one bit per cause.
+    ///
+    /// A cause appears here whoever it is routed to, so a handler on the host side has to
+    /// intersect it with the routing registers to get the causes routed to the host.
+    pub(crate) NV_PFALCON_FALCON_IRQSTAT(u32) @ PFalconBase + 0x00000008 {
+        6:6     swgen0 => bool;
+    }
+
     pub(crate) NV_PFALCON_FALCON_MAILBOX0(u32) @ PFalconBase + 0x00000040 {
         31:0    value => u32;
     }
@@ -247,6 +255,18 @@ pub(crate) fn usable_fb_size(self) -> u64 {
         0:0     reset => bool;
     }
 
+    /// Re-emits the falcon's latched interrupt causes into the interrupt tree.
+    ///
+    /// Write-only. A falcon signals the tree on a transition of the causes routed to the host, so
+    /// a handler that cleared the tree leaf while a cause was still latched has left no
+    /// transition behind, and this write supplies one. Turing falcons do not implement this
+    /// register.
+    ///
+    /// Open RM declares two elements and uses only the first.
+    pub(crate) NV_PFALCON_FALCON_INTR_RETRIGGER(u32)[2] @ PFalconBase + 0x000003e8 {
+        0:0     trigger => bool;
+    }
+
     pub(crate) NV_PFALCON_FBIF_TRANSCFG(u32)[8] @ PFalconBase + 0x00000600 {
         2:2     mem_type => FalconFbifMemType;
         1:0     target ?=> FalconFbifTarget;
@@ -395,6 +415,29 @@ pub(crate) mod gm107 {
     }
 }
 
+pub(crate) mod tu102 {
+    use kernel::io::register;
+
+    use crate::falcon::PFalcon2Base;
+
+    // PRISCV
+    //
+    // The two registers below select which of a RISC-V falcon's interrupt causes reach the host,
+    // in the layout of `NV_PFALCON_FALCON_IRQSTAT`. GA100 uses these offsets as well.
+
+    register! {
+        /// Causes the RISC-V core enables. Read-only to the host.
+        pub(crate) NV_PRISCV_RISCV_IRQMASK(u32) @ PFalcon2Base + 0x000002b4 {
+            31:0    value => u32;
+        }
+
+        /// Causes routed to the host rather than to the RISC-V core itself.
+        pub(crate) NV_PRISCV_RISCV_IRQDEST(u32) @ PFalcon2Base + 0x000002b8 {
+            31:0    value => u32;
+        }
+    }
+}
+
 pub(crate) mod ga100 {
     use kernel::io::register;
 
@@ -407,6 +450,29 @@ pub(crate) mod ga100 {
     }
 }
 
+pub(crate) mod ga102 {
+    use kernel::io::register;
+
+    use crate::falcon::PFalcon2Base;
+
+    // PRISCV
+    //
+    // GA102 moved the two routing registers. GA100 kept the Turing offsets, so this pair covers
+    // GA102 and later rather than the whole Ampere architecture.
+
+    register! {
+        /// Causes the RISC-V core enables. Read-only to the host.
+        pub(crate) NV_PRISCV_RISCV_IRQMASK(u32) @ PFalcon2Base + 0x00000528 {
+            31:0    value => u32;
+        }
+
+        /// Causes routed to the host rather than to the RISC-V core itself.
+        pub(crate) NV_PRISCV_RISCV_IRQDEST(u32) @ PFalcon2Base + 0x0000052c {
+            31:0    value => u32;
+        }
+    }
+}
+
 pub(crate) const NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS: u32 = 0xff;
 
 pub(crate) mod gh100 {
-- 
2.55.0