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charset=UTF-8 Date: Tue, 30 Jun 2026 22:39:01 +0900 Message-Id: Cc: , , , , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: Re: [PATCH v2 7/7] gpu: nova-core: reserve larger WPR2 heap for vGPU From: "Alexandre Courbot" To: "Zhi Wang" References: <20260622194353.1308872-1-zhiw@nvidia.com> <20260622194353.1308872-8-zhiw@nvidia.com> In-Reply-To: <20260622194353.1308872-8-zhiw@nvidia.com> X-ClientProxiedBy: OS7PR01CA0035.jpnprd01.prod.outlook.com (2603:1096:604:257::8) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: nova-gpu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DM6PR12MB4123:EE_ X-MS-Office365-Filtering-Correlation-Id: 5cc227e5-cd53-4f78-a9fd-08ded6acf48a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|10070799003|7416014|376014|23010399003|22082099003|18002099003|3023799007|4143699003|11063799006|56012099006; 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For vGPU, > reserve 581 MiB for up to 32 VFs and 1370 MiB for larger VF counts. > > Signed-off-by: Zhi Wang > --- > drivers/gpu/nova-core/fb.rs | 25 ++++++++++++++++++++----- > drivers/gpu/nova-core/gsp.rs | 1 + > drivers/gpu/nova-core/gsp/boot.rs | 2 +- > drivers/gpu/nova-core/gsp/fw.rs | 10 ++++++++++ > 4 files changed, 32 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs > index 725e428154cf..b5b1f6c13edc 100644 > --- a/drivers/gpu/nova-core/fb.rs > +++ b/drivers/gpu/nova-core/fb.rs > @@ -24,7 +24,8 @@ > gpu::Chipset, > gsp, > num::FromSafeCast, > - regs, // > + regs, > + vgpu::VgpuManager, // > }; > =20 > mod hal; > @@ -171,7 +172,12 @@ pub(crate) struct FbLayout { > =20 > impl FbLayout { > /// Computes the FB layout for `chipset` required to run the `gsp_fw= ` GSP firmware. > - pub(crate) fn new(chipset: Chipset, bar: Bar0<'_>, gsp_fw: &GspFirmw= are) -> Result { > + pub(crate) fn new( > + chipset: Chipset, > + bar: Bar0<'_>, > + gsp_fw: &GspFirmware, > + vgpu: &VgpuManager, > + ) -> Result { > let hal =3D hal::fb_hal(chipset); > =20 > let fb =3D { > @@ -234,10 +240,19 @@ pub(crate) fn new(chipset: Chipset, bar: Bar0<'_>, = gsp_fw: &GspFirmware) -> Resu > FbRange(elf_addr..elf_addr + elf_size) > }; > =20 > + let vf_partition_count =3D if vgpu.enabled() { > + vgpu.total_vfs().try_into().map_err(|_| EINVAL)? > + } else { > + 0 > + }; > + > let wpr2_heap =3D { > const WPR2_HEAP_DOWN_ALIGN: Alignment =3D Alignment::new::(); > - let wpr2_heap_size =3D > - gsp::LibosParams::from_chipset(chipset).wpr_heap_size(ch= ipset, fb.end)?; > + let wpr2_heap_size =3D if vgpu.enabled() { > + gsp::vgpu_fw_heap_size(u32::from(vgpu.total_vfs())) > + } else { > + gsp::LibosParams::from_chipset(chipset).wpr_heap_size(ch= ipset, fb.end)? > + }; > let wpr2_heap_addr =3D (elf.start - wpr2_heap_size).align_do= wn(WPR2_HEAP_DOWN_ALIGN); > =20 > FbRange(wpr2_heap_addr..(elf.start).align_down(WPR2_HEAP_DOW= N_ALIGN)) > @@ -265,7 +280,7 @@ pub(crate) fn new(chipset: Chipset, bar: Bar0<'_>, gs= p_fw: &GspFirmware) -> Resu > wpr2_heap, > wpr2, > heap, > - vf_partition_count: 0, > + vf_partition_count, > pmu_reserved_size: hal.pmu_reserved_size(), > }) > } > diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs > index 6821008d48d9..a159f36bf704 100644 > --- a/drivers/gpu/nova-core/gsp.rs > +++ b/drivers/gpu/nova-core/gsp.rs > @@ -26,6 +26,7 @@ > mod sequencer; > =20 > pub(crate) use fw::{ > + vgpu_fw_heap_size, > GspFmcBootParams, > GspFwWprMeta, > LibosParams, // > diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gs= p/boot.rs > index c607081e8242..dea028f4b434 100644 > --- a/drivers/gpu/nova-core/gsp/boot.rs > +++ b/drivers/gpu/nova-core/gsp/boot.rs > @@ -56,7 +56,7 @@ pub(crate) fn boot( > =20 > let gsp_fw =3D KBox::pin_init(GspFirmware::new(dev, chipset, FIR= MWARE_VERSION), GFP_KERNEL)?; > =20 > - let fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw)?; > + let fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw, ctx.vgpu)= ?; > dev_dbg!(dev, "{:#x?}\n", fb_layout); > =20 > let wpr_meta =3D Coherent::init(dev, GFP_KERNEL, GspFwWprMeta::n= ew(&gsp_fw, &fb_layout))?; > diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/= fw.rs > index 4db0cfa4dc4d..2fb72f8dc3c9 100644 > --- a/drivers/gpu/nova-core/gsp/fw.rs > +++ b/drivers/gpu/nova-core/gsp/fw.rs > @@ -101,6 +101,16 @@ pub(in crate::gsp) fn advance_cpu_write_ptr(qs: &Coh= erent, count: u32) { > pub(crate) const GSP_MSG_QUEUE_ELEMENT_SIZE_MAX: usize =3D > num::u32_as_usize(bindings::GSP_MSG_QUEUE_ELEMENT_SIZE_MAX); > =20 > +const GSP_FW_HEAP_SIZE_VGPU_DEFAULT: u64 =3D 581 * u64::SZ_1M; > +const GSP_FW_HEAP_SIZE_VGPU_48VMS: u64 =3D 1370 * u64::SZ_1M; Another thing: I would like to get these values generated from OpenRM, so they end up in `bindings.rs`, as these are firmware-dependent. I see that for 570.144 (the firmware we are currently supporting), only `GSP_FW_HEAP_SIZE_VGPU_DEFAULT` is defined. Is it ok if we limit ourselves to this value until the firmware upgrade? If so, here is the diff you can include to declare it in the right place: diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index ea350f9b2cc4..ebcc9f9ae126 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -40,6 +40,7 @@ fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::= core::fmt::Result { pub const GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100: u32 =3D 14680064; pub const GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB: u32 =3D 98304; pub const GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE: u32 =3D 100663296; +pub const GSP_FW_HEAP_SIZE_VGPU_DEFAULT: u32 =3D 609222656; pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB: u32 =3D 64; pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB: u32 =3D 256; pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB: u32 =3D 88;