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charset=UTF-8 Date: Thu, 23 Jul 2026 23:12:30 +0900 Message-Id: Subject: Re: [PATCH v2 06/10] gpu: nova-core: correct FRTS vidmem offset calculation From: "Alexandre Courbot" To: "Eliot Courtney" Cc: "Danilo Krummrich" , "Alice Ryhl" , "David Airlie" , "Simona Vetter" , "Benno Lossin" , "Gary Guo" , "John Hubbard" , "Alistair Popple" , "Timur Tabi" , , , , References: <20260703-blackwell-fixes-v2-0-8e3d8bc32bb9@nvidia.com> <20260703-blackwell-fixes-v2-6-8e3d8bc32bb9@nvidia.com> In-Reply-To: <20260703-blackwell-fixes-v2-6-8e3d8bc32bb9@nvidia.com> X-ClientProxiedBy: OSTPR01CA0089.jpnprd01.prod.outlook.com (2603:1096:604:218::6) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: nova-gpu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS3PR12MB999240:EE_ X-MS-Office365-Filtering-Correlation-Id: 129a40d5-fd32-4a24-6727-08dee8c47113 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|10070799003|366016|376014|23010399003|7416014|18002099003|22082099003|4143699003|10067099003|11063799006|56012099006; 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The layout > actually looks like this: > > | non-wpr heap | WPR2 .. FRTS | PMU reserved | ... | VGA workspace | > > It's just by coincidence + generous alignment that the values happened > to match. Instead, define a per-architecture reserved size at the end of > the framebuffer and use this plus the PMU reserved size to calculate the > frts vidmem offset. > > Fixes: d317e4585fa3 ("gpu: nova-core: Hopper/Blackwell: add FSP Chain of = Trust boot") > Signed-off-by: Eliot Courtney > --- > drivers/gpu/nova-core/fb.rs | 4 ++++ > drivers/gpu/nova-core/fb/hal.rs | 3 +++ > drivers/gpu/nova-core/fb/hal/ga100.rs | 4 ++++ > drivers/gpu/nova-core/fb/hal/ga102.rs | 4 ++++ > drivers/gpu/nova-core/fb/hal/gb100.rs | 5 +++++ > drivers/gpu/nova-core/fb/hal/gb202.rs | 5 +++++ > drivers/gpu/nova-core/fb/hal/gh100.rs | 4 ++++ > drivers/gpu/nova-core/fb/hal/tu102.rs | 8 ++++++++ > drivers/gpu/nova-core/fsp.rs | 25 ++++++++++++++++++------- > 9 files changed, 55 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs > index fd60f93258a9..5ffe66af282f 100644 > --- a/drivers/gpu/nova-core/fb.rs > +++ b/drivers/gpu/nova-core/fb.rs > @@ -305,6 +305,9 @@ pub(crate) struct FbSizes { > pub(crate) heap_size: u64, > /// PMU reserved memory size, in bytes. > pub(crate) pmu_reserved_size: u32, > + /// Size reserved at the end of the framebuffer. This is architectur= e dependent and used to > + /// compute the FRTS offset for the FSP CoT message. > + pub(crate) fb_end_reserved_size: u32, > /// Number of VF partitions. > pub(crate) vf_partition_count: u8, > } > @@ -322,6 +325,7 @@ fn new(chipset: Chipset, bar: Bar0<'_>) -> Result { > .wpr_heap_size(chipset, fb_size)?, > heap_size: u64::from(hal.non_wpr_heap_size()), > pmu_reserved_size: hal.pmu_reserved_size(), > + fb_end_reserved_size: hal.fb_end_reserved_size(), > vf_partition_count: 0, > }) > } > diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/h= al.rs > index 714f0b51cd8f..aa50534550eb 100644 > --- a/drivers/gpu/nova-core/fb/hal.rs > +++ b/drivers/gpu/nova-core/fb/hal.rs > @@ -41,6 +41,9 @@ pub(crate) trait FbHal { > =20 > /// Returns the FRTS size, in bytes. > fn frts_size(&self) -> u64; > + > + /// Returns the size reserved at the end of the framebuffer, in byte= s. > + fn fb_end_reserved_size(&self) -> u32; This connects to my comments on the previous patch, but this HAL method is only ever used on the FSP path, yet we have to provide values (that will remain unused), for all chipsets. This really strenghen the case for making FbLayout/FbRanges/FbSizes local to the boot method they belong to. Since `fb_end_reserved_size` is only ever used by `fsp.rs`, it would make sense (from an architectural point of view at least) to have it defined as a HAL method - even though its name screams "fb". Since they are firmware-dependent, I'm even tempted to place their definition as constants into `firmware/fw.rs` to make that fact unmistakable (and keep all firmware-dependent data in the same place, as missing these upon update is a source for headaches). It's not perfectly clean but there is precedent for that: `fb.rs` uses `LibosParams` for instance, and `GspFwWprMeta` also comes from there. > diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs > index 533fb95573ab..a38ba66626d8 100644 > --- a/drivers/gpu/nova-core/fsp.rs > +++ b/drivers/gpu/nova-core/fsp.rs > @@ -134,20 +134,31 @@ struct FspCotMessage { > } > =20 > impl FspCotMessage { > + /// Computes the FRTS vidmem offset for the Chain-of-Trust message. = It is measured from the end > + /// of the framebuffer. > + fn frts_vidmem_offset(fb_info: &FbSizes) -> Result { > + let mut offset =3D u64::from(fb_info.fb_end_reserved_size); > + > + if fb_info.pmu_reserved_size !=3D 0 { > + offset =3D offset > + .checked_add(u64::from(fb_info.pmu_reserved_size)) > + .ok_or(EINVAL)? > + // The 2 MiB alignment is r570-specific. > + .align_up(Alignment::new::()) > + .ok_or(EINVAL)?; Note that we are adding two `u32`s and aligning to 2M - so there is no risk of overflow. I think we can just document this, use unfallible operators, and return a `u64` directly. Although `align_up` will still return `Result`, so maybe we need to keep it after all - but the initial addition can be unchecked.