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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from MW4PR12MB6873.namprd12.prod.outlook.com (2603:10b6:303:20c::17) by CH3PR12MB7594.namprd12.prod.outlook.com (2603:10b6:610:140::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.8; Wed, 4 Nov 2026 14:04:16 +0000 Received: from MW4PR12MB6873.namprd12.prod.outlook.com ([fe80::a338:bd2c:3a38:ece1]) by MW4PR12MB6873.namprd12.prod.outlook.com ([fe80::a338:bd2c:3a38:ece1%5]) with mapi id 15.21.0592.007; Wed, 4 Nov 2026 14:04:14 +0000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 04 Nov 2026 23:04:11 +0900 Message-Id: Cc: "Danilo Krummrich" , "Alice Ryhl" , "David Airlie" , "Simona Vetter" , "Benno Lossin" , "Gary Guo" , "John Hubbard" , "Alistair Popple" , "Timur Tabi" , "Zhi Wang" , , , Subject: Re: [PATCH v2 4/5] gpu: nova-core: gsp: cmdq: compute the queue regions from a count and a slot From: "Alexandre Courbot" To: "Eliot Courtney" References: <20261102-r000-cmdq-prep-v2-0-c2c2b69bdec0@nvidia.com> <20261102-r000-cmdq-prep-v2-4-c2c2b69bdec0@nvidia.com> In-Reply-To: X-ClientProxiedBy: TYCP286CA0256.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:455::14) To MW4PR12MB6873.namprd12.prod.outlook.com (2603:10b6:303:20c::17) X-Mailing-List: nova-gpu@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW4PR12MB6873:EE_|CH3PR12MB7594:EE_ X-MS-Office365-Filtering-Correlation-Id: aa375e11-6f39-49b4-8a09-08df3a7c820b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|10070799003|366016|1800799024|10063799003|10067099003|6133799003|22082099003|18002099003|4143699003|56012099006|261021121427099003|261022105027099003|261009223027099003|261021123027099003|261026140227099003|261026121527099003|261028144727099003|261102123227099003|11063799006|261021135927099003; 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This works for msgq v0, where the pointers are indices >> into the ring, but msgq v2 (used by the r000 firmware) keeps them in >> BAR0 registers as free-running counters, so the branches and their >> SAFETY arguments would have to be rewritten for it. >> >> Instead, compute the number of slots available to the driver and the >> slot they start at, and derive the slices from that. The slot counts >> come from one helper per queue, which are the only two places msgq v2 >> will need to touch. >> >> Use I/O projections to limit the amount of unsafe code to the bare >> minimum. >> >> No functional change intended. >> >> Assisted-by: LLM >> Signed-off-by: John Hubbard >> Co-developed-by: Alexandre Courbot >> Signed-off-by: Alexandre Courbot >> --- >> drivers/gpu/nova-core/gsp/cmdq.rs | 130 +++++++++++++++++--------------= ------- >> 1 file changed, 58 insertions(+), 72 deletions(-) >> >> diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/g= sp/cmdq.rs >> index 90e26c4dcc28..33cb9174c1e6 100644 >> --- a/drivers/gpu/nova-core/gsp/cmdq.rs >> +++ b/drivers/gpu/nova-core/gsp/cmdq.rs >> @@ -19,8 +19,8 @@ >> Io, // >> }, >> new_mutex, >> + num::casts::FromSafeCast, >> prelude::*, >> - ptr, >> sync::{ >> barrier::{ >> dma_mb, >> @@ -186,60 +186,58 @@ fn new(dev: &'a device::Device, bar= : Bar0<'a>) -> Result { >> /// As the message queue is a circular buffer, the region may be di= scontiguous in memory. In >> /// that case the second slice will have a non-zero length. >> fn driver_write_area(&mut self) -> (&mut [[u8; GSP_PAGE_SIZE]], &mu= t [[u8; GSP_PAGE_SIZE]]) { >> - let tx =3D self.cpu_write_ptr(); >> - let rx =3D self.gsp_read_ptr(); >> + let avail =3D usize::from_safe_cast(self.cpuq_free_slots()); >> + let w_slot =3D usize::from_safe_cast(self.cpu_write_ptr()); >> =20 >> - // Pointer to the first entry of the CPU message queue. >> - let data =3D ptr::project!(mut self.mem.as_mut_ptr(), .cpuq.msg= q.data[build: 0]); >> + // `w_slot` is below `MSGQ_NUM_PAGES` per the invariant of `cpu= _write_ptr`, so the >> + // subtraction cannot underflow. >> + let before_wrap =3D avail.min(cv!(MSGQ_NUM_PAGES =3D> usize) - = w_slot); >> + // Per the line above, `before_wrap` is less or equal to `avail= ` so the subtraction cannot >> + // underflow. >> + let after_wrap =3D avail - before_wrap; >> =20 >> - let (tail_end, wrap_end) =3D if rx =3D=3D 0 { >> - // The write area is non-wrapping, and stops at the second-= to-last entry of the command >> - // queue (to leave the last one empty). >> - (MSGQ_NUM_PAGES - 1, 0) >> - } else if rx <=3D tx { >> - // The write area wraps and continues until `rx - 1`. >> - (MSGQ_NUM_PAGES, rx - 1) >> - } else { >> - // The write area doesn't wrap and stops at `rx - 1`. >> - (rx - 1, 0) >> - }; >> + // PANIC: `w_slot + before_wrap` is at most `MSGQ_NUM_PAGES` by= construction of >> + // `before_wrap`. >> + let after =3D io_project!(self.mem, .cpuq.msgq.data[panic: w_sl= ot..w_slot + before_wrap]); >> + // PANIC: `after_wrap` is at most `avail`, which is below `MSGQ= _NUM_PAGES`. >> + let before =3D io_project!(self.mem, .cpuq.msgq.data[panic: ..a= fter_wrap]); > > It looks like compared to v1, this kept the `after` and `before` names I > suggested but changed the indices (e.g. in_after =3D> before_wrap). It > means that "before" and "after" are being used in two different ways in > this function ("after wrapping" and "after write pointer"). What about > picking one usage for the entire function? Either is fine imo. Same for > the other spot (read side). Indeed, this was a bit confusing. I have used `after_len/before_len` for the length, and kept `after/before` for the slices, so things should be more consistent now.