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The > r000 load-and-execute bootloader event can name any image for it to > load, and the bootloader must then sit above the blocks that the image > occupies, that is, in the last blocks of IMEM, regardless of its size. > > Place the bootloader at the top of the falcon's IMEM, using the IMEM > size that the HWCFG register reports, instead of assuming a 64 KiB IMEM. > > Assisted-by: LLM > Signed-off-by: John Hubbard > Reviewed-by: Timur Tabi > Reviewed-by: Zhi Wang > [acourbot: split out of the patch separating the bootloader from FWSEC; > convert the IMEM size with usize::from()] > Signed-off-by: Alexandre Courbot > --- > drivers/gpu/nova-core/falcon.rs | 7 +++++++ > drivers/gpu/nova-core/firmware/fwsec/bootloader.rs | 3 ++- > drivers/gpu/nova-core/firmware/gen_bootloader.rs | 23 +++++++++++++---= ------ > drivers/gpu/nova-core/gsp/hal/tu102.rs | 6 ++++-- > drivers/gpu/nova-core/regs.rs | 5 +++++ > 5 files changed, 32 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falc= on.rs > index 0b377bd6524a..1bceb38c33c6 100644 > --- a/drivers/gpu/nova-core/falcon.rs > +++ b/drivers/gpu/nova-core/falcon.rs > @@ -382,6 +382,13 @@ pub(crate) fn new( > }) > } > =20 > + /// Returns the size of this falcon's IMEM in bytes. > + pub(crate) fn imem_size(&self) -> usize { > + let blocks =3D usize::from(self.pfalcon.read(regs::NV_PFALCON_FA= LCON_HWCFG).imem_size()); > + > + blocks * MEM_BLOCK_ALIGNMENT > + } > + > /// Resets DMA-related registers. > pub(crate) fn dma_reset(&self) { > self.pfalcon.update(regs::NV_PFALCON_FBIF_CTL, |v| { > diff --git a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs b/drivers= /gpu/nova-core/firmware/fwsec/bootloader.rs > index 59f57714fcfb..3943948d74bc 100644 > --- a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs > +++ b/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs > @@ -108,8 +108,9 @@ pub(crate) fn new( nit: docs on `GenericBootloader::new` and `FwsecFirmwareWithBl::new` need updating > - pub(crate) fn new(dev: &device::Device, chipset: Chip= set) -> Result { > + pub(crate) fn new( > + dev: &device::Device, > + chipset: Chipset, > + falcon: &Falcon<'_, Gsp>, > + ) -> Result { > let fw =3D request_tlv(dev, chipset, "gen_bootloader")?; > let tlv =3D Tlv::new(fw.data())?; > dev_dbg!( > @@ -68,9 +73,9 @@ pub(crate) fn new(dev: &device::Device, = chipset: Chipset) -> Resu > ucode > }; > =20 > - // The bootloader's code must be loaded in the area right below = the first 64K of IMEM. > - const BOOTLOADER_LOAD_CEILING: usize =3D sizes::SZ_64K; > - let imem_dst_start =3D BOOTLOADER_LOAD_CEILING > + // The top of IMEM, above the blocks that the bootloader loads t= he image into. > + let imem_dst_start =3D falcon > + .imem_size() > .checked_sub(ucode.len()) > .ok_or(EOVERFLOW)?; `imem_size` is 8:0 (so 9 bits), and multiplied by 256. So it can be max ~2^17. Then we subtract off ucode.len() and do u16::try_from, so that could fail. I don't know if any real hardware actually hits this though. This value (`imem_dst_start`) eventually gets written into NV_PFALCON_FALCON_IMEMC::offs which is 15:0 in nova. According to openrm though, it's 15:0 for turing, and after that it's 23:0. So maybe worth checking (then we'd widen `imem_dst_start` etc to u32). I think it probably 'just works' fine to switch to u32 and change NV_PFALCON_FALCON_IMEMC::offs to 23:0, even for turing, and would be the same behaviour as nouveau afaict.