From: Neeraj Kumar <s.neeraj@samsung.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev,
linux-kernel@vger.kernel.org, gost.dev@samsung.com,
a.manzanares@samsung.com, vishak.g@samsung.com,
neeraj.kernel@gmail.com, cpgs@samsung.com
Subject: Re: [PATCH V3 13/20] cxl/mem: Refactor cxl pmem region auto-assembling
Date: Fri, 7 Nov 2025 18:09:12 +0530 [thread overview]
Message-ID: <1983025922.01762749301758.JavaMail.epsvc@epcpadp1new> (raw)
In-Reply-To: <361d0e84-9362-4389-a909-37878910b90f@intel.com>
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On 06/10/25 08:55AM, Dave Jiang wrote:
>
>
>On 9/29/25 6:30 AM, Neeraj Kumar wrote:
>> On 23/09/25 03:37PM, Dave Jiang wrote:
>>>
>>>
>>> On 9/17/25 6:41 AM, Neeraj Kumar wrote:
>>>> In 84ec985944ef3, devm_cxl_add_nvdimm() sequence was changed and called
>>>> before devm_cxl_add_endpoint(). It's because cxl pmem region auto-assembly
>>>> used to get called at last in cxl_endpoint_port_probe(), which requires
>>>> cxl_nvd presence.
>>>>
>>>> For cxl region persistency, region creation happens during nvdimm_probe
>>>> which need the completion of endpoint probe.
>>>>
>>>> In order to accommodate both cxl pmem region auto-assembly and cxl region
>>>> persistency, refactored following
>>>>
>>>> 1. Re-Sequence devm_cxl_add_nvdimm() after devm_cxl_add_endpoint(). This
>>>> will be called only after successful completion of endpoint probe.
>>>>
>>>> 2. Moved cxl pmem region auto-assembly from cxl_endpoint_port_probe() to
>>>> cxl_mem_probe() after devm_cxl_add_nvdimm(). It gurantees both the
>>>> completion of endpoint probe and cxl_nvd presence before its call.
>>>
>>> Given that we are going forward with this implementation [1] from Dan and drivers like the type2 enabling are going to be using it as well, can you please consider converting this change to Dan's mechanism instead of creating a whole new one?
>>>
>>> I think the region discovery can be done via the ops->probe() callback. Thanks.
>>>
>>> [1]: https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git/commit/?h=for-6.18/cxl-probe-order&id=88aec5ea7a24da00dc92c7778df4851fe4fd3ec6
>>>
>>> DJ
>>>
>>
>> Sure, Let me revisit this.
>> It seems [1] is there in seperate branch "for-6.18/cxl-probe-order", and not yet merged into next, right?
>
>Right. I believe Smita and Alejandro are using that as well. Depending on who gets there first. We can setup an immutable branch at some point.
>
>[1]: https://lore.kernel.org/linux-cxl/20250822034202.26896-1-Smita.KoralahalliChannabasappa@amd.com/T/#t
>
>DJ
Hi Dave,
As per Dan's [1] newly introduced infra, Following is my understanding.
Currently cxl_pci does not care about the attach state of the cxl_memdev
because all generic memory expansion functionality can be handled by the
cxl_core. For accelerators, the driver needs to know and perform driver
specific initialization if CXL is available, or exectute a fallback to PCIe
only operation.
Dan's new infra is needed for CXL accelerator device drivers that need to
make decisions about enabling CXL dependent functionality in the device, or
falling back to PCIe-only operation.
During cxl_pci_probe() we call devm_cxl_add_memdev(struct cxl_memdev_ops *ops)
where function pointer as ops gets registered which gets called in cxl_mem_probe()
using cxlmd->ops->probe()
The probe callback runs after the port topology is successfully attached for
the given memdev.
So to use this infra we have to pass cxl_region_discovery() as ops parameter
of devm_cxl_add_memdev() getting called from cxl_pci_probe().
In this patch-set cxl_region_discovery() signature is different from cxlmd->ops->probe()
{{{
void cxl_region_discovery(struct cxl_port *port)
{
device_for_each_child(&port->dev, NULL, discover_region);
}
struct cxl_memdev_ops {
int (*probe)(struct cxl_memdev *cxlmd);
};
}}}
Even after changing the signature of cxl_region_discovery() as per cxlmd->ops->probe()
may create problem as when the ops->probe() fails, then it will halts the probe sequence
of cxl_pci_probe()
It is because discover_region() may fail if two memdevs are participating into one region
Also, region auto assembly is mandatory functionality which creates region
if (cxled->state == CXL_DECODER_STATE_AUTO) gets satisfied.
Currently region auto assembly (added by a32320b71f085) happens after successfull
enumeration of endpoint decoders at cxl_endpoint_port_probe(), which I have moved at
cxl_mem_probe() after devm_cxl_add_nvdimm() which prepares cxl_nvd infra required by it.
As discussed in [1], this patch-set does the movement of auto region assembly from
cxl_endpoint_port_probe() to cxl_mem_probe() and resolved the conflicting dependency
of cxl_nvd infra required by both region creation using LSA and auto region assembly.
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git/commit/?h=for-6.18/cxl-probe-order&id=88aec5ea7a24da00dc92c7778df4851fe4fd3ec6
[2]: https://lore.kernel.org/linux-cxl/1931444790.41752909482841.JavaMail.epsvc@epcpadp2new/
Please let me know if my understanding is correct or I am missing something?
Regards,
Neeraj
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next prev parent reply other threads:[~2025-11-10 4:35 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250917134126epcas5p3e20c773759b91f70a1caa32b9f6f27ff@epcas5p3.samsung.com>
2025-09-17 13:40 ` [PATCH V3 00/20] Add CXL LSA 2.1 format support in nvdimm and cxl pmem Neeraj Kumar
2025-09-17 13:40 ` [PATCH V3 01/20] nvdimm/label: Introduce NDD_REGION_LABELING flag to set region label Neeraj Kumar
2025-09-19 23:10 ` Dave Jiang
2025-09-22 12:41 ` Neeraj Kumar
2025-09-17 13:40 ` [PATCH V3 02/20] nvdimm/label: CXL labels skip the need for 'interleave-set cookie' Neeraj Kumar
2025-09-19 23:31 ` Dave Jiang
2025-09-17 13:40 ` [PATCH V3 03/20] nvdimm/label: Modify nd_label_base() signature Neeraj Kumar
2025-09-19 21:42 ` Ira Weiny
2025-09-19 23:34 ` Dave Jiang
2025-09-22 12:44 ` Neeraj Kumar
2025-09-24 21:02 ` Alison Schofield
2025-09-29 14:07 ` Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 04/20] nvdimm/label: Update mutex_lock() with guard(mutex)() Neeraj Kumar
2025-09-19 21:55 ` Ira Weiny
2025-09-22 12:56 ` Neeraj Kumar
2025-09-19 23:50 ` Dave Jiang
2025-09-20 17:44 ` Ira Weiny
2025-09-22 13:01 ` Neeraj Kumar
2025-09-24 21:42 ` Alison Schofield
2025-09-29 14:19 ` Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 05/20] nvdimm/namespace_label: Add namespace label changes as per CXL LSA v2.1 Neeraj Kumar
2025-09-17 14:54 ` Jonathan Cameron
2025-09-19 22:00 ` Ira Weiny
2025-09-22 13:05 ` Neeraj Kumar
2025-09-19 23:59 ` Dave Jiang
2025-09-22 13:03 ` Neeraj Kumar
2025-09-23 21:48 ` Dave Jiang
2025-09-29 13:28 ` Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 06/20] nvdimm/region_label: Add region label update support Neeraj Kumar
2025-09-17 15:36 ` Jonathan Cameron
2025-09-22 13:12 ` Neeraj Kumar
2025-10-06 16:56 ` Dave Jiang
2025-09-22 23:11 ` Dave Jiang
2025-09-29 13:24 ` Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 07/20] nvdimm/region_label: Add region label delete support Neeraj Kumar
2025-09-22 21:37 ` Dave Jiang
2025-09-29 13:13 ` Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 08/20] nvdimm/label: Include region label in slot validation Neeraj Kumar
2025-09-22 22:17 ` Dave Jiang
2025-09-29 13:17 ` Neeraj Kumar
2025-09-24 21:30 ` Alison Schofield
2025-09-29 14:10 ` Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 09/20] nvdimm/namespace_label: Skip region label during ns label DPA reservation Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 10/20] nvdimm/namespace_label: Skip region label during namespace creation Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 11/20] nvdimm/region_label: Preserve cxl region information from region label Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 12/20] nvdimm/region_label: Export routine to fetch region information Neeraj Kumar
2025-09-23 20:23 ` Dave Jiang
2025-09-29 13:26 ` Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 13/20] cxl/mem: Refactor cxl pmem region auto-assembling Neeraj Kumar
2025-09-23 22:37 ` Dave Jiang
2025-09-29 13:30 ` Neeraj Kumar
2025-10-06 15:55 ` Dave Jiang
2025-11-07 12:39 ` Neeraj Kumar [this message]
2025-11-12 15:55 ` Dave Jiang
2025-11-13 7:27 ` Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 14/20] cxl/region: Add devm_cxl_pmem_add_region() for pmem region creation Neeraj Kumar
2025-09-23 23:50 ` Dave Jiang
2025-09-29 13:37 ` Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 15/20] cxl: Add a routine to find cxl root decoder on cxl bus using cxl port Neeraj Kumar
2025-09-24 18:11 ` Dave Jiang
2025-09-29 13:40 ` Neeraj Kumar
2025-10-06 16:02 ` Dave Jiang
2025-09-17 13:41 ` [PATCH V3 16/20] cxl/mem: Preserve cxl root decoder during mem probe Neeraj Kumar
2025-09-24 18:23 ` Dave Jiang
2025-09-29 13:52 ` Neeraj Kumar
2025-09-24 21:38 ` Alison Schofield
2025-09-29 14:13 ` Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 17/20] cxl/pmem: Preserve region information into nd_set Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 18/20] cxl/pmem_region: Prep patch to accommodate pmem_region attributes Neeraj Kumar
2025-09-24 18:53 ` Dave Jiang
2025-09-29 13:57 ` Neeraj Kumar
2025-10-06 16:06 ` Dave Jiang
2025-11-07 12:49 ` Neeraj Kumar
2025-11-12 15:40 ` Dave Jiang
2025-11-13 7:29 ` Neeraj Kumar
2025-10-06 16:09 ` Dave Jiang
2025-09-17 13:41 ` [PATCH V3 19/20] cxl/pmem_region: Add sysfs attribute cxl region label updation/deletion Neeraj Kumar
2025-09-24 20:25 ` Dave Jiang
2025-09-29 14:00 ` Neeraj Kumar
2025-09-17 13:41 ` [PATCH V3 20/20] cxl/pmem: Add CXL LSA 2.1 support in cxl pmem Neeraj Kumar
2025-09-24 20:47 ` Dave Jiang
2025-09-29 14:02 ` Neeraj Kumar
2025-10-06 16:13 ` Dave Jiang
2025-09-17 14:50 ` [PATCH V3 00/20] Add CXL LSA 2.1 format support in nvdimm and " Jonathan Cameron
2025-09-17 15:38 ` Dave Jiang
2025-09-22 12:36 ` Neeraj Kumar
2025-09-23 23:04 ` Alison Schofield
2025-09-29 13:33 ` Neeraj Kumar
[not found] <CGME20250917133048epcas5p182057ccd92859fe501c0296a9027e3cf@epcas5p1.samsung.com>
2025-09-17 13:29 ` Neeraj Kumar
2025-09-17 13:29 ` [PATCH V3 13/20] cxl/mem: Refactor cxl pmem region auto-assembling Neeraj Kumar
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