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From: Dave Jiang <dave.jiang@intel.com>
To: Neeraj Kumar <s.neeraj@samsung.com>,
	linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev,
	linux-kernel@vger.kernel.org, gost.dev@samsung.com
Cc: a.manzanares@samsung.com, vishak.g@samsung.com,
	neeraj.kernel@gmail.com, cpgs@samsung.com
Subject: Re: [PATCH V3 13/20] cxl/mem: Refactor cxl pmem region auto-assembling
Date: Tue, 23 Sep 2025 15:37:54 -0700	[thread overview]
Message-ID: <c7b41eb6-b946-4ac0-9ddd-e75ba4ceb636@intel.com> (raw)
In-Reply-To: <20250917134116.1623730-14-s.neeraj@samsung.com>



On 9/17/25 6:41 AM, Neeraj Kumar wrote:
> In 84ec985944ef3, devm_cxl_add_nvdimm() sequence was changed and called
> before devm_cxl_add_endpoint(). It's because cxl pmem region auto-assembly
> used to get called at last in cxl_endpoint_port_probe(), which requires
> cxl_nvd presence.
> 
> For cxl region persistency, region creation happens during nvdimm_probe
> which need the completion of endpoint probe.
> 
> In order to accommodate both cxl pmem region auto-assembly and cxl region
> persistency, refactored following
> 
> 1. Re-Sequence devm_cxl_add_nvdimm() after devm_cxl_add_endpoint(). This
>    will be called only after successful completion of endpoint probe.
> 
> 2. Moved cxl pmem region auto-assembly from cxl_endpoint_port_probe() to
>    cxl_mem_probe() after devm_cxl_add_nvdimm(). It gurantees both the
>    completion of endpoint probe and cxl_nvd presence before its call.

Given that we are going forward with this implementation [1] from Dan and drivers like the type2 enabling are going to be using it as well, can you please consider converting this change to Dan's mechanism instead of creating a whole new one?

I think the region discovery can be done via the ops->probe() callback. Thanks.

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git/commit/?h=for-6.18/cxl-probe-order&id=88aec5ea7a24da00dc92c7778df4851fe4fd3ec6

DJ

> 
> Signed-off-by: Neeraj Kumar <s.neeraj@samsung.com>
> ---
>  drivers/cxl/core/region.c | 33 +++++++++++++++++++++++++++++++++
>  drivers/cxl/cxl.h         |  4 ++++
>  drivers/cxl/mem.c         | 24 +++++++++++++++---------
>  drivers/cxl/port.c        | 39 +--------------------------------------
>  4 files changed, 53 insertions(+), 47 deletions(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 7a0cead24490..c325aa827992 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -3606,6 +3606,39 @@ int cxl_add_to_region(struct cxl_endpoint_decoder *cxled)
>  }
>  EXPORT_SYMBOL_NS_GPL(cxl_add_to_region, "CXL");
>  
> +static int discover_region(struct device *dev, void *unused)
> +{
> +	struct cxl_endpoint_decoder *cxled;
> +	int rc;
> +
> +	if (!is_endpoint_decoder(dev))
> +		return 0;
> +
> +	cxled = to_cxl_endpoint_decoder(dev);
> +	if ((cxled->cxld.flags & CXL_DECODER_F_ENABLE) == 0)
> +		return 0;
> +
> +	if (cxled->state != CXL_DECODER_STATE_AUTO)
> +		return 0;
> +
> +	/*
> +	 * Region enumeration is opportunistic, if this add-event fails,
> +	 * continue to the next endpoint decoder.
> +	 */
> +	rc = cxl_add_to_region(cxled);
> +	if (rc)
> +		dev_dbg(dev, "failed to add to region: %#llx-%#llx\n",
> +			cxled->cxld.hpa_range.start, cxled->cxld.hpa_range.end);
> +
> +	return 0;
> +}
> +
> +void cxl_region_discovery(struct cxl_port *port)
> +{
> +	device_for_each_child(&port->dev, NULL, discover_region);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_region_discovery, "CXL");
> +
>  u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, u64 spa)
>  {
>  	struct cxl_region_ref *iter;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 4fe3df06f57a..b57597e55f7e 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -873,6 +873,7 @@ struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
>  int cxl_add_to_region(struct cxl_endpoint_decoder *cxled);
>  struct cxl_dax_region *to_cxl_dax_region(struct device *dev);
>  u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, u64 spa);
> +void cxl_region_discovery(struct cxl_port *port);
>  #else
>  static inline bool is_cxl_pmem_region(struct device *dev)
>  {
> @@ -895,6 +896,9 @@ static inline u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint,
>  {
>  	return 0;
>  }
> +static inline void cxl_region_discovery(struct cxl_port *port)
> +{
> +}
>  #endif
>  
>  void cxl_endpoint_parse_cdat(struct cxl_port *port);
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 6e6777b7bafb..54501616ff09 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -152,15 +152,6 @@ static int cxl_mem_probe(struct device *dev)
>  		return -ENXIO;
>  	}
>  
> -	if (cxl_pmem_size(cxlds) && IS_ENABLED(CONFIG_CXL_PMEM)) {
> -		rc = devm_cxl_add_nvdimm(parent_port, cxlmd);
> -		if (rc) {
> -			if (rc == -ENODEV)
> -				dev_info(dev, "PMEM disabled by platform\n");
> -			return rc;
> -		}
> -	}
> -
>  	if (dport->rch)
>  		endpoint_parent = parent_port->uport_dev;
>  	else
> @@ -184,6 +175,21 @@ static int cxl_mem_probe(struct device *dev)
>  	if (rc)
>  		dev_dbg(dev, "CXL memdev EDAC registration failed rc=%d\n", rc);
>  
> +	if (cxl_pmem_size(cxlds) && IS_ENABLED(CONFIG_CXL_PMEM)) {
> +		rc = devm_cxl_add_nvdimm(parent_port, cxlmd);
> +		if (rc) {
> +			if (rc == -ENODEV)
> +				dev_info(dev, "PMEM disabled by platform\n");
> +			return rc;
> +		}
> +	}
> +
> +	/*
> +	 * Now that all endpoint decoders are successfully enumerated, try to
> +	 * assemble region autodiscovery from committed decoders.
> +	 */
> +	cxl_region_discovery(cxlmd->endpoint);
> +
>  	/*
>  	 * The kernel may be operating out of CXL memory on this device,
>  	 * there is no spec defined way to determine whether this device
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index cf32dc50b7a6..07bb909b7d2e 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -30,33 +30,6 @@ static void schedule_detach(void *cxlmd)
>  	schedule_cxl_memdev_detach(cxlmd);
>  }
>  
> -static int discover_region(struct device *dev, void *unused)
> -{
> -	struct cxl_endpoint_decoder *cxled;
> -	int rc;
> -
> -	if (!is_endpoint_decoder(dev))
> -		return 0;
> -
> -	cxled = to_cxl_endpoint_decoder(dev);
> -	if ((cxled->cxld.flags & CXL_DECODER_F_ENABLE) == 0)
> -		return 0;
> -
> -	if (cxled->state != CXL_DECODER_STATE_AUTO)
> -		return 0;
> -
> -	/*
> -	 * Region enumeration is opportunistic, if this add-event fails,
> -	 * continue to the next endpoint decoder.
> -	 */
> -	rc = cxl_add_to_region(cxled);
> -	if (rc)
> -		dev_dbg(dev, "failed to add to region: %#llx-%#llx\n",
> -			cxled->cxld.hpa_range.start, cxled->cxld.hpa_range.end);
> -
> -	return 0;
> -}
> -
>  static int cxl_switch_port_probe(struct cxl_port *port)
>  {
>  	struct cxl_hdm *cxlhdm;
> @@ -121,17 +94,7 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
>  	if (rc)
>  		return rc;
>  
> -	rc = devm_cxl_enumerate_decoders(cxlhdm, &info);
> -	if (rc)
> -		return rc;
> -
> -	/*
> -	 * Now that all endpoint decoders are successfully enumerated, try to
> -	 * assemble regions from committed decoders
> -	 */
> -	device_for_each_child(&port->dev, NULL, discover_region);
> -
> -	return 0;
> +	return devm_cxl_enumerate_decoders(cxlhdm, &info);
>  }
>  
>  static int cxl_port_probe(struct device *dev)


  reply	other threads:[~2025-09-23 22:38 UTC|newest]

Thread overview: 89+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20250917134126epcas5p3e20c773759b91f70a1caa32b9f6f27ff@epcas5p3.samsung.com>
2025-09-17 13:40 ` [PATCH V3 00/20] Add CXL LSA 2.1 format support in nvdimm and cxl pmem Neeraj Kumar
2025-09-17 13:40   ` [PATCH V3 01/20] nvdimm/label: Introduce NDD_REGION_LABELING flag to set region label Neeraj Kumar
2025-09-19 23:10     ` Dave Jiang
2025-09-22 12:41       ` Neeraj Kumar
2025-09-17 13:40   ` [PATCH V3 02/20] nvdimm/label: CXL labels skip the need for 'interleave-set cookie' Neeraj Kumar
2025-09-19 23:31     ` Dave Jiang
2025-09-17 13:40   ` [PATCH V3 03/20] nvdimm/label: Modify nd_label_base() signature Neeraj Kumar
2025-09-19 21:42     ` Ira Weiny
2025-09-19 23:34     ` Dave Jiang
2025-09-22 12:44       ` Neeraj Kumar
2025-09-24 21:02         ` Alison Schofield
2025-09-29 14:07           ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 04/20] nvdimm/label: Update mutex_lock() with guard(mutex)() Neeraj Kumar
2025-09-19 21:55     ` Ira Weiny
2025-09-22 12:56       ` Neeraj Kumar
2025-09-19 23:50     ` Dave Jiang
2025-09-20 17:44       ` Ira Weiny
2025-09-22 13:01         ` Neeraj Kumar
2025-09-24 21:42     ` Alison Schofield
2025-09-29 14:19       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 05/20] nvdimm/namespace_label: Add namespace label changes as per CXL LSA v2.1 Neeraj Kumar
2025-09-17 14:54     ` Jonathan Cameron
2025-09-19 22:00     ` Ira Weiny
2025-09-22 13:05       ` Neeraj Kumar
2025-09-19 23:59     ` Dave Jiang
2025-09-22 13:03       ` Neeraj Kumar
2025-09-23 21:48     ` Dave Jiang
2025-09-29 13:28       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 06/20] nvdimm/region_label: Add region label update support Neeraj Kumar
2025-09-17 15:36     ` Jonathan Cameron
2025-09-22 13:12       ` Neeraj Kumar
2025-10-06 16:56       ` Dave Jiang
2025-09-22 23:11     ` Dave Jiang
2025-09-29 13:24       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 07/20] nvdimm/region_label: Add region label delete support Neeraj Kumar
2025-09-22 21:37     ` Dave Jiang
2025-09-29 13:13       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 08/20] nvdimm/label: Include region label in slot validation Neeraj Kumar
2025-09-22 22:17     ` Dave Jiang
2025-09-29 13:17       ` Neeraj Kumar
2025-09-24 21:30     ` Alison Schofield
2025-09-29 14:10       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 09/20] nvdimm/namespace_label: Skip region label during ns label DPA reservation Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 10/20] nvdimm/namespace_label: Skip region label during namespace creation Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 11/20] nvdimm/region_label: Preserve cxl region information from region label Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 12/20] nvdimm/region_label: Export routine to fetch region information Neeraj Kumar
2025-09-23 20:23     ` Dave Jiang
2025-09-29 13:26       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 13/20] cxl/mem: Refactor cxl pmem region auto-assembling Neeraj Kumar
2025-09-23 22:37     ` Dave Jiang [this message]
2025-09-29 13:30       ` Neeraj Kumar
2025-10-06 15:55         ` Dave Jiang
2025-11-07 12:39           ` Neeraj Kumar
2025-11-12 15:55             ` Dave Jiang
2025-11-13  7:27               ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 14/20] cxl/region: Add devm_cxl_pmem_add_region() for pmem region creation Neeraj Kumar
2025-09-23 23:50     ` Dave Jiang
2025-09-29 13:37       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 15/20] cxl: Add a routine to find cxl root decoder on cxl bus using cxl port Neeraj Kumar
2025-09-24 18:11     ` Dave Jiang
2025-09-29 13:40       ` Neeraj Kumar
2025-10-06 16:02         ` Dave Jiang
2025-09-17 13:41   ` [PATCH V3 16/20] cxl/mem: Preserve cxl root decoder during mem probe Neeraj Kumar
2025-09-24 18:23     ` Dave Jiang
2025-09-29 13:52       ` Neeraj Kumar
2025-09-24 21:38     ` Alison Schofield
2025-09-29 14:13       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 17/20] cxl/pmem: Preserve region information into nd_set Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 18/20] cxl/pmem_region: Prep patch to accommodate pmem_region attributes Neeraj Kumar
2025-09-24 18:53     ` Dave Jiang
2025-09-29 13:57       ` Neeraj Kumar
2025-10-06 16:06         ` Dave Jiang
2025-11-07 12:49           ` Neeraj Kumar
2025-11-12 15:40             ` Dave Jiang
2025-11-13  7:29               ` Neeraj Kumar
2025-10-06 16:09         ` Dave Jiang
2025-09-17 13:41   ` [PATCH V3 19/20] cxl/pmem_region: Add sysfs attribute cxl region label updation/deletion Neeraj Kumar
2025-09-24 20:25     ` Dave Jiang
2025-09-29 14:00       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 20/20] cxl/pmem: Add CXL LSA 2.1 support in cxl pmem Neeraj Kumar
2025-09-24 20:47     ` Dave Jiang
2025-09-29 14:02       ` Neeraj Kumar
2025-10-06 16:13         ` Dave Jiang
2025-09-17 14:50   ` [PATCH V3 00/20] Add CXL LSA 2.1 format support in nvdimm and " Jonathan Cameron
2025-09-17 15:38     ` Dave Jiang
2025-09-22 12:36     ` Neeraj Kumar
2025-09-23 23:04   ` Alison Schofield
2025-09-29 13:33     ` Neeraj Kumar
     [not found] <CGME20250917133048epcas5p182057ccd92859fe501c0296a9027e3cf@epcas5p1.samsung.com>
2025-09-17 13:29 ` Neeraj Kumar
2025-09-17 13:29   ` [PATCH V3 13/20] cxl/mem: Refactor cxl pmem region auto-assembling Neeraj Kumar

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