From: kernel test robot <lkp@intel.com>
To: oe-kbuild@lists.linux.dev
Cc: lkp@intel.com, Dan Carpenter <error27@gmail.com>
Subject: drivers/phy/samsung/phy-exynos5-usbdrd.c:1794 exynos5_usbdrd_orien_sw_set() error: 'phy_drd' dereferencing possible ERR_PTR()
Date: Mon, 30 Mar 2026 20:07:08 +0800 [thread overview]
Message-ID: <202603302019.JrplV8tA-lkp@intel.com> (raw)
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
CC: linux-kernel@vger.kernel.org
TO: Stephen Boyd <swboyd@chromium.org>
CC: Heikki Krogerus <heikki.krogerus@linux.intel.com>
CC: Xu Yang <xu.yang_2@nxp.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 7aaa8047eafd0bd628065b15757d9b48c5f9c07d
commit: 45fe729be9a6be326a1ca25af82d34de32ba2ce8 usb: typec: Stub out typec_switch APIs when CONFIG_TYPEC=n
date: 6 months ago
:::::: branch date: 13 hours ago
:::::: commit date: 6 months ago
config: arc-randconfig-r071-20260330 (https://download.01.org/0day-ci/archive/20260330/202603302019.JrplV8tA-lkp@intel.com/config)
compiler: arc-linux-gcc (GCC) 13.4.0
smatch: v0.5.0-9004-gb810ac53
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202603302019.JrplV8tA-lkp@intel.com/
smatch warnings:
drivers/phy/samsung/phy-exynos5-usbdrd.c:1794 exynos5_usbdrd_orien_sw_set() error: 'phy_drd' dereferencing possible ERR_PTR()
vim +/phy_drd +1794 drivers/phy/samsung/phy-exynos5-usbdrd.c
cc52a697f87e8b Ivaylo Ivanov 2025-05-04 1787
09dc674295a388 André Draszik 2024-12-06 1788 static int exynos5_usbdrd_orien_sw_set(struct typec_switch_dev *sw,
09dc674295a388 André Draszik 2024-12-06 1789 enum typec_orientation orientation)
09dc674295a388 André Draszik 2024-12-06 1790 {
09dc674295a388 André Draszik 2024-12-06 1791 struct exynos5_usbdrd_phy *phy_drd = typec_switch_get_drvdata(sw);
f4fb9c4d7f94da André Draszik 2024-12-06 1792 int ret;
f4fb9c4d7f94da André Draszik 2024-12-06 1793
f4fb9c4d7f94da André Draszik 2024-12-06 @1794 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
f4fb9c4d7f94da André Draszik 2024-12-06 1795 if (ret) {
f4fb9c4d7f94da André Draszik 2024-12-06 1796 dev_err(phy_drd->dev, "Failed to enable PHY clocks(s)\n");
f4fb9c4d7f94da André Draszik 2024-12-06 1797 return ret;
f4fb9c4d7f94da André Draszik 2024-12-06 1798 }
f4fb9c4d7f94da André Draszik 2024-12-06 1799
f4fb9c4d7f94da André Draszik 2024-12-06 1800 scoped_guard(mutex, &phy_drd->phy_mutex) {
f4fb9c4d7f94da André Draszik 2024-12-06 1801 void __iomem * const regs_base = phy_drd->reg_phy;
f4fb9c4d7f94da André Draszik 2024-12-06 1802 unsigned int reg;
f4fb9c4d7f94da André Draszik 2024-12-06 1803
f4fb9c4d7f94da André Draszik 2024-12-06 1804 if (orientation == TYPEC_ORIENTATION_NONE) {
f4fb9c4d7f94da André Draszik 2024-12-06 1805 reg = readl(regs_base + EXYNOS850_DRD_UTMI);
f4fb9c4d7f94da André Draszik 2024-12-06 1806 reg &= ~(UTMI_FORCE_VBUSVALID | UTMI_FORCE_BVALID);
f4fb9c4d7f94da André Draszik 2024-12-06 1807 writel(reg, regs_base + EXYNOS850_DRD_UTMI);
f4fb9c4d7f94da André Draszik 2024-12-06 1808
f4fb9c4d7f94da André Draszik 2024-12-06 1809 reg = readl(regs_base + EXYNOS850_DRD_HSP);
f4fb9c4d7f94da André Draszik 2024-12-06 1810 reg |= HSP_VBUSVLDEXTSEL;
f4fb9c4d7f94da André Draszik 2024-12-06 1811 reg &= ~HSP_VBUSVLDEXT;
f4fb9c4d7f94da André Draszik 2024-12-06 1812 writel(reg, regs_base + EXYNOS850_DRD_HSP);
f4fb9c4d7f94da André Draszik 2024-12-06 1813 } else {
f4fb9c4d7f94da André Draszik 2024-12-06 1814 reg = readl(regs_base + EXYNOS850_DRD_UTMI);
f4fb9c4d7f94da André Draszik 2024-12-06 1815 reg |= UTMI_FORCE_VBUSVALID | UTMI_FORCE_BVALID;
f4fb9c4d7f94da André Draszik 2024-12-06 1816 writel(reg, regs_base + EXYNOS850_DRD_UTMI);
f4fb9c4d7f94da André Draszik 2024-12-06 1817
f4fb9c4d7f94da André Draszik 2024-12-06 1818 reg = readl(regs_base + EXYNOS850_DRD_HSP);
f4fb9c4d7f94da André Draszik 2024-12-06 1819 reg |= HSP_VBUSVLDEXTSEL | HSP_VBUSVLDEXT;
f4fb9c4d7f94da André Draszik 2024-12-06 1820 writel(reg, regs_base + EXYNOS850_DRD_HSP);
f4fb9c4d7f94da André Draszik 2024-12-06 1821 }
09dc674295a388 André Draszik 2024-12-06 1822
09dc674295a388 André Draszik 2024-12-06 1823 phy_drd->orientation = orientation;
f4fb9c4d7f94da André Draszik 2024-12-06 1824 }
f4fb9c4d7f94da André Draszik 2024-12-06 1825
f4fb9c4d7f94da André Draszik 2024-12-06 1826 clk_bulk_disable(phy_drd->drv_data->n_clks, phy_drd->clks);
09dc674295a388 André Draszik 2024-12-06 1827
09dc674295a388 André Draszik 2024-12-06 1828 return 0;
09dc674295a388 André Draszik 2024-12-06 1829 }
09dc674295a388 André Draszik 2024-12-06 1830
:::::: The code at line 1794 was first introduced by commit
:::::: f4fb9c4d7f94dabef4abf2209cf840dd1c9ca11e phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+)
:::::: TO: André Draszik <andre.draszik@linaro.org>
:::::: CC: Vinod Koul <vkoul@kernel.org>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
reply other threads:[~2026-03-30 12:08 UTC|newest]
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