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Tue, 21 Apr 2026 12:32:25 +0000 (UTC) Authentication-Results: lists.trustedfirmware.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=lidjiUFB; dkim-atps=neutral Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 48D6A60123; Tue, 21 Apr 2026 12:32:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C61D7C2BCB0; Tue, 21 Apr 2026 12:32:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776774745; bh=fHogJFUXtmJ8h9rv9J/W39FCHQRKZiuaR6kEImeePd4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=lidjiUFBNlGW1ZK0cSZ+MOH/azPjNeQC2ufFrT3Euzuck2WCt3RLjFYrFRp0vfnli OuUlNVqJtli074ztaXzrFbQ/yRocV1IPcQWnHpns8hQ1NE57s+Sia+dZBi5TdWIkTa saMQNbkE5vLxG0Jay62Njd1XE4oPW1yWc7aBRs8YZU6awIQy0Yuhf4XkWVbBzy2F1K A4nPWMje0DwxXeQWCMRKEdOucnglxzzugl582jJbezldoCpkHno8lLygyOz7Ia9P8S H8bSr0zGdzaRMZRv3UWKdMFouo1Y6N2OwQIsWRisEmT9z48LmNyPoMWI4YzfzDIas8 HLFwNc8s0xsjQ== Date: Tue, 21 Apr 2026 18:02:06 +0530 To: lumag@kernel.org, robin.clark@oss.qualcomm.com Subject: Re: [PATCH v3 10/15] drm/msm: Switch to generic PAS TZ APIs Message-ID: References: <20260327131043.627120-1-sumit.garg@kernel.org> <20260327131043.627120-11-sumit.garg@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; 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ARC_NA(0.00)[]; TO_MATCH_ENVRCPT_SOME(0.00)[]; RCPT_COUNT_GT_50(0.00)[52]; RCVD_COUNT_TWO(0.00)[2]; ALIAS_RESOLVED(0.00)[]; DKIM_TRACE(0.00)[kernel.org:+] X-Rspamd-Server: lists.trustedfirmware.org X-Rspamd-Queue-Id: C151E44935 X-Spamd-Bar: - Message-ID-Hash: VHX33QVO37J5BS6RS3BKBMT27KOB2SCW X-Message-ID-Hash: VHX33QVO37J5BS6RS3BKBMT27KOB2SCW X-MailFrom: sumit.garg@kernel.org X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-op-tee.lists.trustedfirmware.org-0; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti. qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, harshal.dev@oss.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg X-Mailman-Version: 3.3.5 Precedence: list List-Id: Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: From: Sumit Garg via OP-TEE Reply-To: Sumit Garg Hey Rob, Dmitry, On Fri, Mar 27, 2026 at 06:40:38PM +0530, Sumit Garg wrote: > From: Sumit Garg > > Switch drm/msm client drivers over to generic PAS TZ APIs. Generic PAS > TZ service allows to support multiple TZ implementation backends like QTEE > based SCM PAS service, OP-TEE based PAS service and any further future TZ > backend service. > > Signed-off-by: Sumit Garg > --- > drivers/gpu/drm/msm/Kconfig | 1 + > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++-- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 ++++++----- > 3 files changed, 9 insertions(+), 7 deletions(-) > Can I get an ack from you on this change? I expect this complete patch-set to land via Qcom SoC tree. -Sumit > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig > index 250246f81ea9..09469d56513b 100644 > --- a/drivers/gpu/drm/msm/Kconfig > +++ b/drivers/gpu/drm/msm/Kconfig > @@ -21,6 +21,7 @@ config DRM_MSM > select SHMEM > select TMPFS > select QCOM_SCM > + select QCOM_PAS > select QCOM_UBWC_CONFIG > select WANT_DEV_COREDUMP > select SND_SOC_HDMI_CODEC if SND_SOC > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index ef9fd6171af7..3283852f9a14 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -5,7 +5,7 @@ > #include > #include > #include > -#include > +#include > #include > #include > #include > @@ -653,7 +653,7 @@ static int a5xx_zap_shader_resume(struct msm_gpu *gpu) > if (adreno_is_a506(adreno_gpu)) > return 0; > > - ret = qcom_scm_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID); > + ret = qcom_pas_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID); > if (ret) > DRM_ERROR("%s: zap-shader resume failed: %d\n", > gpu->name, ret); > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > index d5fe6f6f0dec..047df0393128 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -8,6 +8,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -146,10 +147,10 @@ static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, > goto out; > > /* Send the image to the secure world */ > - ret = qcom_scm_pas_auth_and_reset(pasid); > + ret = qcom_pas_auth_and_reset(pasid); > > /* > - * If the scm call returns -EOPNOTSUPP we assume that this target > + * If the pas call returns -EOPNOTSUPP we assume that this target > * doesn't need/support the zap shader so quietly fail > */ > if (ret == -EOPNOTSUPP) > @@ -175,9 +176,9 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) > if (!zap_available) > return -ENODEV; > > - /* We need SCM to be able to load the firmware */ > - if (!qcom_scm_is_available()) { > - DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n"); > + /* We need PAS to be able to load the firmware */ > + if (!qcom_pas_is_available()) { > + DRM_DEV_ERROR(&pdev->dev, "Qcom PAS is not available\n"); > return -EPROBE_DEFER; > } > > -- > 2.51.0 > >