* [PATCH linux dev-6.12 v1 1/6] soc: aspeed: Add XDMA Engine Driver
2025-09-02 18:31 [PATCH linux dev-6.12 v1 0/6] Port linux fixes from dev-6.6 Ninad Palsule
@ 2025-09-02 18:31 ` Ninad Palsule
2025-09-03 2:14 ` Andrew Jeffery
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 2/6] soc: aspeed: xdma: Add user interface Ninad Palsule
` (4 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Ninad Palsule @ 2025-09-02 18:31 UTC (permalink / raw)
To: openbmc, andrew, joel, eajames; +Cc: ninad, Andrew Jeffery
From: Eddie James <eajames@linux.ibm.com>
The XDMA engine embedded in the AST2500 and AST2600 SOCs performs PCI
DMA operations between the SOC (acting as a BMC) and a host processor
in a server.
This commit adds a driver to control the XDMA engine and adds functions
to initialize the hardware and memory and start DMA operations.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/1588697905-23444-3-git-send-email-eajames@linux.ibm.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
---
MAINTAINERS | 2 +
drivers/soc/aspeed/Kconfig | 10 +
drivers/soc/aspeed/Makefile | 1 +
drivers/soc/aspeed/aspeed-xdma.c | 961 +++++++++++++++++++++++++++++++
include/uapi/linux/aspeed-xdma.h | 38 ++
5 files changed, 1012 insertions(+)
create mode 100644 drivers/soc/aspeed/aspeed-xdma.c
create mode 100644 include/uapi/linux/aspeed-xdma.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8026b0337a0b1..cc6791d023ea7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3464,6 +3464,8 @@ M: Eddie James <eajames@linux.ibm.com>
L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/soc/aspeed/xdma.yaml
+F: drivers/soc/aspeed/aspeed-xdma.c
+F: include/uapi/linux/aspeed-xdma.h
ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
M: Corentin Chary <corentin.chary@gmail.com>
diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
index 7a2a5bed8bc57..bbb5f18a6704a 100644
--- a/drivers/soc/aspeed/Kconfig
+++ b/drivers/soc/aspeed/Kconfig
@@ -59,6 +59,16 @@ config ASPEED_SBC
Say yes to provide information about the secure boot controller in
debugfs.
+config ASPEED_XDMA
+ tristate "ASPEED XDMA Engine Driver"
+ select REGMAP
+ select MFD_SYSCON
+ depends on HAS_DMA
+ help
+ Enable support for the XDMA Engine found on the ASPEED BMC
+ SoCs. The XDMA engine can perform PCIe DMA operations between the BMC
+ and a host processor.
+
endmenu
endif
diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
index 042235ffa05b2..5f61bb4cc36cf 100644
--- a/drivers/soc/aspeed/Makefile
+++ b/drivers/soc/aspeed/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_ASPEED_UART_ROUTING) += aspeed-uart-routing.o
obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o
obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o
obj-$(CONFIG_ASPEED_SBC) += aspeed-sbc.o
+obj-$(CONFIG_ASPEED_XDMA) += aspeed-xdma.o
diff --git a/drivers/soc/aspeed/aspeed-xdma.c b/drivers/soc/aspeed/aspeed-xdma.c
new file mode 100644
index 0000000000000..fae8ebb09203c
--- /dev/null
+++ b/drivers/soc/aspeed/aspeed-xdma.c
@@ -0,0 +1,961 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright IBM Corp 2019
+
+#include <linux/aspeed-xdma.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/fs.h>
+#include <linux/genalloc.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_device.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/platform_device.h>
+#include <linux/poll.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+
+#define DEVICE_NAME "aspeed-xdma"
+
+#define SCU_AST2600_MISC_CTRL 0x0c0
+#define SCU_AST2600_MISC_CTRL_XDMA_BMC BIT(8)
+
+#define SCU_AST2600_DEBUG_CTRL 0x0c8
+#define DEBUG_CTRL_XDMA_DISABLE BIT(2)
+
+#define SCU_AST2500_PCIE_CONF 0x180
+#define SCU_AST2600_PCIE_CONF 0xc20
+#define SCU_PCIE_CONF_VGA_EN BIT(0)
+#define SCU_PCIE_CONF_VGA_EN_MMIO BIT(1)
+#define SCU_PCIE_CONF_VGA_EN_LPC BIT(2)
+#define SCU_PCIE_CONF_VGA_EN_MSI BIT(3)
+#define SCU_PCIE_CONF_VGA_EN_MCTP BIT(4)
+#define SCU_PCIE_CONF_VGA_EN_IRQ BIT(5)
+#define SCU_PCIE_CONF_VGA_EN_DMA BIT(6)
+#define SCU_PCIE_CONF_BMC_EN BIT(8)
+#define SCU_PCIE_CONF_BMC_EN_MMIO BIT(9)
+#define SCU_PCIE_CONF_BMC_EN_MSI BIT(11)
+#define SCU_PCIE_CONF_BMC_EN_MCTP BIT(12)
+#define SCU_PCIE_CONF_BMC_EN_IRQ BIT(13)
+#define SCU_PCIE_CONF_BMC_EN_DMA BIT(14)
+
+#define SCU_AST2500_BMC_CLASS_REV 0x19c
+#define SCU_AST2600_BMC_CLASS_REV 0xc68
+#define SCU_BMC_CLASS_REV_XDMA 0xff000001
+
+#define XDMA_CMDQ_SIZE PAGE_SIZE
+#define XDMA_NUM_CMDS \
+ (XDMA_CMDQ_SIZE / sizeof(struct aspeed_xdma_cmd))
+
+/* Aspeed specification requires 100us after disabling the reset */
+#define XDMA_ENGINE_SETUP_TIME_MAX_US 1000
+#define XDMA_ENGINE_SETUP_TIME_MIN_US 100
+
+#define XDMA_CMD_AST2500_PITCH_SHIFT 3
+#define XDMA_CMD_AST2500_PITCH_BMC GENMASK_ULL(62, 51)
+#define XDMA_CMD_AST2500_PITCH_HOST GENMASK_ULL(46, 35)
+#define XDMA_CMD_AST2500_PITCH_UPSTREAM BIT_ULL(31)
+#define XDMA_CMD_AST2500_PITCH_ADDR GENMASK_ULL(29, 4)
+#define XDMA_CMD_AST2500_PITCH_ID BIT_ULL(0)
+#define XDMA_CMD_AST2500_CMD_IRQ_EN BIT_ULL(31)
+#define XDMA_CMD_AST2500_CMD_LINE_NO GENMASK_ULL(27, 16)
+#define XDMA_CMD_AST2500_CMD_IRQ_BMC BIT_ULL(15)
+#define XDMA_CMD_AST2500_CMD_LINE_SIZE_SHIFT 4
+#define XDMA_CMD_AST2500_CMD_LINE_SIZE \
+ GENMASK_ULL(14, XDMA_CMD_AST2500_CMD_LINE_SIZE_SHIFT)
+#define XDMA_CMD_AST2500_CMD_ID BIT_ULL(1)
+
+#define XDMA_CMD_AST2600_PITCH_BMC GENMASK_ULL(62, 48)
+#define XDMA_CMD_AST2600_PITCH_HOST GENMASK_ULL(46, 32)
+#define XDMA_CMD_AST2600_PITCH_ADDR GENMASK_ULL(30, 0)
+#define XDMA_CMD_AST2600_CMD_64_EN BIT_ULL(40)
+#define XDMA_CMD_AST2600_CMD_IRQ_BMC BIT_ULL(37)
+#define XDMA_CMD_AST2600_CMD_IRQ_HOST BIT_ULL(36)
+#define XDMA_CMD_AST2600_CMD_UPSTREAM BIT_ULL(32)
+#define XDMA_CMD_AST2600_CMD_LINE_NO GENMASK_ULL(27, 16)
+#define XDMA_CMD_AST2600_CMD_LINE_SIZE GENMASK_ULL(14, 0)
+#define XDMA_CMD_AST2600_CMD_MULTILINE_SIZE GENMASK_ULL(14, 12)
+
+#define XDMA_AST2500_QUEUE_ENTRY_SIZE 4
+#define XDMA_AST2500_HOST_CMDQ_ADDR0 0x00
+#define XDMA_AST2500_HOST_CMDQ_ENDP 0x04
+#define XDMA_AST2500_HOST_CMDQ_WRITEP 0x08
+#define XDMA_AST2500_HOST_CMDQ_READP 0x0c
+#define XDMA_AST2500_BMC_CMDQ_ADDR 0x10
+#define XDMA_AST2500_BMC_CMDQ_ENDP 0x14
+#define XDMA_AST2500_BMC_CMDQ_WRITEP 0x18
+#define XDMA_AST2500_BMC_CMDQ_READP 0x1c
+#define XDMA_BMC_CMDQ_READP_RESET 0xee882266
+#define XDMA_AST2500_CTRL 0x20
+#define XDMA_AST2500_CTRL_US_COMP BIT(4)
+#define XDMA_AST2500_CTRL_DS_COMP BIT(5)
+#define XDMA_AST2500_CTRL_DS_DIRTY BIT(6)
+#define XDMA_AST2500_CTRL_DS_SIZE_256 BIT(17)
+#define XDMA_AST2500_CTRL_DS_TIMEOUT BIT(28)
+#define XDMA_AST2500_CTRL_DS_CHECK_ID BIT(29)
+#define XDMA_AST2500_STATUS 0x24
+#define XDMA_AST2500_STATUS_US_COMP BIT(4)
+#define XDMA_AST2500_STATUS_DS_COMP BIT(5)
+#define XDMA_AST2500_STATUS_DS_DIRTY BIT(6)
+#define XDMA_AST2500_INPRG_DS_CMD1 0x38
+#define XDMA_AST2500_INPRG_DS_CMD2 0x3c
+#define XDMA_AST2500_INPRG_US_CMD00 0x40
+#define XDMA_AST2500_INPRG_US_CMD01 0x44
+#define XDMA_AST2500_INPRG_US_CMD10 0x48
+#define XDMA_AST2500_INPRG_US_CMD11 0x4c
+#define XDMA_AST2500_INPRG_US_CMD20 0x50
+#define XDMA_AST2500_INPRG_US_CMD21 0x54
+#define XDMA_AST2500_HOST_CMDQ_ADDR1 0x60
+#define XDMA_AST2500_VGA_CMDQ_ADDR0 0x64
+#define XDMA_AST2500_VGA_CMDQ_ENDP 0x68
+#define XDMA_AST2500_VGA_CMDQ_WRITEP 0x6c
+#define XDMA_AST2500_VGA_CMDQ_READP 0x70
+#define XDMA_AST2500_VGA_CMD_STATUS 0x74
+#define XDMA_AST2500_VGA_CMDQ_ADDR1 0x78
+
+#define XDMA_AST2600_QUEUE_ENTRY_SIZE 2
+#define XDMA_AST2600_HOST_CMDQ_ADDR0 0x00
+#define XDMA_AST2600_HOST_CMDQ_ADDR1 0x04
+#define XDMA_AST2600_HOST_CMDQ_ENDP 0x08
+#define XDMA_AST2600_HOST_CMDQ_WRITEP 0x0c
+#define XDMA_AST2600_HOST_CMDQ_READP 0x10
+#define XDMA_AST2600_BMC_CMDQ_ADDR 0x14
+#define XDMA_AST2600_BMC_CMDQ_ENDP 0x18
+#define XDMA_AST2600_BMC_CMDQ_WRITEP 0x1c
+#define XDMA_AST2600_BMC_CMDQ_READP 0x20
+#define XDMA_AST2600_VGA_CMDQ_ADDR0 0x24
+#define XDMA_AST2600_VGA_CMDQ_ADDR1 0x28
+#define XDMA_AST2600_VGA_CMDQ_ENDP 0x2c
+#define XDMA_AST2600_VGA_CMDQ_WRITEP 0x30
+#define XDMA_AST2600_VGA_CMDQ_READP 0x34
+#define XDMA_AST2600_CTRL 0x38
+#define XDMA_AST2600_CTRL_US_COMP BIT(16)
+#define XDMA_AST2600_CTRL_DS_COMP BIT(17)
+#define XDMA_AST2600_CTRL_DS_DIRTY BIT(18)
+#define XDMA_AST2600_CTRL_DS_SIZE_256 BIT(20)
+#define XDMA_AST2600_STATUS 0x3c
+#define XDMA_AST2600_STATUS_US_COMP BIT(16)
+#define XDMA_AST2600_STATUS_DS_COMP BIT(17)
+#define XDMA_AST2600_STATUS_DS_DIRTY BIT(18)
+#define XDMA_AST2600_INPRG_DS_CMD00 0x40
+#define XDMA_AST2600_INPRG_DS_CMD01 0x44
+#define XDMA_AST2600_INPRG_DS_CMD10 0x48
+#define XDMA_AST2600_INPRG_DS_CMD11 0x4c
+#define XDMA_AST2600_INPRG_DS_CMD20 0x50
+#define XDMA_AST2600_INPRG_DS_CMD21 0x54
+#define XDMA_AST2600_INPRG_US_CMD00 0x60
+#define XDMA_AST2600_INPRG_US_CMD01 0x64
+#define XDMA_AST2600_INPRG_US_CMD10 0x68
+#define XDMA_AST2600_INPRG_US_CMD11 0x6c
+#define XDMA_AST2600_INPRG_US_CMD20 0x70
+#define XDMA_AST2600_INPRG_US_CMD21 0x74
+
+struct aspeed_xdma_cmd {
+ u64 host_addr;
+ u64 pitch;
+ u64 cmd;
+ u64 reserved;
+};
+
+struct aspeed_xdma_regs {
+ u8 bmc_cmdq_addr;
+ u8 bmc_cmdq_endp;
+ u8 bmc_cmdq_writep;
+ u8 bmc_cmdq_readp;
+ u8 control;
+ u8 status;
+};
+
+struct aspeed_xdma_status_bits {
+ u32 us_comp;
+ u32 ds_comp;
+ u32 ds_dirty;
+};
+
+struct aspeed_xdma;
+
+struct aspeed_xdma_chip {
+ u32 control;
+ u32 scu_bmc_class;
+ u32 scu_misc_ctrl;
+ u32 scu_pcie_conf;
+ unsigned int queue_entry_size;
+ struct aspeed_xdma_regs regs;
+ struct aspeed_xdma_status_bits status_bits;
+ unsigned int (*set_cmd)(struct aspeed_xdma *ctx,
+ struct aspeed_xdma_cmd cmds[2],
+ struct aspeed_xdma_op *op, u32 bmc_addr);
+};
+
+struct aspeed_xdma_client;
+
+struct aspeed_xdma {
+ struct kobject kobj;
+ const struct aspeed_xdma_chip *chip;
+
+ int irq;
+ int pcie_irq;
+ struct clk *clock;
+ struct device *dev;
+ void __iomem *base;
+ resource_size_t res_size;
+ resource_size_t res_start;
+ struct reset_control *reset;
+ struct reset_control *reset_rc;
+
+ /* Protects current_client */
+ spinlock_t client_lock;
+ struct aspeed_xdma_client *current_client;
+
+ /* Protects engine configuration */
+ spinlock_t engine_lock;
+ struct aspeed_xdma_cmd *cmdq;
+ unsigned int cmd_idx;
+ bool in_reset;
+ bool upstream;
+
+ /* Queue waiters for idle engine */
+ wait_queue_head_t wait;
+
+ struct work_struct reset_work;
+
+ u32 mem_phys;
+ u32 mem_size;
+ void *mem_virt;
+ dma_addr_t mem_coherent;
+ dma_addr_t cmdq_phys;
+ struct gen_pool *pool;
+};
+
+struct aspeed_xdma_client {
+ struct aspeed_xdma *ctx;
+
+ bool error;
+ bool in_progress;
+ void *virt;
+ dma_addr_t phys;
+ u32 size;
+};
+
+static u32 aspeed_xdma_readl(struct aspeed_xdma *ctx, u8 reg)
+{
+ u32 v = readl(ctx->base + reg);
+
+ dev_dbg(ctx->dev, "read %02x[%08x]\n", reg, v);
+ return v;
+}
+
+static void aspeed_xdma_writel(struct aspeed_xdma *ctx, u8 reg, u32 val)
+{
+ writel(val, ctx->base + reg);
+ dev_dbg(ctx->dev, "write %02x[%08x]\n", reg, val);
+}
+
+static void aspeed_xdma_init_eng(struct aspeed_xdma *ctx)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&ctx->engine_lock, flags);
+ aspeed_xdma_writel(ctx, ctx->chip->regs.bmc_cmdq_endp,
+ ctx->chip->queue_entry_size * XDMA_NUM_CMDS);
+ aspeed_xdma_writel(ctx, ctx->chip->regs.bmc_cmdq_readp,
+ XDMA_BMC_CMDQ_READP_RESET);
+ aspeed_xdma_writel(ctx, ctx->chip->regs.bmc_cmdq_writep, 0);
+ aspeed_xdma_writel(ctx, ctx->chip->regs.control, ctx->chip->control);
+ aspeed_xdma_writel(ctx, ctx->chip->regs.bmc_cmdq_addr, ctx->cmdq_phys);
+
+ ctx->cmd_idx = 0;
+ spin_unlock_irqrestore(&ctx->engine_lock, flags);
+}
+
+static unsigned int aspeed_xdma_ast2500_set_cmd(struct aspeed_xdma *ctx,
+ struct aspeed_xdma_cmd cmds[2],
+ struct aspeed_xdma_op *op,
+ u32 bmc_addr)
+{
+ unsigned int rc = 1;
+ unsigned int pitch = 1;
+ unsigned int line_no = 1;
+ unsigned int line_size = op->len >>
+ XDMA_CMD_AST2500_CMD_LINE_SIZE_SHIFT;
+ u64 cmd = XDMA_CMD_AST2500_CMD_IRQ_EN | XDMA_CMD_AST2500_CMD_IRQ_BMC |
+ XDMA_CMD_AST2500_CMD_ID;
+ u64 cmd_pitch = (op->direction ? XDMA_CMD_AST2500_PITCH_UPSTREAM : 0) |
+ XDMA_CMD_AST2500_PITCH_ID;
+
+ dev_dbg(ctx->dev, "xdma %s ast2500: bmc[%08x] len[%08x] host[%08x]\n",
+ op->direction ? "upstream" : "downstream", bmc_addr, op->len,
+ (u32)op->host_addr);
+
+ if (op->len > XDMA_CMD_AST2500_CMD_LINE_SIZE) {
+ unsigned int rem;
+ unsigned int total;
+
+ line_no = op->len / XDMA_CMD_AST2500_CMD_LINE_SIZE;
+ total = XDMA_CMD_AST2500_CMD_LINE_SIZE * line_no;
+ rem = (op->len - total) >>
+ XDMA_CMD_AST2500_CMD_LINE_SIZE_SHIFT;
+ line_size = XDMA_CMD_AST2500_CMD_LINE_SIZE;
+ pitch = line_size >> XDMA_CMD_AST2500_PITCH_SHIFT;
+ line_size >>= XDMA_CMD_AST2500_CMD_LINE_SIZE_SHIFT;
+
+ if (rem) {
+ u32 rbmc = bmc_addr + total;
+
+ cmds[1].host_addr = op->host_addr + (u64)total;
+ cmds[1].pitch = cmd_pitch |
+ ((u64)rbmc & XDMA_CMD_AST2500_PITCH_ADDR) |
+ FIELD_PREP(XDMA_CMD_AST2500_PITCH_HOST, 1) |
+ FIELD_PREP(XDMA_CMD_AST2500_PITCH_BMC, 1);
+ cmds[1].cmd = cmd |
+ FIELD_PREP(XDMA_CMD_AST2500_CMD_LINE_NO, 1) |
+ FIELD_PREP(XDMA_CMD_AST2500_CMD_LINE_SIZE,
+ rem);
+ cmds[1].reserved = 0ULL;
+
+ print_hex_dump_debug("xdma rem ", DUMP_PREFIX_OFFSET,
+ 16, 1, &cmds[1], sizeof(*cmds),
+ true);
+
+ cmd &= ~(XDMA_CMD_AST2500_CMD_IRQ_EN |
+ XDMA_CMD_AST2500_CMD_IRQ_BMC);
+
+ rc++;
+ }
+ }
+
+ cmds[0].host_addr = op->host_addr;
+ cmds[0].pitch = cmd_pitch |
+ ((u64)bmc_addr & XDMA_CMD_AST2500_PITCH_ADDR) |
+ FIELD_PREP(XDMA_CMD_AST2500_PITCH_HOST, pitch) |
+ FIELD_PREP(XDMA_CMD_AST2500_PITCH_BMC, pitch);
+ cmds[0].cmd = cmd | FIELD_PREP(XDMA_CMD_AST2500_CMD_LINE_NO, line_no) |
+ FIELD_PREP(XDMA_CMD_AST2500_CMD_LINE_SIZE, line_size);
+ cmds[0].reserved = 0ULL;
+
+ print_hex_dump_debug("xdma cmd ", DUMP_PREFIX_OFFSET, 16, 1, cmds,
+ sizeof(*cmds), true);
+
+ return rc;
+}
+
+static unsigned int aspeed_xdma_ast2600_set_cmd(struct aspeed_xdma *ctx,
+ struct aspeed_xdma_cmd cmds[2],
+ struct aspeed_xdma_op *op,
+ u32 bmc_addr)
+{
+ unsigned int rc = 1;
+ unsigned int pitch = 1;
+ unsigned int line_no = 1;
+ unsigned int line_size = op->len;
+ u64 cmd = XDMA_CMD_AST2600_CMD_IRQ_BMC |
+ (op->direction ? XDMA_CMD_AST2600_CMD_UPSTREAM : 0);
+
+ if (op->host_addr & 0xffffffff00000000ULL ||
+ (op->host_addr + (u64)op->len) & 0xffffffff00000000ULL)
+ cmd |= XDMA_CMD_AST2600_CMD_64_EN;
+
+ dev_dbg(ctx->dev, "xdma %s ast2600: bmc[%08x] len[%08x] "
+ "host[%016llx]\n", op->direction ? "upstream" : "downstream",
+ bmc_addr, op->len, op->host_addr);
+
+ if (op->len > XDMA_CMD_AST2600_CMD_LINE_SIZE) {
+ unsigned int rem;
+ unsigned int total;
+
+ line_no = op->len / XDMA_CMD_AST2600_CMD_MULTILINE_SIZE;
+ total = XDMA_CMD_AST2600_CMD_MULTILINE_SIZE * line_no;
+ rem = op->len - total;
+ line_size = XDMA_CMD_AST2600_CMD_MULTILINE_SIZE;
+ pitch = line_size;
+
+ if (rem) {
+ u32 rbmc = bmc_addr + total;
+
+ cmds[1].host_addr = op->host_addr + (u64)total;
+ cmds[1].pitch =
+ ((u64)rbmc & XDMA_CMD_AST2600_PITCH_ADDR) |
+ FIELD_PREP(XDMA_CMD_AST2600_PITCH_HOST, 1) |
+ FIELD_PREP(XDMA_CMD_AST2600_PITCH_BMC, 1);
+ cmds[1].cmd = cmd |
+ FIELD_PREP(XDMA_CMD_AST2600_CMD_LINE_NO, 1) |
+ FIELD_PREP(XDMA_CMD_AST2600_CMD_LINE_SIZE,
+ rem);
+ cmds[1].reserved = 0ULL;
+
+ print_hex_dump_debug("xdma rem ", DUMP_PREFIX_OFFSET,
+ 16, 1, &cmds[1], sizeof(*cmds),
+ true);
+
+ cmd &= ~XDMA_CMD_AST2600_CMD_IRQ_BMC;
+
+ rc++;
+ }
+ }
+
+ cmds[0].host_addr = op->host_addr;
+ cmds[0].pitch = ((u64)bmc_addr & XDMA_CMD_AST2600_PITCH_ADDR) |
+ FIELD_PREP(XDMA_CMD_AST2600_PITCH_HOST, pitch) |
+ FIELD_PREP(XDMA_CMD_AST2600_PITCH_BMC, pitch);
+ cmds[0].cmd = cmd | FIELD_PREP(XDMA_CMD_AST2600_CMD_LINE_NO, line_no) |
+ FIELD_PREP(XDMA_CMD_AST2600_CMD_LINE_SIZE, line_size);
+ cmds[0].reserved = 0ULL;
+
+ print_hex_dump_debug("xdma cmd ", DUMP_PREFIX_OFFSET, 16, 1, cmds,
+ sizeof(*cmds), true);
+
+ return rc;
+}
+
+static int aspeed_xdma_start(struct aspeed_xdma *ctx, unsigned int num_cmds,
+ struct aspeed_xdma_cmd cmds[2], bool upstream,
+ struct aspeed_xdma_client *client)
+{
+ unsigned int i;
+ int rc = -EBUSY;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ctx->engine_lock, flags);
+ if (ctx->in_reset)
+ goto unlock;
+
+ spin_lock(&ctx->client_lock);
+ if (ctx->current_client) {
+ spin_unlock(&ctx->client_lock);
+ goto unlock;
+ }
+
+ client->error = false;
+ client->in_progress = true;
+ ctx->current_client = client;
+ spin_unlock(&ctx->client_lock);
+
+ ctx->upstream = upstream;
+ for (i = 0; i < num_cmds; ++i) {
+ /*
+ * Use memcpy_toio here to get some barriers before starting
+ * the operation. The command(s) need to be in physical memory
+ * before the XDMA engine starts.
+ */
+ memcpy_toio(&ctx->cmdq[ctx->cmd_idx], &cmds[i],
+ sizeof(struct aspeed_xdma_cmd));
+ ctx->cmd_idx = (ctx->cmd_idx + 1) % XDMA_NUM_CMDS;
+ }
+
+ aspeed_xdma_writel(ctx, ctx->chip->regs.bmc_cmdq_writep,
+ ctx->cmd_idx * ctx->chip->queue_entry_size);
+ rc = 0;
+
+unlock:
+ spin_unlock_irqrestore(&ctx->engine_lock, flags);
+ return rc;
+}
+
+static void aspeed_xdma_done(struct aspeed_xdma *ctx, bool error)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&ctx->client_lock, flags);
+ if (ctx->current_client) {
+ ctx->current_client->error = error;
+ ctx->current_client->in_progress = false;
+ ctx->current_client = NULL;
+ }
+ spin_unlock_irqrestore(&ctx->client_lock, flags);
+
+ wake_up_interruptible_all(&ctx->wait);
+}
+
+static irqreturn_t aspeed_xdma_irq(int irq, void *arg)
+{
+ struct aspeed_xdma *ctx = arg;
+ u32 status;
+
+ spin_lock(&ctx->engine_lock);
+ status = aspeed_xdma_readl(ctx, ctx->chip->regs.status);
+
+ if (status & ctx->chip->status_bits.ds_dirty) {
+ aspeed_xdma_done(ctx, true);
+ } else {
+ if (status & ctx->chip->status_bits.us_comp) {
+ if (ctx->upstream)
+ aspeed_xdma_done(ctx, false);
+ }
+
+ if (status & ctx->chip->status_bits.ds_comp) {
+ if (!ctx->upstream)
+ aspeed_xdma_done(ctx, false);
+ }
+ }
+
+ aspeed_xdma_writel(ctx, ctx->chip->regs.status, status);
+ spin_unlock(&ctx->engine_lock);
+
+ return IRQ_HANDLED;
+}
+
+static void aspeed_xdma_reset(struct aspeed_xdma *ctx)
+{
+ unsigned long flags;
+
+ reset_control_assert(ctx->reset);
+ usleep_range(XDMA_ENGINE_SETUP_TIME_MIN_US,
+ XDMA_ENGINE_SETUP_TIME_MAX_US);
+ reset_control_deassert(ctx->reset);
+ usleep_range(XDMA_ENGINE_SETUP_TIME_MIN_US,
+ XDMA_ENGINE_SETUP_TIME_MAX_US);
+
+ aspeed_xdma_init_eng(ctx);
+
+ aspeed_xdma_done(ctx, true);
+
+ spin_lock_irqsave(&ctx->engine_lock, flags);
+ ctx->in_reset = false;
+ spin_unlock_irqrestore(&ctx->engine_lock, flags);
+
+ wake_up_interruptible(&ctx->wait);
+}
+
+static void aspeed_xdma_reset_work(struct work_struct *work)
+{
+ struct aspeed_xdma *ctx = container_of(work, struct aspeed_xdma,
+ reset_work);
+
+ aspeed_xdma_reset(ctx);
+}
+
+static irqreturn_t aspeed_xdma_pcie_irq(int irq, void *arg)
+{
+ struct aspeed_xdma *ctx = arg;
+
+ dev_dbg(ctx->dev, "PCI-E reset requested.\n");
+
+ spin_lock(&ctx->engine_lock);
+ if (ctx->in_reset) {
+ spin_unlock(&ctx->engine_lock);
+ return IRQ_HANDLED;
+ }
+
+ ctx->in_reset = true;
+ spin_unlock(&ctx->engine_lock);
+
+ schedule_work(&ctx->reset_work);
+ return IRQ_HANDLED;
+}
+
+static int aspeed_xdma_init_scu(struct aspeed_xdma *ctx, struct device *dev)
+{
+ struct regmap *scu = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "aspeed,scu");
+
+ if (!IS_ERR(scu)) {
+ u32 selection;
+ bool pcie_device_bmc = true;
+ const u32 bmc = SCU_PCIE_CONF_BMC_EN |
+ SCU_PCIE_CONF_BMC_EN_MSI | SCU_PCIE_CONF_BMC_EN_IRQ |
+ SCU_PCIE_CONF_BMC_EN_DMA;
+ const u32 vga = SCU_PCIE_CONF_VGA_EN |
+ SCU_PCIE_CONF_VGA_EN_MSI | SCU_PCIE_CONF_VGA_EN_IRQ |
+ SCU_PCIE_CONF_VGA_EN_DMA;
+ const char *pcie = NULL;
+
+ if (!of_property_read_string(dev->of_node,
+ "aspeed,pcie-device", &pcie)) {
+ if (!strcmp(pcie, "vga")) {
+ pcie_device_bmc = false;
+ } else if (strcmp(pcie, "bmc")) {
+ dev_err(dev,
+ "Invalid pcie-device property %s.\n",
+ pcie);
+ return -EINVAL;
+ }
+ }
+
+ if (pcie_device_bmc) {
+ selection = bmc;
+ regmap_write(scu, ctx->chip->scu_bmc_class,
+ SCU_BMC_CLASS_REV_XDMA);
+ } else {
+ selection = vga;
+ }
+
+ regmap_update_bits(scu, ctx->chip->scu_pcie_conf, bmc | vga,
+ selection);
+
+ if (ctx->chip->scu_misc_ctrl) {
+ regmap_update_bits(scu, ctx->chip->scu_misc_ctrl,
+ SCU_AST2600_MISC_CTRL_XDMA_BMC,
+ SCU_AST2600_MISC_CTRL_XDMA_BMC);
+
+ /* Allow XDMA to be used on AST2600 */
+ regmap_update_bits(scu, SCU_AST2600_DEBUG_CTRL,
+ DEBUG_CTRL_XDMA_DISABLE, 0);
+ }
+ } else {
+ dev_warn(dev, "Unable to configure PCIe: %ld; continuing.\n",
+ PTR_ERR(scu));
+ }
+
+ return 0;
+}
+
+static void aspeed_xdma_kobject_release(struct kobject *kobj)
+{
+ struct aspeed_xdma *ctx = container_of(kobj, struct aspeed_xdma, kobj);
+
+ if (ctx->pcie_irq >= 0)
+ free_irq(ctx->pcie_irq, ctx);
+
+ gen_pool_free(ctx->pool, (unsigned long)ctx->cmdq, XDMA_CMDQ_SIZE);
+
+ gen_pool_destroy(ctx->pool);
+
+ dma_free_coherent(ctx->dev, ctx->mem_size, ctx->mem_virt,
+ ctx->mem_coherent);
+
+ if (ctx->reset_rc)
+ reset_control_put(ctx->reset_rc);
+ reset_control_put(ctx->reset);
+
+ clk_put(ctx->clock);
+
+ free_irq(ctx->irq, ctx);
+
+ iounmap(ctx->base);
+ release_mem_region(ctx->res_start, ctx->res_size);
+
+ kfree(ctx);
+}
+
+static struct kobj_type aspeed_xdma_kobject_type = {
+ .release = aspeed_xdma_kobject_release,
+};
+
+static int aspeed_xdma_iomap(struct aspeed_xdma *ctx,
+ struct platform_device *pdev)
+{
+ resource_size_t size;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ if (!res)
+ return -ENOMEM;
+
+ size = resource_size(res);
+ if (!request_mem_region(res->start, size, dev_name(ctx->dev)))
+ return -ENOMEM;
+
+ ctx->base = ioremap(res->start, size);
+ if (!ctx->base) {
+ release_mem_region(res->start, size);
+ return -ENOMEM;
+ }
+
+ ctx->res_start = res->start;
+ ctx->res_size = size;
+
+ return 0;
+}
+
+static int aspeed_xdma_probe(struct platform_device *pdev)
+{
+ int rc;
+ struct aspeed_xdma *ctx;
+ struct reserved_mem *mem;
+ struct device *dev = &pdev->dev;
+ struct device_node *memory_region;
+ const void *md = of_device_get_match_data(dev);
+
+ if (!md)
+ return -ENODEV;
+
+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ ctx->chip = md;
+ ctx->dev = dev;
+ platform_set_drvdata(pdev, ctx);
+ spin_lock_init(&ctx->client_lock);
+ spin_lock_init(&ctx->engine_lock);
+ INIT_WORK(&ctx->reset_work, aspeed_xdma_reset_work);
+ init_waitqueue_head(&ctx->wait);
+
+ rc = aspeed_xdma_iomap(ctx, pdev);
+ if (rc) {
+ dev_err(dev, "Failed to map registers.\n");
+ goto err_nomap;
+ }
+
+ ctx->irq = platform_get_irq(pdev, 0);
+ if (ctx->irq < 0) {
+ dev_err(dev, "Failed to find IRQ.\n");
+ rc = ctx->irq;
+ goto err_noirq;
+ }
+
+ rc = request_irq(ctx->irq, aspeed_xdma_irq, 0, DEVICE_NAME, ctx);
+ if (rc < 0) {
+ dev_err(dev, "Failed to request IRQ %d.\n", ctx->irq);
+ goto err_noirq;
+ }
+
+ ctx->clock = clk_get(dev, NULL);
+ if (IS_ERR(ctx->clock)) {
+ dev_err(dev, "Failed to request clock.\n");
+ rc = PTR_ERR(ctx->clock);
+ goto err_noclk;
+ }
+
+ ctx->reset = reset_control_get_exclusive(dev, NULL);
+ if (IS_ERR(ctx->reset)) {
+ dev_err(dev, "Failed to request reset control.\n");
+ rc = PTR_ERR(ctx->reset);
+ goto err_noreset;
+ }
+
+ ctx->reset_rc = reset_control_get_exclusive(dev, "root-complex");
+ if (IS_ERR(ctx->reset_rc)) {
+ dev_dbg(dev, "Failed to request reset RC control.\n");
+ ctx->reset_rc = NULL;
+ }
+
+ memory_region = of_parse_phandle(dev->of_node, "memory-region", 0);
+ if (!memory_region) {
+ dev_err(dev, "Failed to find memory-region.\n");
+ rc = -ENOMEM;
+ goto err_nomem;
+ }
+
+ mem = of_reserved_mem_lookup(memory_region);
+ of_node_put(memory_region);
+ if (!mem) {
+ dev_err(dev, "Failed to find reserved memory.\n");
+ rc = -ENOMEM;
+ goto err_nomem;
+ }
+
+ ctx->mem_phys = mem->base;
+ ctx->mem_size = mem->size;
+
+ rc = of_reserved_mem_device_init(dev);
+ if (rc) {
+ dev_err(dev, "Failed to init reserved memory.\n");
+ goto err_nomem;
+ }
+
+ rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
+ if (rc) {
+ dev_err(dev, "Failed to mask DMA.\n");
+ goto err_nomem;
+ }
+
+ ctx->mem_virt = dma_alloc_coherent(dev, ctx->mem_size,
+ &ctx->mem_coherent, 0);
+ if (!ctx->mem_virt) {
+ dev_err(dev, "Failed to allocate reserved memory.\n");
+ rc = -ENOMEM;
+ goto err_nomem;
+ }
+
+ ctx->pool = gen_pool_create(ilog2(PAGE_SIZE), -1);
+ if (!ctx->pool) {
+ dev_err(dev, "Failed to setup genalloc pool.\n");
+ rc = -ENOMEM;
+ goto err_nopool;
+ }
+
+ rc = gen_pool_add_virt(ctx->pool, (unsigned long)ctx->mem_virt,
+ ctx->mem_phys, ctx->mem_size, -1);
+ if (rc) {
+ dev_err(ctx->dev, "Failed to add memory to genalloc pool.\n");
+ goto err_pool_scu_clk;
+ }
+
+ rc = aspeed_xdma_init_scu(ctx, dev);
+ if (rc)
+ goto err_pool_scu_clk;
+
+ rc = clk_prepare_enable(ctx->clock);
+ if (rc) {
+ dev_err(dev, "Failed to enable the clock.\n");
+ goto err_pool_scu_clk;
+ }
+
+ if (ctx->reset_rc) {
+ rc = reset_control_deassert(ctx->reset_rc);
+ if (rc) {
+ dev_err(dev, "Failed to clear the RC reset.\n");
+ goto err_reset_rc;
+ }
+ usleep_range(XDMA_ENGINE_SETUP_TIME_MIN_US,
+ XDMA_ENGINE_SETUP_TIME_MAX_US);
+ }
+
+ rc = reset_control_deassert(ctx->reset);
+ if (rc) {
+ dev_err(dev, "Failed to clear the reset.\n");
+ goto err_reset;
+ }
+ usleep_range(XDMA_ENGINE_SETUP_TIME_MIN_US,
+ XDMA_ENGINE_SETUP_TIME_MAX_US);
+
+ ctx->cmdq = gen_pool_dma_alloc(ctx->pool, XDMA_CMDQ_SIZE,
+ &ctx->cmdq_phys);
+ if (!ctx->cmdq) {
+ dev_err(ctx->dev, "Failed to genalloc cmdq.\n");
+ rc = -ENOMEM;
+ goto err_pool;
+ }
+
+ aspeed_xdma_init_eng(ctx);
+
+ /*
+ * This interrupt could fire immediately so only request it once the
+ * engine and driver are initialized.
+ */
+ ctx->pcie_irq = platform_get_irq(pdev, 1);
+ if (ctx->pcie_irq < 0) {
+ dev_warn(dev, "Failed to find PCI-E IRQ.\n");
+ } else {
+ rc = request_irq(ctx->pcie_irq, aspeed_xdma_pcie_irq,
+ IRQF_SHARED, DEVICE_NAME, ctx);
+ if (rc < 0) {
+ dev_warn(dev, "Failed to request PCI-E IRQ %d.\n", rc);
+ ctx->pcie_irq = -1;
+ }
+ }
+
+ kobject_init(&ctx->kobj, &aspeed_xdma_kobject_type);
+ return 0;
+
+err_misc:
+ gen_pool_free(ctx->pool, (unsigned long)ctx->cmdq, XDMA_CMDQ_SIZE);
+err_pool:
+ reset_control_assert(ctx->reset);
+err_reset:
+ if (ctx->reset_rc)
+ reset_control_assert(ctx->reset_rc);
+err_reset_rc:
+ clk_disable_unprepare(ctx->clock);
+err_pool_scu_clk:
+ gen_pool_destroy(ctx->pool);
+err_nopool:
+ dma_free_coherent(ctx->dev, ctx->mem_size, ctx->mem_virt,
+ ctx->mem_coherent);
+err_nomem:
+ if (ctx->reset_rc)
+ reset_control_put(ctx->reset_rc);
+ reset_control_put(ctx->reset);
+err_noreset:
+ clk_put(ctx->clock);
+err_noclk:
+ free_irq(ctx->irq, ctx);
+err_noirq:
+ iounmap(ctx->base);
+ release_mem_region(ctx->res_start, ctx->res_size);
+err_nomap:
+ kfree(ctx);
+ return rc;
+}
+
+static void aspeed_xdma_remove(struct platform_device *pdev)
+{
+ struct aspeed_xdma *ctx = platform_get_drvdata(pdev);
+
+ reset_control_assert(ctx->reset);
+ if (ctx->reset_rc)
+ reset_control_assert(ctx->reset_rc);
+ clk_disable_unprepare(ctx->clock);
+
+ aspeed_xdma_done(ctx, true);
+
+ misc_deregister(&ctx->misc);
+ kobject_put(&ctx->kobj);
+}
+
+static const struct aspeed_xdma_chip aspeed_ast2500_xdma_chip = {
+ .control = XDMA_AST2500_CTRL_US_COMP | XDMA_AST2500_CTRL_DS_COMP |
+ XDMA_AST2500_CTRL_DS_DIRTY | XDMA_AST2500_CTRL_DS_SIZE_256 |
+ XDMA_AST2500_CTRL_DS_TIMEOUT | XDMA_AST2500_CTRL_DS_CHECK_ID,
+ .scu_bmc_class = SCU_AST2500_BMC_CLASS_REV,
+ .scu_misc_ctrl = 0,
+ .scu_pcie_conf = SCU_AST2500_PCIE_CONF,
+ .queue_entry_size = XDMA_AST2500_QUEUE_ENTRY_SIZE,
+ .regs = {
+ .bmc_cmdq_addr = XDMA_AST2500_BMC_CMDQ_ADDR,
+ .bmc_cmdq_endp = XDMA_AST2500_BMC_CMDQ_ENDP,
+ .bmc_cmdq_writep = XDMA_AST2500_BMC_CMDQ_WRITEP,
+ .bmc_cmdq_readp = XDMA_AST2500_BMC_CMDQ_READP,
+ .control = XDMA_AST2500_CTRL,
+ .status = XDMA_AST2500_STATUS,
+ },
+ .status_bits = {
+ .us_comp = XDMA_AST2500_STATUS_US_COMP,
+ .ds_comp = XDMA_AST2500_STATUS_DS_COMP,
+ .ds_dirty = XDMA_AST2500_STATUS_DS_DIRTY,
+ },
+ .set_cmd = aspeed_xdma_ast2500_set_cmd,
+};
+
+static const struct aspeed_xdma_chip aspeed_ast2600_xdma_chip = {
+ .control = XDMA_AST2600_CTRL_US_COMP | XDMA_AST2600_CTRL_DS_COMP |
+ XDMA_AST2600_CTRL_DS_DIRTY | XDMA_AST2600_CTRL_DS_SIZE_256,
+ .scu_bmc_class = SCU_AST2600_BMC_CLASS_REV,
+ .scu_misc_ctrl = SCU_AST2600_MISC_CTRL,
+ .scu_pcie_conf = SCU_AST2600_PCIE_CONF,
+ .queue_entry_size = XDMA_AST2600_QUEUE_ENTRY_SIZE,
+ .regs = {
+ .bmc_cmdq_addr = XDMA_AST2600_BMC_CMDQ_ADDR,
+ .bmc_cmdq_endp = XDMA_AST2600_BMC_CMDQ_ENDP,
+ .bmc_cmdq_writep = XDMA_AST2600_BMC_CMDQ_WRITEP,
+ .bmc_cmdq_readp = XDMA_AST2600_BMC_CMDQ_READP,
+ .control = XDMA_AST2600_CTRL,
+ .status = XDMA_AST2600_STATUS,
+ },
+ .status_bits = {
+ .us_comp = XDMA_AST2600_STATUS_US_COMP,
+ .ds_comp = XDMA_AST2600_STATUS_DS_COMP,
+ .ds_dirty = XDMA_AST2600_STATUS_DS_DIRTY,
+ },
+ .set_cmd = aspeed_xdma_ast2600_set_cmd,
+};
+
+static const struct of_device_id aspeed_xdma_match[] = {
+ {
+ .compatible = "aspeed,ast2500-xdma",
+ .data = &aspeed_ast2500_xdma_chip,
+ },
+ {
+ .compatible = "aspeed,ast2600-xdma",
+ .data = &aspeed_ast2600_xdma_chip,
+ },
+ { },
+};
+
+static struct platform_driver aspeed_xdma_driver = {
+ .probe = aspeed_xdma_probe,
+ .remove = aspeed_xdma_remove,
+ .driver = {
+ .name = DEVICE_NAME,
+ .of_match_table = aspeed_xdma_match,
+ },
+};
+
+module_platform_driver(aspeed_xdma_driver);
+
+MODULE_AUTHOR("Eddie James");
+MODULE_DESCRIPTION("ASPEED XDMA Engine Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/uapi/linux/aspeed-xdma.h b/include/uapi/linux/aspeed-xdma.h
new file mode 100644
index 0000000000000..2efaa6067c39b
--- /dev/null
+++ b/include/uapi/linux/aspeed-xdma.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
+/* Copyright IBM Corp 2019 */
+
+#ifndef _UAPI_LINUX_ASPEED_XDMA_H_
+#define _UAPI_LINUX_ASPEED_XDMA_H_
+
+#include <linux/types.h>
+
+/*
+ * aspeed_xdma_direction
+ *
+ * ASPEED_XDMA_DIRECTION_DOWNSTREAM: transfers data from the host to the BMC
+ *
+ * ASPEED_XDMA_DIRECTION_UPSTREAM: transfers data from the BMC to the host
+ */
+enum aspeed_xdma_direction {
+ ASPEED_XDMA_DIRECTION_DOWNSTREAM = 0,
+ ASPEED_XDMA_DIRECTION_UPSTREAM,
+};
+
+/*
+ * aspeed_xdma_op
+ *
+ * host_addr: the DMA address on the host side, typically configured by PCI
+ * subsystem
+ *
+ * len: the size of the transfer in bytes
+ *
+ * direction: an enumerator indicating the direction of the DMA operation; see
+ * enum aspeed_xdma_direction
+ */
+struct aspeed_xdma_op {
+ __u64 host_addr;
+ __u32 len;
+ __u32 direction;
+};
+
+#endif /* _UAPI_LINUX_ASPEED_XDMA_H_ */
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH linux dev-6.12 v1 1/6] soc: aspeed: Add XDMA Engine Driver
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 1/6] soc: aspeed: Add XDMA Engine Driver Ninad Palsule
@ 2025-09-03 2:14 ` Andrew Jeffery
0 siblings, 0 replies; 8+ messages in thread
From: Andrew Jeffery @ 2025-09-03 2:14 UTC (permalink / raw)
To: Ninad Palsule, openbmc, joel, eajames; +Cc: Andrew Jeffery
On Tue, 2025-09-02 at 13:31 -0500, Ninad Palsule wrote:
> From: Eddie James <eajames@linux.ibm.com>
>
> The XDMA engine embedded in the AST2500 and AST2600 SOCs performs PCI
> DMA operations between the SOC (acting as a BMC) and a host processor
> in a server.
>
> This commit adds a driver to control the XDMA engine and adds functions
> to initialize the hardware and memory and start DMA operations.
>
> Signed-off-by: Eddie James <eajames@linux.ibm.com>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Link: https://lore.kernel.org/r/1588697905-23444-3-git-send-email-eajames@linux.ibm.com
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
> ---
> MAINTAINERS | 2 +
> drivers/soc/aspeed/Kconfig | 10 +
> drivers/soc/aspeed/Makefile | 1 +
> drivers/soc/aspeed/aspeed-xdma.c | 961 +++++++++++++++++++++++++++++++
> include/uapi/linux/aspeed-xdma.h | 38 ++
> 5 files changed, 1012 insertions(+)
> create mode 100644 drivers/soc/aspeed/aspeed-xdma.c
> create mode 100644 include/uapi/linux/aspeed-xdma.h
Applying this to dev-6.12 and building it for aspeed_g5_defconfig
produces:
../drivers/soc/aspeed/aspeed-xdma.c: In function ‘aspeed_xdma_probe’:
../drivers/soc/aspeed/aspeed-xdma.c:844:1: warning: label ‘err_misc’ defined but not used [-Wunused-label]
844 | err_misc:
| ^~~~~~~~
../drivers/soc/aspeed/aspeed-xdma.c: In function ‘aspeed_xdma_remove’:
../drivers/soc/aspeed/aspeed-xdma.c:885:9: error: implicit declaration of function ‘misc_deregister’; did you mean ‘bus_unregister’? [-Werror=implicit-function-declaration]
885 | misc_deregister(&ctx->misc);
| ^~~~~~~~~~~~~~~
| bus_unregister
../drivers/soc/aspeed/aspeed-xdma.c:885:29: error: ‘struct aspeed_xdma’ has no member named ‘misc’
885 | misc_deregister(&ctx->misc);
| ^~
../drivers/soc/aspeed/aspeed-xdma.c: At top level:
../drivers/soc/aspeed/aspeed-xdma.c:423:12: warning: ‘aspeed_xdma_start’ defined but not used [-Wunused-function]
423 | static int aspeed_xdma_start(struct aspeed_xdma *ctx, unsigned int num_cmds,
| ^~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
make[6]: *** [../scripts/Makefile.build:229: drivers/soc/aspeed/aspeed-xdma.o] Error 1
make[5]: *** [../scripts/Makefile.build:478: drivers/soc/aspeed] Error 2
make[4]: *** [../scripts/Makefile.build:478: drivers/soc] Error 2
make[4]: *** Waiting for unfinished jobs....
Can you please fix these?
Also, during application, checkpatch complained:
✓ [PATCH v1 1/6] soc: aspeed: Add XDMA Engine Driver
+ Link: https://patch.msgid.link/20250902183155.2988560-2-ninad@linux.ibm.com
+ Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
● checkpatch.pl: 164: WARNING: please write a help paragraph that fully describes the config symbol
● checkpatch.pl: 228: WARNING: please, no space before tabs
● checkpatch.pl: 563: WARNING: quoted string split across lines
● checkpatch.pl: 834: WARNING: struct kobj_type should normally be const
● checkpatch.pl: 959: WARNING: Possible unnecessary 'out of memory' message
● checkpatch.pl: 1152: WARNING: Prefer "GPL" over "GPL v2" - see commit bf7fbeeae6db ("module: Cure the MODULE_LICENSE "GPL" vs. "GPL v2" bogosity")
Can you please address these as well when posting v2?
Thanks,
Andrew
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH linux dev-6.12 v1 2/6] soc: aspeed: xdma: Add user interface
2025-09-02 18:31 [PATCH linux dev-6.12 v1 0/6] Port linux fixes from dev-6.6 Ninad Palsule
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 1/6] soc: aspeed: Add XDMA Engine Driver Ninad Palsule
@ 2025-09-02 18:31 ` Ninad Palsule
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 3/6] soc: aspeed: xdma: Add reset ioctl Ninad Palsule
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Ninad Palsule @ 2025-09-02 18:31 UTC (permalink / raw)
To: openbmc, andrew, joel, eajames; +Cc: ninad, Andrew Jeffery
From: Eddie James <eajames@linux.ibm.com>
This commits adds a miscdevice to provide a user interface to the XDMA
engine. The interface provides the write operation to start DMA
operations. The DMA parameters are passed as the data to the write call.
The actual data to transfer is NOT passed through write. Note that both
directions of DMA operation are accomplished through the write command;
BMC to host and host to BMC.
The XDMA driver reserves an area of physical memory for DMA operations,
as the XDMA engine is restricted to accessing certain physical memory
areas on some platforms. This memory forms a pool from which users can
allocate pages for their usage with calls to mmap. The space allocated
by a client will be the space used in the DMA operation. For an
"upstream" (BMC to host) operation, the data in the client's area will
be transferred to the host. For a "downstream" (host to BMC) operation,
the host data will be placed in the client's memory area.
Poll is also provided in order to determine when the DMA operation is
complete for non-blocking IO.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/1588697905-23444-4-git-send-email-eajames@linux.ibm.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/soc/aspeed/aspeed-xdma.c | 217 +++++++++++++++++++++++++++++++
1 file changed, 217 insertions(+)
diff --git a/drivers/soc/aspeed/aspeed-xdma.c b/drivers/soc/aspeed/aspeed-xdma.c
index fae8ebb09203c..584038e69d49e 100644
--- a/drivers/soc/aspeed/aspeed-xdma.c
+++ b/drivers/soc/aspeed/aspeed-xdma.c
@@ -13,6 +13,7 @@
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/mfd/syscon.h>
+#include <linux/miscdevice.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_device.h>
@@ -238,6 +239,8 @@ struct aspeed_xdma {
dma_addr_t mem_coherent;
dma_addr_t cmdq_phys;
struct gen_pool *pool;
+
+ struct miscdevice misc;
};
struct aspeed_xdma_client {
@@ -556,6 +559,210 @@ static irqreturn_t aspeed_xdma_pcie_irq(int irq, void *arg)
return IRQ_HANDLED;
}
+static ssize_t aspeed_xdma_write(struct file *file, const char __user *buf,
+ size_t len, loff_t *offset)
+{
+ int rc;
+ unsigned int num_cmds;
+ struct aspeed_xdma_op op;
+ struct aspeed_xdma_cmd cmds[2];
+ struct aspeed_xdma_client *client = file->private_data;
+ struct aspeed_xdma *ctx = client->ctx;
+
+ if (len != sizeof(op))
+ return -EINVAL;
+
+ if (copy_from_user(&op, buf, len))
+ return -EFAULT;
+
+ if (!op.len || op.len > client->size ||
+ op.direction > ASPEED_XDMA_DIRECTION_UPSTREAM)
+ return -EINVAL;
+
+ num_cmds = ctx->chip->set_cmd(ctx, cmds, &op, client->phys);
+ do {
+ rc = aspeed_xdma_start(ctx, num_cmds, cmds, !!op.direction,
+ client);
+ if (!rc)
+ break;
+
+ if ((file->f_flags & O_NONBLOCK) || rc != -EBUSY)
+ return rc;
+
+ rc = wait_event_interruptible(ctx->wait,
+ !(ctx->current_client ||
+ ctx->in_reset));
+ } while (!rc);
+
+ if (rc)
+ return -EINTR;
+
+ if (!(file->f_flags & O_NONBLOCK)) {
+ rc = wait_event_interruptible(ctx->wait, !client->in_progress);
+ if (rc)
+ return -EINTR;
+
+ if (client->error)
+ return -EIO;
+ }
+
+ return len;
+}
+
+static __poll_t aspeed_xdma_poll(struct file *file,
+ struct poll_table_struct *wait)
+{
+ __poll_t mask = 0;
+ __poll_t req = poll_requested_events(wait);
+ struct aspeed_xdma_client *client = file->private_data;
+ struct aspeed_xdma *ctx = client->ctx;
+
+ if (req & (EPOLLIN | EPOLLRDNORM)) {
+ if (READ_ONCE(client->in_progress))
+ poll_wait(file, &ctx->wait, wait);
+
+ if (!READ_ONCE(client->in_progress)) {
+ if (READ_ONCE(client->error))
+ mask |= EPOLLERR;
+ else
+ mask |= EPOLLIN | EPOLLRDNORM;
+ }
+ }
+
+ if (req & (EPOLLOUT | EPOLLWRNORM)) {
+ if (READ_ONCE(ctx->current_client))
+ poll_wait(file, &ctx->wait, wait);
+
+ if (!READ_ONCE(ctx->current_client))
+ mask |= EPOLLOUT | EPOLLWRNORM;
+ }
+
+ return mask;
+}
+
+static void aspeed_xdma_vma_close(struct vm_area_struct *vma)
+{
+ int rc;
+ struct aspeed_xdma_client *client = vma->vm_private_data;
+
+ rc = wait_event_interruptible(client->ctx->wait, !client->in_progress);
+ if (rc)
+ return;
+
+ gen_pool_free(client->ctx->pool, (unsigned long)client->virt,
+ client->size);
+
+ client->virt = NULL;
+ client->phys = 0;
+ client->size = 0;
+}
+
+static const struct vm_operations_struct aspeed_xdma_vm_ops = {
+ .close = aspeed_xdma_vma_close,
+};
+
+static int aspeed_xdma_mmap(struct file *file, struct vm_area_struct *vma)
+{
+ int rc;
+ struct aspeed_xdma_client *client = file->private_data;
+ struct aspeed_xdma *ctx = client->ctx;
+
+ /* restrict file to one mapping */
+ if (client->size)
+ return -EBUSY;
+
+ client->size = vma->vm_end - vma->vm_start;
+ client->virt = gen_pool_dma_alloc(ctx->pool, client->size,
+ &client->phys);
+ if (!client->virt) {
+ client->phys = 0;
+ client->size = 0;
+ return -ENOMEM;
+ }
+
+ vma->vm_pgoff = (client->phys - ctx->mem_phys) >> PAGE_SHIFT;
+ vma->vm_ops = &aspeed_xdma_vm_ops;
+ vma->vm_private_data = client;
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+ rc = io_remap_pfn_range(vma, vma->vm_start, client->phys >> PAGE_SHIFT,
+ client->size, vma->vm_page_prot);
+ if (rc) {
+ dev_warn(ctx->dev, "mmap err: v[%08lx] to p[%08x], s[%08x]\n",
+ vma->vm_start, (u32)client->phys, client->size);
+
+ gen_pool_free(ctx->pool, (unsigned long)client->virt,
+ client->size);
+
+ client->virt = NULL;
+ client->phys = 0;
+ client->size = 0;
+ return rc;
+ }
+
+ dev_dbg(ctx->dev, "mmap: v[%08lx] to p[%08x], s[%08x]\n",
+ vma->vm_start, (u32)client->phys, client->size);
+
+ return 0;
+}
+
+static int aspeed_xdma_open(struct inode *inode, struct file *file)
+{
+ struct miscdevice *misc = file->private_data;
+ struct aspeed_xdma *ctx = container_of(misc, struct aspeed_xdma, misc);
+ struct aspeed_xdma_client *client = kzalloc(sizeof(*client),
+ GFP_KERNEL);
+
+ if (!client)
+ return -ENOMEM;
+
+ kobject_get(&ctx->kobj);
+ client->ctx = ctx;
+ file->private_data = client;
+ return 0;
+}
+
+static int aspeed_xdma_release(struct inode *inode, struct file *file)
+{
+ bool reset = false;
+ unsigned long flags;
+ struct aspeed_xdma_client *client = file->private_data;
+ struct aspeed_xdma *ctx = client->ctx;
+
+ spin_lock_irqsave(&ctx->client_lock, flags);
+ if (client == ctx->current_client) {
+ spin_lock(&ctx->engine_lock);
+ if (ctx->in_reset) {
+ ctx->current_client = NULL;
+ } else {
+ ctx->in_reset = true;
+ reset = true;
+ }
+ spin_unlock(&ctx->engine_lock);
+ }
+ spin_unlock_irqrestore(&ctx->client_lock, flags);
+
+ if (reset)
+ aspeed_xdma_reset(ctx);
+
+ if (client->virt)
+ gen_pool_free(ctx->pool, (unsigned long)client->virt,
+ client->size);
+
+ kfree(client);
+ kobject_put(&ctx->kobj);
+ return 0;
+}
+
+static const struct file_operations aspeed_xdma_fops = {
+ .owner = THIS_MODULE,
+ .write = aspeed_xdma_write,
+ .poll = aspeed_xdma_poll,
+ .mmap = aspeed_xdma_mmap,
+ .open = aspeed_xdma_open,
+ .release = aspeed_xdma_release,
+};
+
static int aspeed_xdma_init_scu(struct aspeed_xdma *ctx, struct device *dev)
{
struct regmap *scu = syscon_regmap_lookup_by_phandle(dev->of_node,
@@ -822,6 +1029,16 @@ static int aspeed_xdma_probe(struct platform_device *pdev)
aspeed_xdma_init_eng(ctx);
+ ctx->misc.minor = MISC_DYNAMIC_MINOR;
+ ctx->misc.fops = &aspeed_xdma_fops;
+ ctx->misc.name = "aspeed-xdma";
+ ctx->misc.parent = dev;
+ rc = misc_register(&ctx->misc);
+ if (rc) {
+ dev_err(dev, "Failed to register xdma miscdevice.\n");
+ goto err_misc;
+ }
+
/*
* This interrupt could fire immediately so only request it once the
* engine and driver are initialized.
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH linux dev-6.12 v1 3/6] soc: aspeed: xdma: Add reset ioctl
2025-09-02 18:31 [PATCH linux dev-6.12 v1 0/6] Port linux fixes from dev-6.6 Ninad Palsule
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 1/6] soc: aspeed: Add XDMA Engine Driver Ninad Palsule
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 2/6] soc: aspeed: xdma: Add user interface Ninad Palsule
@ 2025-09-02 18:31 ` Ninad Palsule
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 4/6] soc: aspeed: xdma: Add trace events Ninad Palsule
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Ninad Palsule @ 2025-09-02 18:31 UTC (permalink / raw)
To: openbmc, andrew, joel, eajames; +Cc: ninad, Andrew Jeffery
From: Eddie James <eajames@linux.ibm.com>
Users of the XDMA engine need a way to reset it if something goes wrong.
Problems on the host side, or user error, such as incorrect host
address, may result in the DMA operation never completing and no way to
determine what went wrong. Therefore, add an ioctl to reset the engine
so that users can recover in this situation.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/1588697905-23444-5-git-send-email-eajames@linux.ibm.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/soc/aspeed/aspeed-xdma.c | 32 ++++++++++++++++++++++++++++++++
include/uapi/linux/aspeed-xdma.h | 4 ++++
2 files changed, 36 insertions(+)
diff --git a/drivers/soc/aspeed/aspeed-xdma.c b/drivers/soc/aspeed/aspeed-xdma.c
index 584038e69d49e..565486ddb3b52 100644
--- a/drivers/soc/aspeed/aspeed-xdma.c
+++ b/drivers/soc/aspeed/aspeed-xdma.c
@@ -640,6 +640,37 @@ static __poll_t aspeed_xdma_poll(struct file *file,
return mask;
}
+static long aspeed_xdma_ioctl(struct file *file, unsigned int cmd,
+ unsigned long param)
+{
+ unsigned long flags;
+ struct aspeed_xdma_client *client = file->private_data;
+ struct aspeed_xdma *ctx = client->ctx;
+
+ switch (cmd) {
+ case ASPEED_XDMA_IOCTL_RESET:
+ spin_lock_irqsave(&ctx->engine_lock, flags);
+ if (ctx->in_reset) {
+ spin_unlock_irqrestore(&ctx->engine_lock, flags);
+ return 0;
+ }
+
+ ctx->in_reset = true;
+ spin_unlock_irqrestore(&ctx->engine_lock, flags);
+
+ if (READ_ONCE(ctx->current_client))
+ dev_warn(ctx->dev,
+ "User reset with transfer in progress.\n");
+
+ aspeed_xdma_reset(ctx);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static void aspeed_xdma_vma_close(struct vm_area_struct *vma)
{
int rc;
@@ -758,6 +789,7 @@ static const struct file_operations aspeed_xdma_fops = {
.owner = THIS_MODULE,
.write = aspeed_xdma_write,
.poll = aspeed_xdma_poll,
+ .unlocked_ioctl = aspeed_xdma_ioctl,
.mmap = aspeed_xdma_mmap,
.open = aspeed_xdma_open,
.release = aspeed_xdma_release,
diff --git a/include/uapi/linux/aspeed-xdma.h b/include/uapi/linux/aspeed-xdma.h
index 2efaa6067c39b..3a3646fd1e9ec 100644
--- a/include/uapi/linux/aspeed-xdma.h
+++ b/include/uapi/linux/aspeed-xdma.h
@@ -4,8 +4,12 @@
#ifndef _UAPI_LINUX_ASPEED_XDMA_H_
#define _UAPI_LINUX_ASPEED_XDMA_H_
+#include <linux/ioctl.h>
#include <linux/types.h>
+#define __ASPEED_XDMA_IOCTL_MAGIC 0xb7
+#define ASPEED_XDMA_IOCTL_RESET _IO(__ASPEED_XDMA_IOCTL_MAGIC, 0)
+
/*
* aspeed_xdma_direction
*
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH linux dev-6.12 v1 4/6] soc: aspeed: xdma: Add trace events
2025-09-02 18:31 [PATCH linux dev-6.12 v1 0/6] Port linux fixes from dev-6.6 Ninad Palsule
` (2 preceding siblings ...)
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 3/6] soc: aspeed: xdma: Add reset ioctl Ninad Palsule
@ 2025-09-02 18:31 ` Ninad Palsule
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 5/6] i2c: core: Add mux root adapter operations Ninad Palsule
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 6/6] iio: si7020: Lock root adapter to wait for reset Ninad Palsule
5 siblings, 0 replies; 8+ messages in thread
From: Ninad Palsule @ 2025-09-02 18:31 UTC (permalink / raw)
To: openbmc, andrew, joel, eajames; +Cc: ninad, Andrew Jeffery
From: Eddie James <eajames@linux.ibm.com>
Trace the flow of the driver to aid debugging after an error.
OpenBMC-Staging-Count: 6
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20220412215331.42491-1-eajames@linux.ibm.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/soc/aspeed/aspeed-xdma.c | 18 +++-
include/trace/events/xdma.h | 139 +++++++++++++++++++++++++++++++
2 files changed, 155 insertions(+), 2 deletions(-)
create mode 100644 include/trace/events/xdma.h
diff --git a/drivers/soc/aspeed/aspeed-xdma.c b/drivers/soc/aspeed/aspeed-xdma.c
index 565486ddb3b52..33310e55eb1ce 100644
--- a/drivers/soc/aspeed/aspeed-xdma.c
+++ b/drivers/soc/aspeed/aspeed-xdma.c
@@ -253,6 +253,9 @@ struct aspeed_xdma_client {
u32 size;
};
+#define CREATE_TRACE_POINTS
+#include <trace/events/xdma.h>
+
static u32 aspeed_xdma_readl(struct aspeed_xdma *ctx, u8 reg)
{
u32 v = readl(ctx->base + reg);
@@ -448,6 +451,7 @@ static int aspeed_xdma_start(struct aspeed_xdma *ctx, unsigned int num_cmds,
ctx->upstream = upstream;
for (i = 0; i < num_cmds; ++i) {
+ trace_xdma_start(ctx, &cmds[i]);
/*
* Use memcpy_toio here to get some barriers before starting
* the operation. The command(s) need to be in physical memory
@@ -490,6 +494,8 @@ static irqreturn_t aspeed_xdma_irq(int irq, void *arg)
spin_lock(&ctx->engine_lock);
status = aspeed_xdma_readl(ctx, ctx->chip->regs.status);
+ trace_xdma_irq(status);
+
if (status & ctx->chip->status_bits.ds_dirty) {
aspeed_xdma_done(ctx, true);
} else {
@@ -514,6 +520,8 @@ static void aspeed_xdma_reset(struct aspeed_xdma *ctx)
{
unsigned long flags;
+ trace_xdma_reset(ctx);
+
reset_control_assert(ctx->reset);
usleep_range(XDMA_ENGINE_SETUP_TIME_MIN_US,
XDMA_ENGINE_SETUP_TIME_MAX_US);
@@ -544,7 +552,7 @@ static irqreturn_t aspeed_xdma_pcie_irq(int irq, void *arg)
{
struct aspeed_xdma *ctx = arg;
- dev_dbg(ctx->dev, "PCI-E reset requested.\n");
+ trace_xdma_perst(ctx);
spin_lock(&ctx->engine_lock);
if (ctx->in_reset) {
@@ -682,6 +690,7 @@ static void aspeed_xdma_vma_close(struct vm_area_struct *vma)
gen_pool_free(client->ctx->pool, (unsigned long)client->virt,
client->size);
+ trace_xdma_unmap(client);
client->virt = NULL;
client->phys = 0;
@@ -706,6 +715,7 @@ static int aspeed_xdma_mmap(struct file *file, struct vm_area_struct *vma)
client->virt = gen_pool_dma_alloc(ctx->pool, client->size,
&client->phys);
if (!client->virt) {
+ trace_xdma_mmap_error(client, 0UL);
client->phys = 0;
client->size = 0;
return -ENOMEM;
@@ -725,12 +735,14 @@ static int aspeed_xdma_mmap(struct file *file, struct vm_area_struct *vma)
gen_pool_free(ctx->pool, (unsigned long)client->virt,
client->size);
+ trace_xdma_mmap_error(client, vma->vm_start);
client->virt = NULL;
client->phys = 0;
client->size = 0;
return rc;
}
+ trace_xdma_mmap(client);
dev_dbg(ctx->dev, "mmap: v[%08lx] to p[%08x], s[%08x]\n",
vma->vm_start, (u32)client->phys, client->size);
@@ -776,9 +788,11 @@ static int aspeed_xdma_release(struct inode *inode, struct file *file)
if (reset)
aspeed_xdma_reset(ctx);
- if (client->virt)
+ if (client->virt) {
gen_pool_free(ctx->pool, (unsigned long)client->virt,
client->size);
+ trace_xdma_unmap(client);
+ }
kfree(client);
kobject_put(&ctx->kobj);
diff --git a/include/trace/events/xdma.h b/include/trace/events/xdma.h
new file mode 100644
index 0000000000000..bf515ad3d8e50
--- /dev/null
+++ b/include/trace/events/xdma.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM xdma
+
+#if !defined(_TRACE_XDMA_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_XDMA_H
+
+#include <linux/tracepoint.h>
+
+TRACE_EVENT(xdma_start,
+ TP_PROTO(const struct aspeed_xdma *ctx, const struct aspeed_xdma_cmd *cmd),
+ TP_ARGS(ctx, cmd),
+ TP_STRUCT__entry(
+ __field(bool, dir_upstream)
+ __field(unsigned int, index)
+ __field(__u64, host)
+ __field(__u64, pitch)
+ __field(__u64, cmd)
+ ),
+ TP_fast_assign(
+ __entry->dir_upstream = ctx->upstream;
+ __entry->index = ctx->cmd_idx;
+ __entry->host = cmd->host_addr;
+ __entry->pitch = cmd->pitch;
+ __entry->cmd = cmd->cmd;
+ ),
+ TP_printk("%s cmd:%u [%08llx %016llx %016llx]",
+ __entry->dir_upstream ? "upstream" : "downstream",
+ __entry->index,
+ __entry->host,
+ __entry->pitch,
+ __entry->cmd
+ )
+);
+
+TRACE_EVENT(xdma_irq,
+ TP_PROTO(u32 sts),
+ TP_ARGS(sts),
+ TP_STRUCT__entry(
+ __field(__u32, status)
+ ),
+ TP_fast_assign(
+ __entry->status = sts;
+ ),
+ TP_printk("sts:%08x",
+ __entry->status
+ )
+);
+
+TRACE_EVENT(xdma_reset,
+ TP_PROTO(const struct aspeed_xdma *ctx),
+ TP_ARGS(ctx),
+ TP_STRUCT__entry(
+ __field(bool, dir_upstream)
+ __field(bool, in_progress)
+ ),
+ TP_fast_assign(
+ __entry->dir_upstream = ctx->upstream;
+ __entry->in_progress =
+ ctx->current_client ? ctx->current_client->in_progress : false;
+ ),
+ TP_printk("%sin progress%s",
+ __entry->in_progress ? "" : "not ",
+ __entry->in_progress ? (__entry->dir_upstream ? " upstream" : " downstream") : ""
+ )
+);
+
+TRACE_EVENT(xdma_perst,
+ TP_PROTO(const struct aspeed_xdma *ctx),
+ TP_ARGS(ctx),
+ TP_STRUCT__entry(
+ __field(bool, in_reset)
+ ),
+ TP_fast_assign(
+ __entry->in_reset = ctx->in_reset;
+ ),
+ TP_printk("%s",
+ __entry->in_reset ? "in reset" : ""
+ )
+);
+
+TRACE_EVENT(xdma_unmap,
+ TP_PROTO(const struct aspeed_xdma_client *client),
+ TP_ARGS(client),
+ TP_STRUCT__entry(
+ __field(__u32, phys)
+ __field(__u32, size)
+ ),
+ TP_fast_assign(
+ __entry->phys = client->phys;
+ __entry->size = client->size;
+ ),
+ TP_printk("p:%08x s:%08x",
+ __entry->phys,
+ __entry->size
+ )
+);
+
+TRACE_EVENT(xdma_mmap_error,
+ TP_PROTO(const struct aspeed_xdma_client *client, unsigned long vm_start),
+ TP_ARGS(client, vm_start),
+ TP_STRUCT__entry(
+ __field(__u32, phys)
+ __field(__u32, size)
+ __field(unsigned long, vm_start)
+ ),
+ TP_fast_assign(
+ __entry->phys = client->phys;
+ __entry->size = client->size;
+ __entry->vm_start = vm_start;
+ ),
+ TP_printk("p:%08x s:%08x v:%08lx",
+ __entry->phys,
+ __entry->size,
+ __entry->vm_start
+ )
+);
+
+TRACE_EVENT(xdma_mmap,
+ TP_PROTO(const struct aspeed_xdma_client *client),
+ TP_ARGS(client),
+ TP_STRUCT__entry(
+ __field(__u32, phys)
+ __field(__u32, size)
+ ),
+ TP_fast_assign(
+ __entry->phys = client->phys;
+ __entry->size = client->size;
+ ),
+ TP_printk("p:%08x s:%08x",
+ __entry->phys,
+ __entry->size
+ )
+);
+
+#endif /* _TRACE_XDMA_H */
+
+#include <trace/define_trace.h>
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH linux dev-6.12 v1 5/6] i2c: core: Add mux root adapter operations
2025-09-02 18:31 [PATCH linux dev-6.12 v1 0/6] Port linux fixes from dev-6.6 Ninad Palsule
` (3 preceding siblings ...)
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 4/6] soc: aspeed: xdma: Add trace events Ninad Palsule
@ 2025-09-02 18:31 ` Ninad Palsule
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 6/6] iio: si7020: Lock root adapter to wait for reset Ninad Palsule
5 siblings, 0 replies; 8+ messages in thread
From: Ninad Palsule @ 2025-09-02 18:31 UTC (permalink / raw)
To: openbmc, andrew, joel, eajames; +Cc: ninad
From: Eddie James <eajames@linux.ibm.com>
Some I2C clients need the ability to control the root I2C bus even if the
endpoint device is behind a mux. For example, a driver for a chip that
can't handle any I2C traffic on the bus while coming out of reset
(including an I2C-driven mux switching channels) may need to lock the root
bus with the mux selection fixed for the entire time the device is in
reset.
For this purpose, add a new structure containing two function pointers to
the adapter structure. These functions pointers should be defined for
every adapter. The lock_select operation, for a mux adapter, locks the
parent adpaters up to the root and selects the adapter's channel. The
unlock_deselect operation deselects the mux channel and unlocks all the
adapters. For a non-mux adapter, the operations lock and unlock the
adapters up to the root. This scheme should work with multiple levels of
muxes and regular adapters in between.
OpenBMC-Staging-Count: 4
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220906202829.1921114-2-eajames@linux.ibm.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/i2c/i2c-core-base.c | 38 ++++++++++++++++++++++++++++
drivers/i2c/i2c-mux.c | 50 +++++++++++++++++++++++++++++++++++++
include/linux/i2c.h | 42 +++++++++++++++++++++++++++++++
3 files changed, 130 insertions(+)
diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
index 75d30861ffe21..0e60f24521220 100644
--- a/drivers/i2c/i2c-core-base.c
+++ b/drivers/i2c/i2c-core-base.c
@@ -1430,6 +1430,41 @@ static const struct i2c_lock_operations i2c_adapter_lock_ops = {
.unlock_bus = i2c_adapter_unlock_bus,
};
+/*
+ * For a non-mux adapter, the lock_select operation locks the chain of
+ * adapters upwards, returning the root. If there's a mux above this adapter
+ * somehow, it should also get locked and the desired channel selected.
+ */
+static struct i2c_adapter *i2c_adapter_lock_select(struct i2c_adapter *adapter)
+{
+ struct i2c_adapter *ret = adapter;
+ struct i2c_adapter *parent = i2c_parent_is_i2c_adapter(adapter);
+
+ if (parent) {
+ ret = parent->mux_root_ops->lock_select(parent);
+ if (IS_ERR(ret))
+ return ret;
+ }
+
+ adapter->lock_ops->lock_bus(adapter, I2C_LOCK_ROOT_ADAPTER);
+ return ret;
+}
+
+static void i2c_adapter_unlock_deselect(struct i2c_adapter *adapter)
+{
+ struct i2c_adapter *parent = i2c_parent_is_i2c_adapter(adapter);
+
+ adapter->lock_ops->unlock_bus(adapter, I2C_LOCK_ROOT_ADAPTER);
+
+ if (parent)
+ parent->mux_root_ops->unlock_deselect(parent);
+}
+
+static const struct i2c_mux_root_operations i2c_adapter_mux_root_ops = {
+ .lock_select = i2c_adapter_lock_select,
+ .unlock_deselect = i2c_adapter_unlock_deselect,
+};
+
static void i2c_host_notify_irq_teardown(struct i2c_adapter *adap)
{
struct irq_domain *domain = adap->host_notify_domain;
@@ -1527,6 +1562,9 @@ static int i2c_register_adapter(struct i2c_adapter *adap)
if (!adap->lock_ops)
adap->lock_ops = &i2c_adapter_lock_ops;
+ if (!adap->mux_root_ops)
+ adap->mux_root_ops = &i2c_adapter_mux_root_ops;
+
adap->locked_flags = 0;
rt_mutex_init(&adap->bus_lock);
rt_mutex_init(&adap->mux_lock);
diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c
index fda72e8be8850..3ba9a8beb7685 100644
--- a/drivers/i2c/i2c-mux.c
+++ b/drivers/i2c/i2c-mux.c
@@ -197,6 +197,49 @@ static void i2c_parent_unlock_bus(struct i2c_adapter *adapter,
rt_mutex_unlock(&parent->mux_lock);
}
+/*
+ * For a mux adapter, the lock_select operation first locks just like the
+ * lock_bus operation. Then it selects the channel for this adapter and
+ * returns the root adapter. If there is another mux above this one, calling
+ * the parent lock_select should ensure that the channel is correctly
+ * selected.
+ */
+static struct i2c_adapter *i2c_mux_lock_select(struct i2c_adapter *adapter)
+{
+ int ret;
+ struct i2c_mux_priv *priv = adapter->algo_data;
+ struct i2c_mux_core *muxc = priv->muxc;
+ struct i2c_adapter *parent = muxc->parent;
+
+ rt_mutex_lock_nested(&parent->mux_lock, i2c_adapter_depth(adapter));
+
+ adapter = parent->mux_root_ops->lock_select(parent);
+ if (IS_ERR(adapter))
+ return adapter;
+
+ ret = muxc->select(muxc, priv->chan_id);
+ if (ret < 0) {
+ parent->mux_root_ops->unlock_deselect(parent);
+ rt_mutex_unlock(&parent->mux_lock);
+ return ERR_PTR(ret);
+ }
+
+ return adapter;
+}
+
+static void i2c_mux_unlock_deselect(struct i2c_adapter *adapter)
+{
+ struct i2c_mux_priv *priv = adapter->algo_data;
+ struct i2c_mux_core *muxc = priv->muxc;
+ struct i2c_adapter *parent = muxc->parent;
+
+ if (muxc->deselect)
+ muxc->deselect(muxc, priv->chan_id);
+
+ parent->mux_root_ops->unlock_deselect(parent);
+ rt_mutex_unlock(&parent->mux_lock);
+}
+
struct i2c_adapter *i2c_root_adapter(struct device *dev)
{
struct device *i2c;
@@ -267,6 +310,11 @@ static const struct i2c_lock_operations i2c_parent_lock_ops = {
.unlock_bus = i2c_parent_unlock_bus,
};
+static const struct i2c_mux_root_operations i2c_mux_root_ops = {
+ .lock_select = i2c_mux_lock_select,
+ .unlock_deselect = i2c_mux_unlock_deselect,
+};
+
int i2c_mux_add_adapter(struct i2c_mux_core *muxc,
u32 force_nr, u32 chan_id)
{
@@ -326,6 +374,8 @@ int i2c_mux_add_adapter(struct i2c_mux_core *muxc,
else
priv->adap.lock_ops = &i2c_parent_lock_ops;
+ priv->adap.mux_root_ops = &i2c_mux_root_ops;
+
/*
* Try to populate the mux adapter's of_node, expands to
* nothing if !CONFIG_OF.
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 388ce71a29a97..3081a48b9ec67 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -595,6 +595,26 @@ struct i2c_lock_operations {
void (*unlock_bus)(struct i2c_adapter *adapter, unsigned int flags);
};
+/**
+ * struct i2c_mux_root_operations - represent operations to lock and select
+ * the adapter's mux channel (if a mux is present)
+ * @lock_select: Get exclusive access to the root I2C bus adapter with the
+ * correct mux channel selected for the adapter
+ * @unlock_deslect: Release exclusive access to the root I2C bus adapter and
+ * deselect the mux channel for the adapter
+ *
+ * Some I2C clients need the ability to control the root I2C bus even if the
+ * endpoint device is behind a mux. For example, a driver for a chip that
+ * can't handle any I2C traffic on the bus while coming out of reset (including
+ * an I2C-driven mux switching channels) may need to lock the root bus with
+ * the mux selection fixed for the entire time the device is in reset.
+ * These operations are for such a purpose.
+ */
+struct i2c_mux_root_operations {
+ struct i2c_adapter *(*lock_select)(struct i2c_adapter *adapter);
+ void (*unlock_deselect)(struct i2c_adapter *adapter);
+};
+
/**
* struct i2c_timings - I2C timing information
* @bus_freq_hz: the bus frequency in Hz
@@ -737,6 +757,7 @@ struct i2c_adapter {
/* data fields that are valid for all devices */
const struct i2c_lock_operations *lock_ops;
+ const struct i2c_mux_root_operations *mux_root_ops;
struct rt_mutex bus_lock;
struct rt_mutex mux_lock;
@@ -834,6 +855,27 @@ i2c_unlock_bus(struct i2c_adapter *adapter, unsigned int flags)
adapter->lock_ops->unlock_bus(adapter, flags);
}
+/**
+ * i2c_lock_select_bus - Get exclusive access to the root I2C bus with the
+ * target's mux channel (if a mux is present) selected.
+ * @adapter: Target I2C bus
+ *
+ * Return the root I2C bus if mux selection succeeds, an ERR_PTR otherwise
+ */
+static inline struct i2c_adapter *i2c_lock_select_bus(struct i2c_adapter *adapter)
+{
+ return adapter->mux_root_ops->lock_select(adapter);
+}
+
+/**
+ * i2c_unlock_deselect_bus - Release exclusive access to the root I2C bus
+ * @adapter: Target I2C bus
+ */
+static inline void i2c_unlock_deselect_bus(struct i2c_adapter *adapter)
+{
+ adapter->mux_root_ops->unlock_deselect(adapter);
+}
+
/**
* i2c_mark_adapter_suspended - Report suspended state of the adapter to the core
* @adap: Adapter to mark as suspended
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH linux dev-6.12 v1 6/6] iio: si7020: Lock root adapter to wait for reset
2025-09-02 18:31 [PATCH linux dev-6.12 v1 0/6] Port linux fixes from dev-6.6 Ninad Palsule
` (4 preceding siblings ...)
2025-09-02 18:31 ` [PATCH linux dev-6.12 v1 5/6] i2c: core: Add mux root adapter operations Ninad Palsule
@ 2025-09-02 18:31 ` Ninad Palsule
5 siblings, 0 replies; 8+ messages in thread
From: Ninad Palsule @ 2025-09-02 18:31 UTC (permalink / raw)
To: openbmc, andrew, joel, eajames; +Cc: ninad
From: Eddie James <eajames@linux.ibm.com>
Use the new mux root operations to lock the root adapter while waiting for
the reset to complete. I2C commands issued after the SI7020 is starting up
or after reset can potentially upset the startup sequence. Therefore, the
host needs to wait for the startup sequence to finish before issuing
further I2C commands.
OpenBMC-Staging-Count: 4
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Link: https://lore.kernel.org/r/20220906202829.1921114-3-eajames@linux.ibm.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/iio/humidity/si7020.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/humidity/si7020.c b/drivers/iio/humidity/si7020.c
index ff2dba50c0a5b..7f24d54beb8d0 100644
--- a/drivers/iio/humidity/si7020.c
+++ b/drivers/iio/humidity/si7020.c
@@ -228,6 +228,7 @@ static const struct iio_info si7020_info = {
static int si7020_probe(struct i2c_client *client)
{
+ struct i2c_adapter *root;
struct iio_dev *indio_dev;
struct si7020_data *data;
int ret;
@@ -237,13 +238,24 @@ static int si7020_probe(struct i2c_client *client)
I2C_FUNC_SMBUS_READ_WORD_DATA))
return -EOPNOTSUPP;
+ root = i2c_lock_select_bus(client->adapter);
+ if (IS_ERR(root))
+ return PTR_ERR(root);
+
/* Reset device, loads default settings. */
- ret = i2c_smbus_write_byte(client, SI7020CMD_RESET);
- if (ret < 0)
+ ret = __i2c_smbus_xfer(root, client->addr, client->flags,
+ I2C_SMBUS_WRITE, SI7020CMD_RESET,
+ I2C_SMBUS_BYTE, NULL);
+ if (ret < 0) {
+ i2c_unlock_deselect_bus(client->adapter);
return ret;
+ }
+
/* Wait the maximum power-up time after software reset. */
msleep(15);
+ i2c_unlock_deselect_bus(client->adapter);
+
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread