RE: [PATCH 0/7] soc: aspeed: Add AST2600 eSPI controller support

YH Chung
2026-03-27T04:15:08Z

Hi Arnd,

> - For the HW-mode-only peripherals (memory, LPC), is there any
> driver interaction at all for setting it up, or is this completely
> transparent to Linux running on the BMC?

For LPC-style IO accesses like Post Code Capture (PCC), the accesses are
completely transparent to Linux.

For memory accesses, they are also transparent to Linux on the BMC. It just
requires configuring the translation from the bus address to a reserved
memory region on the BMC during driver probe.

> - For the other devices running in SW mode, is the interface that the
> driver sees abstract in the sense that the same low-level code
> is shared for all of them, or are these still separate functional
> blocks that each need their own register-level interface?

The channels are distinct functional blocks within the eSPI controller, each
using its own channel-specific registers regardless of whether they operate
in HW or SW mode. There is no common message flow or registers for the
software modes. The eSPI controller dispatches eSPI messages to the relevant
channel's hardware function block, which then takes action according to its
mode configuration.

Some low-level framework code may be shareable, for example a unified ISR
entry that checks interrupt status register and routes to channel-specific
handlers, but the corresponding handling will be channel-specific.

Thanks,
Yun Hsuan