[PATCH u-boot v2 1/2] drivers: spi: Add support for disabling FMC_WDT2 for aspeed

Marc Olberding
2025-12-02T23:53:43Z

Adds support for disabling the ast2600 FMC_WDT2 through
a device tree entry in the fmc node.
Set `aspeed,watchdog-disable` in your device tree to have
the driver disable it.

Signed-off-by: Marc Olberding <molberding@nvidia.com>
---
drivers/spi/aspeed_spi.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/aspeed_spi.c b/drivers/spi/aspeed_spi.c
index 54520122f1c48c8b2052b4b1e47445a9b990d25e..de954e477aa15e6d1be042a2aee47f5a501178da 100644
--- a/drivers/spi/aspeed_spi.c
+++ b/drivers/spi/aspeed_spi.c
@@ -30,14 +30,16 @@ struct aspeed_spi_regs {
/* 0x30 .. 0x38 Segment Address */
u32 _reserved1[5]; /* .. */
u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */
- u32 _reserved2[11]; /* .. */
+ u32 _reserved2[4]; /* .. */
+ u32 wdt2_ctrl; /* 0x64 FMC_WDT2 control */
+ u32 _reserved3[6]; /* .. */
u32 dma_ctrl; /* 0x80 DMA Control/Status */
u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */
u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */
u32 dma_len; /* 0x8c DMA Length Register */
u32 dma_checksum; /* 0x90 Checksum Calculation Result */
u32 timings; /* 0x94 Read Timing Compensation */
- u32 _reserved3[1];
+ u32 _reserved4[1];
/* not used */
u32 soft_strap_status; /* 0x9c Software Strap Status */
u32 write_cmd_filter_ctrl; /* 0xa0 Write Command Filter Control */
@@ -45,7 +47,7 @@ struct aspeed_spi_regs {
u32 lock_ctrl_reset; /* 0xa8 Lock Control (SRST#) */
u32 lock_ctrl_wdt; /* 0xac Lock Control (Watchdog) */
u32 write_addr_filter[8]; /* 0xb0 Write Address Filter */
- u32 _reserved4[12];
+ u32 _reserved5[12];
u32 fully_qualified_cmd[20]; /* 0x100 Fully Qualified Command */
u32 addr_qualified_cmd[12]; /* 0x150 Address Qualified Command */
};
@@ -163,7 +165,8 @@ struct aspeed_spi_regs {
#define SPI_3B_AUTO_CLR_REG 0x1e6e2510
#define SPI_3B_AUTO_CLR BIT(9)

-
+/* FMC_WDT2 control register */
+#define WDT2_ENABLE BIT(0)
/*
* flash related info
*/
@@ -267,6 +270,7 @@ struct aspeed_spi_priv {
ulong hclk_rate; /* AHB clock rate */
u8 num_cs;
bool is_fmc;
+ bool disable_wdt;

struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS];
u32 flash_count;
@@ -683,6 +687,9 @@ static int aspeed_spi_controller_init(struct aspeed_spi_priv *priv)
setbits_le32(&priv->regs->conf,
CONF_ENABLE_W2 | CONF_ENABLE_W1 | CONF_ENABLE_W0);

+ if (priv->is_fmc && priv->disable_wdt)
+ clrbits_le32(&priv->regs->wdt2_ctrl, WDT2_ENABLE);
+
/*
* Set safe default settings for each device. These will be
* tuned after the SPI flash devices are probed.
@@ -1907,6 +1914,10 @@ static int aspeed_spi_probe(struct udevice *bus)
* SPI controllers
*/
priv->is_fmc = dev_get_driver_data(bus);
+ if (device_is_compatible(bus, "aspeed,ast2600-fmc") &&
+ dev_read_bool(bus, "aspeed,watchdog-disable"))
+ priv->disable_wdt = true;
+

ret = aspeed_spi_controller_init(priv);
if (ret)

--
2.34.1