From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f194.google.com (mail-pf0-f194.google.com [209.85.192.194]) by mail.openembedded.org (Postfix) with ESMTP id A968771C7A for ; Fri, 10 Nov 2017 05:51:32 +0000 (UTC) Received: by mail-pf0-f194.google.com with SMTP id b79so6036074pfk.5 for ; Thu, 09 Nov 2017 21:51:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=3p8JWVkyyynQbZfM48VqRKB6wVbAxyUc402gUpOKHrw=; b=ux/gq8Gw5dqw2unARckPE2WRyDsbdGO0mDCtlIejLTQYtpTVvS4lxgcVjMSa8SVOlh 0Hvl9xMuM9XYFvP32Z+qAWI+pYvShR0QDIPEvt4h7ZkDzuX5v4WuEmamgcZEvfyKxqRV fRqV1st//gC56y0mB5YtO3Lyoj4xpj/57LGrU/D0506i8HWgwnIWsCBxr9V9ZswYqUBl J46Bsi+KYMHNe1aCgVeT7f30w+ANDjFmMXXta5bUzoM8r64gRhuuOq+kq7Ii/3nzVzz3 lOmNJFWsspbceFxft9BZLnw3FwpnNdQaOpR513pywo8ErGsQoyAfUm8cK18CFFIvcjX1 fuFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=3p8JWVkyyynQbZfM48VqRKB6wVbAxyUc402gUpOKHrw=; b=PoMEUGd1bEgG6Y9NVXssWWurt/ZlsCIAyQPWmM1Kldg1A+IbTc+hHpwPEKBOn5YSi7 CyD+66J79x3DQ3t0m94CZQLryNUFv42TUkVDesXHr9guMEopmaQwJYLnZpNsQihLktPL DRlPBp/BLZNCSQVC/LbOKIACMJSQYKL6+DXEzUxCXz5TG3HJuLU1T7+jhyR6t6FryhWE vS4tSZeaOho5qDm4EiVZFcvdanxvhUviArJrKIE+6csa52YXpe6JoXUckr4SbMrGNRu2 N83rew7hcODtyWtGOfcdEhmkTfaNc3ryFtPVkOcKgqjY6ekYqUKbxaNCEucwGxKeS2S+ iofA== X-Gm-Message-State: AJaThX7firO0hY8NWOs5xXpvNhWfk9yP6UQb3+/LGNpABSr/tyiDRUQO OdIL5vaPf3vya+Vgi+8m5KcDlQ== X-Google-Smtp-Source: ABhQp+SrNx4l+ibd6uBGT6q8pLNk6u385PxvE8jMwPxPprbg2X5l7N9bCzcSWxaUGymNzcRx/1O+ew== X-Received: by 10.84.132.42 with SMTP id 39mr2961778ple.382.1510293093848; Thu, 09 Nov 2017 21:51:33 -0800 (PST) Received: from e6520.gateway.sonic.net (173-228-90-28.dsl.dynamic.fusionbroadband.com. [173.228.90.28]) by smtp.gmail.com with ESMTPSA id u7sm14295437pfh.142.2017.11.09.21.51.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Nov 2017 21:51:32 -0800 (PST) From: Andre McCurdy To: openembedded-core@lists.openembedded.org Date: Thu, 9 Nov 2017 21:51:26 -0800 Message-Id: <1510293086-31666-1-git-send-email-armccurdy@gmail.com> X-Mailer: git-send-email 1.9.1 Subject: [PATCH] gcc6: enable FL_LPAE flag for armv7ve cores X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Nov 2017 05:51:33 -0000 The following commit added the FL_LPAE flag to FL_FOR_ARCH7VE, but neglected to also add it to the armv7ve compatible cores defined in arm-cores.def. https://github.com/gcc-mirror/gcc/commit/af2d9b9e58e8be576c53d94f30c48c68146b0c98 The result is that gcc 6.4 now refuses to allow -march=armv7ve and -mcpu=XXX to be used together, even when -mcpu is set to an armv7ve compatible core: arm-linux-gnueabi-gcc -march=armv7ve -mcpu=cortex-a7 -Werror ... error: switch -mcpu=cortex-a7 conflicts with -march=armv7ve switch [-Werror] Fix by defining flags for armv7ve compatible cores directly from FL_FOR_ARCH7VE, rather than re-creating the armv7ve flags independently by combining FL_FOR_ARCH7A with the armv7ve specific FL_THUMB_DIV and FL_ARM_DIV flags. Signed-off-by: Andre McCurdy --- meta/recipes-devtools/gcc/gcc-6.4.inc | 1 + ...001-enable-FL_LPAE-flag-for-armv7ve-cores.patch | 67 ++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 meta/recipes-devtools/gcc/gcc-6.4/backport/0001-enable-FL_LPAE-flag-for-armv7ve-cores.patch diff --git a/meta/recipes-devtools/gcc/gcc-6.4.inc b/meta/recipes-devtools/gcc/gcc-6.4.inc index a42b7d8..942b39f 100644 --- a/meta/recipes-devtools/gcc/gcc-6.4.inc +++ b/meta/recipes-devtools/gcc/gcc-6.4.inc @@ -80,6 +80,7 @@ SRC_URI = "\ " BACKPORTS = "\ file://CVE-2016-6131.patch \ + file://0001-enable-FL_LPAE-flag-for-armv7ve-cores.patch \ " SRC_URI[md5sum] = "11ba51a0cfb8471927f387c8895fe232" SRC_URI[sha256sum] = "850bf21eafdfe5cd5f6827148184c08c4a0852a37ccf36ce69855334d2c914d4" diff --git a/meta/recipes-devtools/gcc/gcc-6.4/backport/0001-enable-FL_LPAE-flag-for-armv7ve-cores.patch b/meta/recipes-devtools/gcc/gcc-6.4/backport/0001-enable-FL_LPAE-flag-for-armv7ve-cores.patch new file mode 100644 index 0000000..9ee029c --- /dev/null +++ b/meta/recipes-devtools/gcc/gcc-6.4/backport/0001-enable-FL_LPAE-flag-for-armv7ve-cores.patch @@ -0,0 +1,67 @@ +From 22fcc126fad61a8e9ddaaabbc8036644273642dc Mon Sep 17 00:00:00 2001 +From: ktkachov +Date: Thu, 9 Nov 2017 14:34:28 +0000 +Subject: [PATCH] enable FL_LPAE flag for armv7ve cores + +The following commit added the FL_LPAE flag to FL_FOR_ARCH7VE, but +neglected to also add it to the armv7ve compatible cores defined in +arm-cores.def. + + https://github.com/gcc-mirror/gcc/commit/af2d9b9e58e8be576c53d94f30c48c68146b0c98 + +The result is that gcc 6.4 now refuses to allow -march=armv7ve and +-mcpu=XXX to be used together, even when -mcpu is set to an armv7ve +compatible core: + + arm-linux-gnueabi-gcc -march=armv7ve -mcpu=cortex-a7 -Werror ... + error: switch -mcpu=cortex-a7 conflicts with -march=armv7ve switch [-Werror] + +Fix by defining flags for armv7ve compatible cores directly from +FL_FOR_ARCH7VE, rather than re-creating the armv7ve flags +independently by combining FL_FOR_ARCH7A with the armv7ve specific +FL_THUMB_DIV and FL_ARM_DIV flags. + +UpStream-Status: Backport + +git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-6-branch@254584 138bc75d-0d04-0410-961f-82ee72b054a4 + +Signed-off-by: Andre McCurdy +--- + gcc/config/arm/arm-cores.def | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def +index 829b839..ca37e6f 100644 +--- a/gcc/config/arm/arm-cores.def ++++ b/gcc/config/arm/arm-cores.def +@@ -145,12 +145,12 @@ ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, + /* V7 Architecture Processors */ + ARM_CORE("generic-armv7-a", genericv7a, genericv7a, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex) + ARM_CORE("cortex-a5", cortexa5, cortexa5, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a5) +-ARM_CORE("cortex-a7", cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7) ++ARM_CORE("cortex-a7", cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a7) + ARM_CORE("cortex-a8", cortexa8, cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a8) + ARM_CORE("cortex-a9", cortexa9, cortexa9, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a9) +-ARM_CORE("cortex-a12", cortexa12, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) +-ARM_CORE("cortex-a15", cortexa15, cortexa15, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15) +-ARM_CORE("cortex-a17", cortexa17, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) ++ARM_CORE("cortex-a12", cortexa12, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a12) ++ARM_CORE("cortex-a15", cortexa15, cortexa15, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a15) ++ARM_CORE("cortex-a17", cortexa17, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a12) + ARM_CORE("cortex-r4", cortexr4, cortexr4, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex) + ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex) + ARM_CORE("cortex-r5", cortexr5, cortexr5, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex) +@@ -162,8 +162,8 @@ ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | + ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), marvell_pj4) + + /* V7 big.LITTLE implementations */ +-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15) +-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) ++ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a15) ++ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a12) + + /* V8 Architecture Processors */ + ARM_CORE("cortex-a32", cortexa32, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35) +-- +1.9.1 + -- 1.9.1