[PATCH v2 1/2] u-boot: relocate SRC_URI_RISCV into recipe

["João Marcos Costa" <joaomarcos.costa@bootlin.com>]

In a custom u-boot recipe that requires u-boot-common.inc, the config
fragments end up in SRC_URI. However, the custom recipe's FILESPATH does
not contain the path to oe-core's u-boot directory (as expected), which
leads to the error below:

ERROR: .../build/../meta-custom/recipes-bsp/u-boot/u-boot-custom_2025.10.bb:
Unable to get checksum for u-boot-custom SRC_URI entry u-boot-riscv-isa_clear.cfg: file could not be found
The following paths were searched:
(...)

Move SRC_URI_RISCV - along with the appends - out of the common
definitions.

Signed-off-by: João Marcos Costa <joaomarcos.costa@bootlin.com>
---
 meta/recipes-bsp/u-boot/u-boot-common.inc | 12 ------------
 meta/recipes-bsp/u-boot/u-boot_2025.10.bb | 12 ++++++++++++
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/meta/recipes-bsp/u-boot/u-boot-common.inc b/meta/recipes-bsp/u-boot/u-boot-common.inc
index 93ff0ca6ca..08cd189f64 100644
--- a/meta/recipes-bsp/u-boot/u-boot-common.inc
+++ b/meta/recipes-bsp/u-boot/u-boot-common.inc
@@ -16,18 +16,6 @@ SRCREV = "e50b1e8715011def8aff1588081a2649a2c6cd47"
 
 SRC_URI = "git://source.denx.de/u-boot/u-boot.git;protocol=https;branch=master;tag=v${PV}"
 
-SRC_URI_RISCV = "\
-    file://u-boot-riscv-isa_clear.cfg \
-    ${@bb.utils.contains    ("TUNE_FEATURES", "a",      "file://u-boot-riscv-isa_a.cfg", "", d)} \
-    ${@bb.utils.contains    ("TUNE_FEATURES", "f",      "file://u-boot-riscv-isa_f.cfg", "", d)} \
-    ${@bb.utils.contains    ("TUNE_FEATURES", "d",      "file://u-boot-riscv-isa_d.cfg", "", d)} \
-    ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb",  "file://u-boot-riscv-isa_zbb.cfg", "", d)} \
-    ${@bb.utils.contains    ("TUNE_FEATURES", "zicbom", "file://u-boot-riscv-isa_zicbom.cfg", "", d)} \
-    "
-
-SRC_URI:append:riscv32 = "${SRC_URI_RISCV}"
-SRC_URI:append:riscv64 = "${SRC_URI_RISCV}"
-
 B = "${WORKDIR}/build"
 
 inherit pkgconfig
diff --git a/meta/recipes-bsp/u-boot/u-boot_2025.10.bb b/meta/recipes-bsp/u-boot/u-boot_2025.10.bb
index 25f264c961..5259fd5832 100644
--- a/meta/recipes-bsp/u-boot/u-boot_2025.10.bb
+++ b/meta/recipes-bsp/u-boot/u-boot_2025.10.bb
@@ -6,3 +6,15 @@ DEPENDS += "bc-native dtc-native gnutls-native python3-pyelftools-native"
 # workarounds for aarch64 kvm qemu boot regressions
 SRC_URI:append:qemuarm64 = " file://disable-CONFIG_BLOBLIST.cfg"
 SRC_URI:append:genericarm64 = " file://disable-CONFIG_BLOBLIST.cfg"
+
+SRC_URI_RISCV = "\
+    file://u-boot-riscv-isa_clear.cfg \
+    ${@bb.utils.contains    ("TUNE_FEATURES", "a",      "file://u-boot-riscv-isa_a.cfg", "", d)} \
+    ${@bb.utils.contains    ("TUNE_FEATURES", "f",      "file://u-boot-riscv-isa_f.cfg", "", d)} \
+    ${@bb.utils.contains    ("TUNE_FEATURES", "d",      "file://u-boot-riscv-isa_d.cfg", "", d)} \
+    ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb",  "file://u-boot-riscv-isa_zbb.cfg", "", d)} \
+    ${@bb.utils.contains    ("TUNE_FEATURES", "zicbom", "file://u-boot-riscv-isa_zicbom.cfg", "", d)} \
+    "
+
+SRC_URI:append:riscv32 = "${SRC_URI_RISCV}"
+SRC_URI:append:riscv64 = "${SRC_URI_RISCV}"
-- 
2.47.0