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([2601:646:8201:fd20:d1b7:aad6:2c95:a1d8]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b38ee479502sm14833562a12.21.2025.07.09.09.23.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Jul 2025 09:23:52 -0700 (PDT) Message-ID: <368a2856-e12a-45dc-940b-cfa269a4bc13@gmail.com> Date: Wed, 9 Jul 2025 09:23:51 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [OE-core] [PATCH v3 6/6] qemuriscv: Dynamically configure qemu CPU To: mark.hatle@kernel.crashing.org, openembedded-core@lists.openembedded.org References: <1751492664-12569-1-git-send-email-mark.hatle@kernel.crashing.org> <1751492664-12569-7-git-send-email-mark.hatle@kernel.crashing.org> <84caeee4b92dad27f67c745c63aaafbf9abb6c1b.camel@linuxfoundation.org> Content-Language: en-US From: Khem Raj In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 09 Jul 2025 16:23:55 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/220103 On 7/9/25 7:54 AM, Mark Hatle via lists.openembedded.org wrote: > I will investigate. > > I suspect SOME of this may be test cases with hard coded riscv assembly > in them using extensions that we've not enabled. > > The configuration listed in the logs for the kernel are: > > rv64imafdc > >  '[    0.000000] riscv: base ISA extensions acdfim\n' >  '[    0.000000] riscv: ELF capabilities acdfim\n' > > The 'v' (vector) extension is intentionally not enabled to match the > software configuration, but some tests may be trying to use it. > > I'll walk through this and attempt to get this identified for real. We should be enabling the rvb23 (rv64gcv) profile as default for qemu, since that is the baseline for a RISCV profile that OE will be used as base infrastructure and we should target that commonly, perhaps changing default tune for qemuriscv64 to consider that would be a good thing. I know there is a value in constructing the ISA+extension set that qemu emulates based on tune selection and whatever rv64gcv devolves down in terms of extensions. > > --Mark > > On 7/9/25 4:17 AM, Richard Purdie via lists.openembedded.org wrote: >> On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via >> lists.openembedded.org wrote: >>> From: Mark Hatle >>> >>> Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the >>> options selected by the DEFAULTTUNE. >>> >>> Note: OpenSBI currently requires 'c' (compressed instructions) or it >>> will >>> not work. >>> >>> Change the base device configuration to use a different variable to >>> select >>> the emulate devices.  This will allow a user to override or append the >>> QB_OPT_APPEND without the riscv32 override getting in the way. >>> >>> Signed-off-by: Mark Hatle >>> --- >>>   meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++-- >>>   1 file changed, 28 insertions(+), 3 deletions(-) >>> >> >> FWIW I narrowed down the ptest failures to this patch. >> >> Cheers, >> >> Richard >> >> >> >> >> > > > -=-=-=-=-=-=-=-=-=-=-=- > Links: You receive all messages sent to this group. > View/Reply Online (#220090): https://lists.openembedded.org/g/openembedded-core/message/220090 > Mute This Topic: https://lists.openembedded.org/mt/113956553/1997914 > Group Owner: openembedded-core+owner@lists.openembedded.org > Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub [raj.khem@gmail.com] > -=-=-=-=-=-=-=-=-=-=-=- >