From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f176.google.com (mail-pf0-f176.google.com [209.85.192.176]) by mail.openembedded.org (Postfix) with ESMTP id 8510B60745 for ; Thu, 24 Mar 2016 23:58:48 +0000 (UTC) Received: by mail-pf0-f176.google.com with SMTP id 4so69958439pfd.0 for ; Thu, 24 Mar 2016 16:58:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=subject:mime-version:from:in-reply-to:date:cc:message-id:references :to; bh=3gWfMb+4GKGbonyqCwJi1bRwY1zigEp0IW1pRZauc/A=; b=a2kvghgT0qsahsMJEIT7Hxs09eGs2DywNDeMiacA2Es0qm/3nc47PAOSlpN40sUa5D 1uY0edkAg/ApI6BjY3XTi56nL5SZZmak1jBHQoate0cfryP8jOziVW9B/TwYWTWyk683 OobuQlYKZ7JSq9Ymel3Bk/gGGfgQKnmpM7Nmo1MeOUJZqEN6iY85HrFgMHHTJRKvA5qo i5HW4IYDOfFAAxAOxN1K5kclhwn7OZ/3ZUakZ+/wB54dO8K3WrsVNsOxw2ZSMEkr1wBq nnPDGBBgjJxuxRgzflNbepNwhmWX8VGYO2cSKI/6T8Xn/F4eCKIas1Z9JGriVeIw3KEI UAEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:subject:mime-version:from:in-reply-to:date:cc :message-id:references:to; bh=3gWfMb+4GKGbonyqCwJi1bRwY1zigEp0IW1pRZauc/A=; b=MZEsVEJbp2ZIvAZWS7OHUzqf/EA905jPmShHTOvnIcISa6X7I7ae2wI5QtLA96MDJD jExrpZzWS5IuiMkklNLPKQTV3oVp7d/JZCMoUBjqYGSxMvULGN2JPJvRgFFYoB+uEIw4 GbTZLe+57IIIGAizuRh0FcDrpwLtUButzr6zrO/2liTkGeqKG41AamQR9s8oLOJIgxrI pSS+DpYdD8mO5fKokH7qTQDGx8/f5gb3Lv3f5uz7BBc0mg7LE3z8hAAEBaqOk8ccRD7r ZSOzvgLSwCY0oKJJ17DaAV6ZMaZ9fXyDC0PaiFrm0AwshfI7/U4KXLIV02EMl/bQYlcf k8hA== X-Gm-Message-State: AD7BkJJnJEspDg1EnIKgF9N/cf50u6DSlhjbO/lNIZKrOSsu1D9+fVxfj6Rv7Gkq+vMmDA== X-Received: by 10.98.79.203 with SMTP id f72mr16808156pfj.102.1458863928875; Thu, 24 Mar 2016 16:58:48 -0700 (PDT) Received: from ?IPv6:2601:646:8800:5a9a:a4d9:b8b5:b926:f5b2? ([2601:646:8800:5a9a:a4d9:b8b5:b926:f5b2]) by smtp.gmail.com with ESMTPSA id 22sm12455595pfh.48.2016.03.24.16.58.46 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 24 Mar 2016 16:58:47 -0700 (PDT) Mime-Version: 1.0 (Mac OS X Mail 9.3 \(3124\)) X-Pgp-Agent: GPGMail 2.6b2 From: Khem Raj In-Reply-To: <1458861705.2038.43.camel@pbcl.net> Date: Thu, 24 Mar 2016 16:58:42 -0700 Message-Id: References: <1458789553-3629-1-git-send-email-armccurdy@gmail.com> <1458844322.3476.198.camel@pbcl.net> <93EB73B6-E9B5-4DAE-9CCE-3D87FAD794D3@gmail.com> <1458861705.2038.43.camel@pbcl.net> To: Phil Blundell X-Mailer: Apple Mail (2.3124) Cc: Patches and discussions about the oe-core layer Subject: Re: [PATCH] gcc-configure-common.inc: duplicate armv7a over-ride for armv8a X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Mar 2016 23:58:49 -0000 X-Groupsio-MsgNum: 80125 Content-Type: multipart/signed; boundary="Apple-Mail=_8E8B571B-F484-44F5-AE75-D0C6C3F2F3D1"; protocol="application/pgp-signature"; micalg=pgp-sha1 --Apple-Mail=_8E8B571B-F484-44F5-AE75-D0C6C3F2F3D1 Content-Type: multipart/alternative; boundary="Apple-Mail=_EBA66671-8852-4055-A699-110C283BD4EF" --Apple-Mail=_EBA66671-8852-4055-A699-110C283BD4EF Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=us-ascii > On Mar 24, 2016, at 4:21 PM, Phil Blundell wrote: >=20 > On Thu, 2016-03-24 at 15:22 -0700, Khem Raj wrote: >>=20 >> > On Mar 24, 2016, at 11:32 AM, Phil Blundell > wrote: >> > >> > On Thu, 2016-03-24 at 10:37 -0700, Andre McCurdy wrote: >> >> >> >> Renaming armv8a -> aarch32 is going to affect almost every line in >> >> the patch. We should probably drop the current patch from master- >> >> next. >> > >> > "AArch32" applies retrospectively to all older versions of the ARM >> > architecture as well, >>=20 >> not really. Arm refers to aarch32 specifically when we use 32-bit on = ARMv8 >> so atleast we are speaking same terms. >=20 > See the glossary at: >=20 > = http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.aeg0014g/ABC= DEFGH.html = >=20 > AArch32 state > The ARM 32-bit Execution state that uses 32-bit general purpose = registers, and a 32-bit program counter (PC), stack pointer (SP), and = link register (LR). AArch32 Execution state provides a choice of two = instruction sets, A32 and T32. >=20 > In implementations of versions of the ARM architecture before ARMv8, = and in the ARM R and M architecture profiles, execution is always in = AArch32 state. I am not saying its any different technically. But aarch32 as term is = only used w.r.t. armv8 >=20 > p. --Apple-Mail=_EBA66671-8852-4055-A699-110C283BD4EF Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=us-ascii
On Mar 24, 2016, at 4:21 PM, Phil Blundell <pb@pbcl.net> = wrote:

On Thu, 2016-03-24 at 15:22 -0700, Khem Raj = wrote:
> On =
Mar 24, 2016, at 11:32 AM, Phil Blundell <pb@pbcl.net> wrote:
> 
> On Thu, 2016-03-24 at 10:37 =
-0700, Andre McCurdy wrote:
>> 
>> Renaming armv8a -> =
aarch32 is going to affect almost every line in
>> the patch. We should =
probably drop the current patch from master-
>> next.
> 
> "AArch32" applies =
retrospectively to all older versions of the ARM
> architecture as well,

not really. Arm refers to aarch32 specifically when we use 32-bit on =
ARMv8
so atleast we are speaking same terms.

See the glossary at:

http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.a= eg0014g/ABCDEFGH.html

AArch32 = state
The ARM 32-bit Execution state that uses 32-bit general = purpose registers, and a 32-bit program counter (PC), stack pointer = (SP), and link register (LR). AArch32 Execution state provides a choice = of two instruction sets, A32 and T32.

In = implementations of versions of the ARM architecture before ARMv8, and in = the ARM R and M architecture profiles, execution is always in AArch32 = state.

I am not saying its any different technically. But = aarch32 as term is only used w.r.t. armv8


p.

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