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Mon, 12 Feb 2024 20:01:38 +0000 Received: from SJ0PR11MB5920.namprd11.prod.outlook.com ([fe80::f3ba:ff33:12be:cff7]) by SJ0PR11MB5920.namprd11.prod.outlook.com ([fe80::f3ba:ff33:12be:cff7%7]) with mapi id 15.20.7270.036; Mon, 12 Feb 2024 20:01:38 +0000 Content-Type: multipart/alternative; boundary="------------j7Tt9DkFsdlcbYZzKTSVxM4A" Message-ID: Date: Mon, 12 Feb 2024 15:01:35 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] gcc: Add riscv64 as a compatible host to gcc-sanitizers Content-Language: en-CA From: Randy MacLeod To: Deepthi.Hemraj@windriver.com, openembedded-core@lists.openembedded.org, "Ramasamy, Rajeshkumar" , "Hao, Kexin" Cc: Umesh.Kalappa@windriver.com, Naveen.Gowda@windriver.com, Shivaprasad.Moodalappa@windriver.com, Sundeep.Kokkonda@windriver.com References: <20240212110000.1687187-1-Deepthi.Hemraj@windriver.com> In-Reply-To: X-ClientProxiedBy: BY5PR17CA0001.namprd17.prod.outlook.com (2603:10b6:a03:1b8::14) To SJ0PR11MB5920.namprd11.prod.outlook.com (2603:10b6:a03:42e::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ0PR11MB5920:EE_|DM4PR11MB5360:EE_ X-MS-Office365-Filtering-Correlation-Id: 5880e9e7-04e7-4253-8d02-08dc2c056c4b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Mon, 12 Feb 2024 20:01:51 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/195361 --------------j7Tt9DkFsdlcbYZzKTSVxM4A Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-0064b401.pphosted.com id 41CDeZQV007528 On 2024-02-12 2:49 p.m., Randy MacLeod wrote: > On 2024-02-12 6:00 a.m., Deepthi.Hemraj@windriver.com wrote: >> From: Deepthi Hemraj >> >> The issue address-sanitizer check failure arises when attempting to ru= n a testcase compiled with AddressSanitizer on RISC-V 64 systems using th= e SV48 and SV57 virtual address scheme. >> This error occurs due to the lack of support for SV48 and SV57 in ASAN= , which was originally designed for SV39 in Riscv64 architecture. >> This patch disables SV48 and SV57 support in QEMU and modifying the ke= rnel to use SV39 by default. > > > Deepthi, > > Thanks for looking into the gcc-sanitizers feature for qemuriscv64. > > I'm not sure if we want to make the qemu change that you have proposed = and > since no one else has replied, I've looped in Kevin and Raj who may be=20 > able to > comment on the change. > > Oh, in reading over the comments to the issue linked below, I see: > =C2=A0 "As a temporary workaround for this problem" > > so I really doubt we want to make this change. Changing thevirtual=20 > address range for qemu is not to be undertaken lightly! > > Let's see what we hear from Kevin, Raj and upstream qemu over the=20 > coming week or two. > > To me, this is a '(very) nice to have' feature not a 'must have feature= ' > so if we have to wait until after Yocto-5.0, that's fine. > One more thing Deepthi, It would be good to add a test case similar to or extending: =C2=A0=C2=A0 meta/lib/oeqa/runtime/cases/gcc.py to ensure the feature does not regress. Thanks, ../Randy >> Upstream-Status: Backport [https://github.com/google/sanitizers/issues= /1707] > > s/Backport/Submitted/ > > as you have done below in the patch body. > > > Only commits merged to supported branches or master/main, should be=20 > labelled as back-ports > > Thanks, > > ../Randy > > ` > >> Signed-off-by: Deepthi Hemraj >> --- >> meta/recipes-devtools/gcc/gcc-sanitizers.inc | 3 ++- >> meta/recipes-devtools/qemu/qemu.inc | 1 + >> ...isable-sv48-sv57-support-for-riscv64.patch | 25 +++++++++++++++++= ++ >> 3 files changed, 28 insertions(+), 1 deletion(-) >> create mode 100644 meta/recipes-devtools/qemu/qemu/disable-sv48-sv57= -support-for-riscv64.patch >> >> diff --git a/meta/recipes-devtools/gcc/gcc-sanitizers.inc b/meta/recip= es-devtools/gcc/gcc-sanitizers.inc >> index 524ebd4ba4..8c98e9cf8a 100644 >> --- a/meta/recipes-devtools/gcc/gcc-sanitizers.inc >> +++ b/meta/recipes-devtools/gcc/gcc-sanitizers.inc >> @@ -73,13 +73,14 @@ RRECOMMENDS:${PN}:append:x86 =3D " liblsan" >> RRECOMMENDS:${PN}:append:x86-64 =3D " liblsan libtsan" >> RRECOMMENDS:${PN}:append:powerpc64 =3D " liblsan libtsan" >> RRECOMMENDS:${PN}:append:aarch64 =3D " liblsan libtsan" >> +RRECOMMENDS:${PN}:append:riscv64 =3D " liblsan libtsan" >> =20 >> do_package_write_ipk[depends] +=3D "virtual/${MLPREFIX}${TARGET_PREF= IX}compilerlibs:do_packagedata" >> do_package_write_deb[depends] +=3D "virtual/${MLPREFIX}${TARGET_PREF= IX}compilerlibs:do_packagedata" >> do_package_write_rpm[depends] +=3D "virtual/${MLPREFIX}${TARGET_PREF= IX}compilerlibs:do_packagedata" >> =20 >> # Only x86, powerpc, sparc, s390, arm, aarch64 and loongarch64 are s= upported >> -COMPATIBLE_HOST =3D '(x86_64|i.86|powerpc|sparc|s390|arm|aarch64|loon= garch64).*-linux' >> +COMPATIBLE_HOST =3D '(x86_64|i.86|powerpc|sparc|s390|arm|aarch64|loon= garch64|riscv64).*-linux' >> # musl is currently broken entirely >> COMPATIBLE_HOST:libc-musl =3D 'null' >> =20 >> diff --git a/meta/recipes-devtools/qemu/qemu.inc b/meta/recipes-devtoo= ls/qemu/qemu.inc >> index 2a81870151..56c988e7fd 100644 >> --- a/meta/recipes-devtools/qemu/qemu.inc >> +++ b/meta/recipes-devtools/qemu/qemu.inc >> @@ -36,6 +36,7 @@ SRC_URI =3D"https://download.qemu.org/${BPN}-${PV}.t= ar.xz \=20 >> file://fix_segv.patch \ file://qemu-guest-agent.init \=20 >> file://qemu-guest-agent.udev \ +=20 >> file://disable-sv48-sv57-support-for-riscv64.patch \ " >> UPSTREAM_CHECK_REGEX =3D "qemu-(?P\d+(\.\d+)+)\.tar" >> =20 >> diff --git a/meta/recipes-devtools/qemu/qemu/disable-sv48-sv57-support= -for-riscv64.patch b/meta/recipes-devtools/qemu/qemu/disable-sv48-sv57-su= pport-for-riscv64.patch >> new file mode 100644 >> index 0000000000..7f3eab1463 >> --- /dev/null >> +++ b/meta/recipes-devtools/qemu/qemu/disable-sv48-sv57-support-for-ri= scv64.patch >> @@ -0,0 +1,25 @@ >> +From: Deepthi Hemraj >> +Date: thur, 18 jan 2024 17:52:45 >> +Subject: disable-sv48-sv57-support-for-riscv64 >> + >> +Disabling 48 & 57 bit virtual memory address in a RISC-V program, wh= ile the system's upper address limit resembles that of a 39-bit address s= pace. >> +This signals a lack of support for the 48 & 57 bit virtual address sp= ace on RISC-V; only the SV39 scheme is supported. >> + >> +Upstream-Status: Submitted [https://github.com/google/sanitizers/issu= es/1707] >> +Signed-off-by: Deepthi Hemraj >> + >> +--- >> + >> +diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> +--- a/target/riscv/csr.c >> ++++ b/target/riscv/csr.c >> +@@ -1178,7 +1178,7 @@ const bool valid_vm_1_10_64[16] =3D { >> + [VM_1_10_MBARE] =3D true, >> + [VM_1_10_SV39] =3D true, >> +- [VM_1_10_SV48] =3D true, >> +- [VM_1_10_SV57] =3D true >> ++ [VM_1_10_SV48] =3D false, >> ++ [VM_1_10_SV57] =3D false >> + }; >> + >> + /* Machine Information Registers */ > > > --=20 > # Randy MacLeod > # Wind River Linux --=20 # Randy MacLeod # Wind River Linux --------------j7Tt9DkFsdlcbYZzKTSVxM4A Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit
On 2024-02-12 2:49 p.m., Randy MacLeod wrote:
On 2024-02-12 6:00 a.m., Deepthi.Hemraj@windriver.com wrote:
From: Deepthi Hemraj <Deepthi.Hemraj@windriver.com>

The issue address-sanitizer check failure arises when attempting to run a testcase compiled with AddressSanitizer on RISC-V 64 systems using the SV48 and SV57 virtual address scheme.
This error occurs due to the lack of support for SV48 and SV57 in ASAN, which was originally designed for SV39 in Riscv64 architecture.
This patch disables SV48 and SV57 support in QEMU and modifying the kernel to use SV39 by default.


Deepthi,

Thanks for looking into the gcc-sanitizers feature for qemuriscv64.

I'm not sure if we want to make the qemu change that you have proposed and
since no one else has replied, I've looped in Kevin and Raj who may be able to
comment on the change.

Oh, in reading over the comments to the issue linked below, I see:
  "As a temporary workaround for this problem" 

so I really doubt we want to make this change. Changing the virtual address range for qemu is not to be undertaken lightly!

Let's see what we hear from Kevin, Raj and upstream qemu over the coming week or two.

To me, this is a '(very) nice to have' feature not a 'must have feature'
so if we have to wait until after Yocto-5.0, that's fine.

One more thing Deepthi,

It would be good to add a test case similar to or extending:

   meta/lib/oeqa/runtime/cases/gcc.py

to ensure the feature does not regress.

Thanks,

../Randy

Upstream-Status: Backport [https://github.com/google/sanitizers/issues/1707]

s/Backport/Submitted/

as you have done below in the patch body.


Only commits merged to supported branches or master/main, should be labelled as back-ports

Thanks,

../Randy

`

Signed-off-by: Deepthi Hemraj <Deepthi.Hemraj@windriver.com>
---
 meta/recipes-devtools/gcc/gcc-sanitizers.inc  |  3 ++-
 meta/recipes-devtools/qemu/qemu.inc           |  1 +
 ...isable-sv48-sv57-support-for-riscv64.patch | 25 +++++++++++++++++++
 3 files changed, 28 insertions(+), 1 deletion(-)
 create mode 100644 meta/recipes-devtools/qemu/qemu/disable-sv48-sv57-support-for-riscv64.patch

diff --git a/meta/recipes-devtools/gcc/gcc-sanitizers.inc b/meta/recipes-devtools/gcc/gcc-sanitizers.inc
index 524ebd4ba4..8c98e9cf8a 100644
--- a/meta/recipes-devtools/gcc/gcc-sanitizers.inc
+++ b/meta/recipes-devtools/gcc/gcc-sanitizers.inc
@@ -73,13 +73,14 @@ RRECOMMENDS:${PN}:append:x86 = " liblsan"
 RRECOMMENDS:${PN}:append:x86-64 = " liblsan libtsan"
 RRECOMMENDS:${PN}:append:powerpc64 = " liblsan libtsan"
 RRECOMMENDS:${PN}:append:aarch64 = " liblsan libtsan"
+RRECOMMENDS:${PN}:append:riscv64 = " liblsan libtsan"
 
 do_package_write_ipk[depends] += "virtual/${MLPREFIX}${TARGET_PREFIX}compilerlibs:do_packagedata"
 do_package_write_deb[depends] += "virtual/${MLPREFIX}${TARGET_PREFIX}compilerlibs:do_packagedata"
 do_package_write_rpm[depends] += "virtual/${MLPREFIX}${TARGET_PREFIX}compilerlibs:do_packagedata"
 
 # Only x86, powerpc, sparc, s390, arm, aarch64 and loongarch64 are supported
-COMPATIBLE_HOST = '(x86_64|i.86|powerpc|sparc|s390|arm|aarch64|loongarch64).*-linux'
+COMPATIBLE_HOST = '(x86_64|i.86|powerpc|sparc|s390|arm|aarch64|loongarch64|riscv64).*-linux'
 # musl is currently broken entirely
 COMPATIBLE_HOST:libc-musl = 'null'
 
diff --git a/meta/recipes-devtools/qemu/qemu.inc b/meta/recipes-devtools/qemu/qemu.inc
index 2a81870151..56c988e7fd 100644
--- a/meta/recipes-devtools/qemu/qemu.inc
+++ b/meta/recipes-devtools/qemu/qemu.inc
@@ -36,6 +36,7 @@ SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \
            file://fix_segv.patch \
            file://qemu-guest-agent.init \
            file://qemu-guest-agent.udev \
+	   file://disable-sv48-sv57-support-for-riscv64.patch \
            "
 UPSTREAM_CHECK_REGEX = "qemu-(?P<pver>\d+(\.\d+)+)\.tar"
 
diff --git a/meta/recipes-devtools/qemu/qemu/disable-sv48-sv57-support-for-riscv64.patch b/meta/recipes-devtools/qemu/qemu/disable-sv48-sv57-support-for-riscv64.patch
new file mode 100644
index 0000000000..7f3eab1463
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/disable-sv48-sv57-support-for-riscv64.patch
@@ -0,0 +1,25 @@
+From: Deepthi Hemraj
+Date: thur, 18 jan 2024 17:52:45
+Subject: disable-sv48-sv57-support-for-riscv64 
+
+Disabling  48 & 57 bit virtual memory address in a RISC-V program, while the system's upper address limit resembles that of a 39-bit address space. 
+This signals a lack of support for the 48 & 57 bit virtual address space on RISC-V; only the SV39 scheme is supported.
+
+Upstream-Status: Submitted [https://github.com/google/sanitizers/issues/1707]
+Signed-off-by: Deepthi Hemraj <Deepthi.Hemraj@windriver.com>
+
+---
+
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -1178,7 +1178,7 @@ const bool valid_vm_1_10_64[16] = {
+     [VM_1_10_MBARE] = true,
+     [VM_1_10_SV39] = true,
+-    [VM_1_10_SV48] = true,
+-    [VM_1_10_SV57] = true
++    [VM_1_10_SV48] = false,
++    [VM_1_10_SV57] = false
+ };
+ 
+ /* Machine Information Registers */



-- 
# Randy MacLeod
# Wind River Linux


-- 
# Randy MacLeod
# Wind River Linux
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