Re: [OE-core] [scarthgap][PATCH] glibc: stable 2.39 branch updates

Deepesh Varatharajan
2025-05-02T03:15:25Z

On 01-05-2025 11:24, Khem Raj wrote:
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> On Wed, Apr 30, 2025 at 8:03 PM Varatharajan, Deepesh via
> lists.openembedded.org
> <deepesh.varatharajan=windriver.com@lists.openembedded.org> wrote:
>> From: Deepesh Varatharajan <Deepesh.Varatharajan@windriver.com>
>>
>> 3463100f2d x86: Detect Intel Diamond Rapids
>> e09436c2cb x86: Handle unknown Intel processor with default tuning
>> 7620d98186 x86: Add ARL/PTL/CWF model detection support
>> 765ff3d0d4 x86: Optimize xstate size calculation
>> 65ae73be01 x86: Use `Avoid_Non_Temporal_Memset` to control non-temporal path
>> 2be36448c4 x86: Tunables may incorrectly set Prefer_PMINUB_for_stringop (bug 32047)
>> bde201e92c x86: Disable non-temporal memset on Skylake Server
>> 38a7632f2d x86: Fix value for `x86_memset_non_temporal_threshold` when it is undesirable
>> cc59fa5dbc x86: Enable non-temporal memset tunable for AMD
>> 0da58e8be0 x86: Add seperate non-temporal tunable for memset
>> 837a36c371 x86: Link tst-gnu2-tls2-x86-noxsave{,c,xsavec} with libpthread
>> 87ab0c7f7f x86: Use separate variable for TLSDESC XSAVE/XSAVEC state size (bug 32810)
>> 60cd7123a6 x86: Skip XSAVE state size reset if ISA level requires XSAVE
>> 4cf3f9df54 x86_64: Add atanh with FMA
>> 01ed435e2e x86_64: Add sinh with FMA
>> 0edcc77fe7 x86_64: Add tanh with FMA
>> 7ecf0d3bde x86-64: Exclude FMA4 IFUNC functions for -mapxf
>> e1fe22368e nptl: clear the whole rseq area before registration
>> dd8c0c3bbd math: Improve layout of exp/exp10 data
>> a1b09e59e2 AArch64: Use prefer_sve_ifuncs for SVE memset
>> d0e2133470 AArch64: Add SVE memset
>> 0cc12d9c47 math: Improve layout of expf data
>> 0cd10047bf AArch64: Remove zva_128 from memset
>> dd1e63ab58 AArch64: Optimize memset
>> 65a96a6f2b AArch64: Improve generic strlen
>> 4073e4ee2c AArch64: Improve codegen for SVE logs
>> 78abd3ef6e AArch64: Improve codegen in SVE tans
>> a10183b633 AArch64: Improve codegen of AdvSIMD atan(2)(f)
>> dcd1229e5b AArch64: Improve codegen of AdvSIMD logf function family
>> 72156cb90b AArch64: Improve codegen in AdvSIMD logs
>> 5e354bf4e2 AArch64: Simplify rounding-multiply pattern in several AdvSIMD routines
>> 80df456112 aarch64: Avoid redundant MOVs in AdvSIMD F32 logs
>> d591876303 aarch64: Fix AdvSIMD libmvec routines for big-endian
>> f6d48470ae assert: Add test for CVE-2025-0395
>>
>> Testresults:
>> After update |Before update |Difference
>> PASS: 5068 |PASS: 5072 |PASS: +4
> +4 should mean more passes after update but the table shows otherwise.
> Can you list the 4 tests which are passing now ?
Hi Khem,

Apologies for the confusion, there was a typo. I mistakenly listed the
'after update'
passing test cases under 'before update' and vice versa. The following four
additional test cases passed after the update:

PASS: assert/tst-assert-sa-2025-0001
PASS: elf/tst-gnu2-tls2-x86-noxsave
PASS: elf/tst-gnu2-tls2-x86-noxsavec
PASS: elf/tst-gnu2-tls2-x86-noxsavexsavec

Regards,
Deepesh
>> FAIL: 120 |FAIL: 120 |FAIL: 0
>> XPASS: 4 |XPASS: 4 |XPASS: 0
>> XFAIL: 16 |XFAIL: 16 |XFAIL: 0
>> UNSUPPORTED: 157|UNSUPPORTED: 157|UNSUPPORTED: 0
>>
>> Signed-off-by: Deepesh Varatharajan <Deepesh.Varatharajan@windriver.com>
>> ---
>> meta/recipes-core/glibc/glibc-version.inc | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/meta/recipes-core/glibc/glibc-version.inc b/meta/recipes-core/glibc/glibc-version.inc
>> index da9227ccca..040fc793b1 100644
>> --- a/meta/recipes-core/glibc/glibc-version.inc
>> +++ b/meta/recipes-core/glibc/glibc-version.inc
>> @@ -1,6 +1,6 @@
>> SRCBRANCH ?= "release/2.39/master"
>> PV = "2.39+git"
>> -SRCREV_glibc ?= "662516aca8b6bf6aa6555f471055d5eb512b1ddc"
>> +SRCREV_glibc ?= "3463100f2d47f2897a24ba8023a5c7aaf2d26550"
>> SRCREV_localedef ?= "fab74f31b3811df543e24b6de47efdf45b538abc"
>>
>> GLIBC_GIT_URI ?= "git://sourceware.org/git/glibc.git;protocol=https"
>> --
>> 2.43.0
>>
>>
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