From: Stafford Horne <shorne@gmail.com>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v3 04/13] dt-bindings: add openrisc to vendor prefixes list
Date: Sun, 22 Oct 2017 12:15:51 +0900 [thread overview]
Message-ID: <20171022031600.29612-5-shorne@gmail.com> (raw)
In-Reply-To: <20171022031600.29612-1-shorne@gmail.com>
Add OpenRISC.io to vendor prefixes. This is reserved for softcores
developed by the OpenRISC community. The OpenRISC community has
separated from OpenCores.org requiring a new prefix.
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
Changes since v2
- None
Changes since v1
- New patch
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1ea1fd4232ab..1478aad87532 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -246,6 +246,7 @@ onion Onion Corporation
onnn ON Semiconductor Corp.
ontat On Tat Industrial Company
opencores OpenCores.org
+openrisc OpenRISC.io
option Option NV
ORCL Oracle Corporation
ortustech Ortus Technology Co., Ltd.
--
2.13.6
next prev parent reply other threads:[~2017-10-22 3:15 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-22 3:15 [OpenRISC] [PATCH v3 00/13] OpenRISC SMP Support Stafford Horne
2017-10-22 3:15 ` [OpenRISC] [PATCH v3 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne
2017-10-22 3:15 ` [OpenRISC] [PATCH v3 02/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
2017-10-22 3:15 ` [OpenRISC] [PATCH v3 03/13] openrisc: use qspinlocks and qrwlocks Stafford Horne
2017-10-22 3:15 ` Stafford Horne [this message]
2017-10-22 3:15 ` [OpenRISC] [PATCH v3 05/13] irqchip: add initial support for ompic Stafford Horne
2017-10-23 8:00 ` Marc Zyngier
2017-10-23 12:57 ` Stafford Horne
2017-10-27 3:19 ` Rob Herring
2017-10-22 3:15 ` [OpenRISC] [PATCH v3 06/13] openrisc: initial SMP support Stafford Horne
2017-10-22 3:15 ` [OpenRISC] [PATCH v3 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne
2017-10-22 3:15 ` [OpenRISC] [PATCH v3 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne
2017-10-22 3:15 ` [OpenRISC] [PATCH v3 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne
2017-10-22 3:15 ` [OpenRISC] [PATCH v3 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
2017-10-22 3:15 ` [OpenRISC] [PATCH v3 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne
2017-10-22 3:15 ` [OpenRISC] [PATCH v3 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne
2017-10-22 3:16 ` [OpenRISC] [PATCH v3 13/13] openrisc: add tick timer multi-core sync logic Stafford Horne
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