From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Date: Fri, 15 May 2020 16:36:39 +0200 Subject: [OpenRISC] [PATCH 22/29] xtensa: implement flush_icache_user_range In-Reply-To: <20200515143646.3857579-1-hch@lst.de> References: <20200515143646.3857579-1-hch@lst.de> Message-ID: <20200515143646.3857579-23-hch@lst.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: openrisc@lists.librecores.org The Xtensa implementation of flush_icache_range seems to be able to cope with user addresses. Just define flush_icache_user_range to flush_icache_range. Signed-off-by: Christoph Hellwig --- arch/xtensa/include/asm/cacheflush.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h index a0d50be5a8cb1..460e666ad0761 100644 --- a/arch/xtensa/include/asm/cacheflush.h +++ b/arch/xtensa/include/asm/cacheflush.h @@ -107,6 +107,8 @@ void flush_cache_page(struct vm_area_struct*, #define flush_cache_page local_flush_cache_page #endif +#define flush_icache_user_range flush_icache_range + #define local_flush_cache_all() \ do { \ __flush_invalidate_dcache_all(); \ -- 2.26.2