* [PATCH v5 1/3] openrisc: Refactor struct cpuinfo_or1k to reduce duplication
2025-03-29 9:46 [PATCH v5 0/3] openrisc: Add cacheinfo support and introduce new utility functions Sahil Siddiq
@ 2025-03-29 9:46 ` Sahil Siddiq
2025-03-29 9:46 ` [PATCH v5 2/3] openrisc: Introduce new utility functions to flush and invalidate caches Sahil Siddiq
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Sahil Siddiq @ 2025-03-29 9:46 UTC (permalink / raw)
To: jonas, stefan.kristiansson, shorne; +Cc: sahilcdq, linux-openrisc, linux-kernel
The "cpuinfo_or1k" structure currently has identical data members for
different cache components.
Remove these fields out of struct cpuinfo_or1k and into its own struct.
This reduces duplication while keeping cpuinfo_or1k extensible so more
cache descriptors can be added in the future.
Also add a new field "sets" to the new structure.
Signed-off-by: Sahil Siddiq <sahilcdq@proton.me>
---
No change from v3 -> v4/v5.
Changes from v1/v2 -> v3:
- arch/openrisc/kernel/setup.c:
(print_cpuinfo):
1. Cascade changes made to struct cpuinfo_or1k.
2. These lines are ultimately shifted to the new file created in
patch #3.
(setup_cpuinfo): Likewise.
(show_cpuinfo): Likewise.
arch/openrisc/include/asm/cpuinfo.h | 16 +++++-----
arch/openrisc/kernel/setup.c | 45 ++++++++++++++---------------
2 files changed, 31 insertions(+), 30 deletions(-)
diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/asm/cpuinfo.h
index 5e4744153d0e..82f5d4c06314 100644
--- a/arch/openrisc/include/asm/cpuinfo.h
+++ b/arch/openrisc/include/asm/cpuinfo.h
@@ -15,16 +15,18 @@
#ifndef __ASM_OPENRISC_CPUINFO_H
#define __ASM_OPENRISC_CPUINFO_H
+struct cache_desc {
+ u32 size;
+ u32 sets;
+ u32 block_size;
+ u32 ways;
+};
+
struct cpuinfo_or1k {
u32 clock_frequency;
- u32 icache_size;
- u32 icache_block_size;
- u32 icache_ways;
-
- u32 dcache_size;
- u32 dcache_block_size;
- u32 dcache_ways;
+ struct cache_desc icache;
+ struct cache_desc dcache;
u16 coreid;
};
diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c
index be56eaafc8b9..66207cd7bb9e 100644
--- a/arch/openrisc/kernel/setup.c
+++ b/arch/openrisc/kernel/setup.c
@@ -115,16 +115,16 @@ static void print_cpuinfo(void)
if (upr & SPR_UPR_DCP)
printk(KERN_INFO
- "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
- cpuinfo->dcache_size, cpuinfo->dcache_block_size,
- cpuinfo->dcache_ways);
+ "-- dcache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
+ cpuinfo->dcache.size, cpuinfo->dcache.block_size,
+ cpuinfo->dcache.sets, cpuinfo->dcache.ways);
else
printk(KERN_INFO "-- dcache disabled\n");
if (upr & SPR_UPR_ICP)
printk(KERN_INFO
- "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
- cpuinfo->icache_size, cpuinfo->icache_block_size,
- cpuinfo->icache_ways);
+ "-- icache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
+ cpuinfo->icache.size, cpuinfo->icache.block_size,
+ cpuinfo->icache.sets, cpuinfo->icache.ways);
else
printk(KERN_INFO "-- icache disabled\n");
@@ -156,7 +156,6 @@ void __init setup_cpuinfo(void)
{
struct device_node *cpu;
unsigned long iccfgr, dccfgr;
- unsigned long cache_set_size;
int cpu_id = smp_processor_id();
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
@@ -165,18 +164,18 @@ void __init setup_cpuinfo(void)
panic("Couldn't find CPU%d in device tree...\n", cpu_id);
iccfgr = mfspr(SPR_ICCFGR);
- cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
- cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
- cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
- cpuinfo->icache_size =
- cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size;
+ cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
+ cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
+ cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
+ cpuinfo->icache.size =
+ cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
dccfgr = mfspr(SPR_DCCFGR);
- cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
- cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
- cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
- cpuinfo->dcache_size =
- cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size;
+ cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
+ cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
+ cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
+ cpuinfo->dcache.size =
+ cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
if (of_property_read_u32(cpu, "clock-frequency",
&cpuinfo->clock_frequency)) {
@@ -320,14 +319,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
}
seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
- seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size);
+ seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache.size);
seq_printf(m, "dcache block size\t: %d bytes\n",
- cpuinfo->dcache_block_size);
- seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways);
- seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size);
+ cpuinfo->dcache.block_size);
+ seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache.ways);
+ seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache.size);
seq_printf(m, "icache block size\t: %d bytes\n",
- cpuinfo->icache_block_size);
- seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways);
+ cpuinfo->icache.block_size);
+ seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache.ways);
seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
--
2.48.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v5 2/3] openrisc: Introduce new utility functions to flush and invalidate caches
2025-03-29 9:46 [PATCH v5 0/3] openrisc: Add cacheinfo support and introduce new utility functions Sahil Siddiq
2025-03-29 9:46 ` [PATCH v5 1/3] openrisc: Refactor struct cpuinfo_or1k to reduce duplication Sahil Siddiq
@ 2025-03-29 9:46 ` Sahil Siddiq
2025-03-29 9:46 ` [PATCH v5 3/3] openrisc: Add cacheinfo support Sahil Siddiq
2025-03-29 10:12 ` [PATCH v5 0/3] openrisc: Add cacheinfo support and introduce new utility functions Stafford Horne
3 siblings, 0 replies; 6+ messages in thread
From: Sahil Siddiq @ 2025-03-29 9:46 UTC (permalink / raw)
To: jonas, stefan.kristiansson, shorne; +Cc: sahilcdq, linux-openrisc, linux-kernel
According to the OpenRISC architecture manual, the dcache and icache may
not be present. When these caches are present, the invalidate and flush
registers may be absent. The current implementation does not perform
checks to verify their presence before utilizing cache registers, or
invalidating and flushing cache blocks.
Introduce new functions to detect the presence of cache components and
related special-purpose registers.
There are a few places where a range of addresses have to be flushed or
invalidated and the implementation is duplicated. Introduce new utility
functions and macros that generalize this implementation and reduce
duplication.
Signed-off-by: Sahil Siddiq <sahilcdq@proton.me>
---
Changes from v4 -> v5:
- arch/openrisc/include/asm/cpuinfo.h: Remove cb_inv_flush_is_implemented.
- arch/openrisc/mm/cache.c:
(cpu_cache_is_present): Shift definition to the top.
(cb_inv_flush_is_implemented): Remove function.
- arch/openrisc/mm/cache.c:
(cpu_cache_is_present): Fix condition.
Changes from v3 -> v4:
- arch/openrisc/include/asm/cpuinfo.h: Move new definitions to cache.c.
- arch/openrisc/mm/cache.c:
(cache_loop): Split function.
(cache_loop_page): New function.
(cpu_cache_is_present): Move definition here.
(cb_inv_flush_is_implemented): Move definition here.
Changes from v2 -> v3:
- arch/openrisc/include/asm/cacheflush.h: Declare new functions and macros.
- arch/openrisc/include/asm/cpuinfo.h: Implement new functions.
(cpu_cache_is_present):
1. The implementation of this function was strewn all over the place in
the previous versions.
2. Fix condition. The condition in the previous version was incorrect.
(cb_inv_flush_is_implemented): New function.
- arch/openrisc/kernel/dma.c: Use new functions.
- arch/openrisc/mm/cache.c:
(cache_loop): Extend function.
(local_*_page_*): Use new cache_loop interface.
(local_*_range_*): Implement new functions.
- arch/openrisc/mm/init.c: Use new functions.
arch/openrisc/include/asm/cacheflush.h | 17 ++++++++
arch/openrisc/include/asm/cpuinfo.h | 8 ++++
arch/openrisc/kernel/dma.c | 18 ++-------
arch/openrisc/mm/cache.c | 56 +++++++++++++++++++++-----
arch/openrisc/mm/init.c | 5 ++-
5 files changed, 79 insertions(+), 25 deletions(-)
diff --git a/arch/openrisc/include/asm/cacheflush.h b/arch/openrisc/include/asm/cacheflush.h
index 984c331ff5f4..0e60af486ec1 100644
--- a/arch/openrisc/include/asm/cacheflush.h
+++ b/arch/openrisc/include/asm/cacheflush.h
@@ -23,6 +23,9 @@
*/
extern void local_dcache_page_flush(struct page *page);
extern void local_icache_page_inv(struct page *page);
+extern void local_dcache_range_flush(unsigned long start, unsigned long end);
+extern void local_dcache_range_inv(unsigned long start, unsigned long end);
+extern void local_icache_range_inv(unsigned long start, unsigned long end);
/*
* Data cache flushing always happen on the local cpu. Instruction cache
@@ -38,6 +41,20 @@ extern void local_icache_page_inv(struct page *page);
extern void smp_icache_page_inv(struct page *page);
#endif /* CONFIG_SMP */
+/*
+ * Even if the actual block size is larger than L1_CACHE_BYTES, paddr
+ * can be incremented by L1_CACHE_BYTES. When paddr is written to the
+ * invalidate register, the entire cache line encompassing this address
+ * is invalidated. Each subsequent reference to the same cache line will
+ * not affect the invalidation process.
+ */
+#define local_dcache_block_flush(addr) \
+ local_dcache_range_flush(addr, addr + L1_CACHE_BYTES)
+#define local_dcache_block_inv(addr) \
+ local_dcache_range_inv(addr, addr + L1_CACHE_BYTES)
+#define local_icache_block_inv(addr) \
+ local_icache_range_inv(addr, addr + L1_CACHE_BYTES)
+
/*
* Synchronizes caches. Whenever a cpu writes executable code to memory, this
* should be called to make sure the processor sees the newly written code.
diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/asm/cpuinfo.h
index 82f5d4c06314..3cfc4cf0b019 100644
--- a/arch/openrisc/include/asm/cpuinfo.h
+++ b/arch/openrisc/include/asm/cpuinfo.h
@@ -15,6 +15,9 @@
#ifndef __ASM_OPENRISC_CPUINFO_H
#define __ASM_OPENRISC_CPUINFO_H
+#include <asm/spr.h>
+#include <asm/spr_defs.h>
+
struct cache_desc {
u32 size;
u32 sets;
@@ -34,4 +37,9 @@ struct cpuinfo_or1k {
extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
extern void setup_cpuinfo(void);
+/*
+ * Check if the cache component exists.
+ */
+extern bool cpu_cache_is_present(const unsigned int cache_type);
+
#endif /* __ASM_OPENRISC_CPUINFO_H */
diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c
index b3edbb33b621..3a7b5baaa450 100644
--- a/arch/openrisc/kernel/dma.c
+++ b/arch/openrisc/kernel/dma.c
@@ -17,6 +17,7 @@
#include <linux/pagewalk.h>
#include <asm/cpuinfo.h>
+#include <asm/cacheflush.h>
#include <asm/spr_defs.h>
#include <asm/tlbflush.h>
@@ -24,9 +25,6 @@ static int
page_set_nocache(pte_t *pte, unsigned long addr,
unsigned long next, struct mm_walk *walk)
{
- unsigned long cl;
- struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
-
pte_val(*pte) |= _PAGE_CI;
/*
@@ -36,8 +34,7 @@ page_set_nocache(pte_t *pte, unsigned long addr,
flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
/* Flush page out of dcache */
- for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size)
- mtspr(SPR_DCBFR, cl);
+ local_dcache_range_flush(__pa(addr), __pa(next));
return 0;
}
@@ -98,21 +95,14 @@ void arch_dma_clear_uncached(void *cpu_addr, size_t size)
void arch_sync_dma_for_device(phys_addr_t addr, size_t size,
enum dma_data_direction dir)
{
- unsigned long cl;
- struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
-
switch (dir) {
case DMA_TO_DEVICE:
/* Flush the dcache for the requested range */
- for (cl = addr; cl < addr + size;
- cl += cpuinfo->dcache_block_size)
- mtspr(SPR_DCBFR, cl);
+ local_dcache_range_flush(addr, addr + size);
break;
case DMA_FROM_DEVICE:
/* Invalidate the dcache for the requested range */
- for (cl = addr; cl < addr + size;
- cl += cpuinfo->dcache_block_size)
- mtspr(SPR_DCBIR, cl);
+ local_dcache_range_inv(addr, addr + size);
break;
default:
/*
diff --git a/arch/openrisc/mm/cache.c b/arch/openrisc/mm/cache.c
index eb43b73f3855..7bdd07cfca60 100644
--- a/arch/openrisc/mm/cache.c
+++ b/arch/openrisc/mm/cache.c
@@ -14,31 +14,70 @@
#include <asm/spr_defs.h>
#include <asm/cache.h>
#include <asm/cacheflush.h>
+#include <asm/cpuinfo.h>
#include <asm/tlbflush.h>
-static __always_inline void cache_loop(struct page *page, const unsigned int reg)
+/*
+ * Check if the cache component exists.
+ */
+bool cpu_cache_is_present(const unsigned int cache_type)
{
- unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
- unsigned long line = paddr & ~(L1_CACHE_BYTES - 1);
+ unsigned long upr = mfspr(SPR_UPR);
+ unsigned long mask = SPR_UPR_UP | cache_type;
+
+ return !((upr & mask) ^ mask);
+}
+
+static __always_inline void cache_loop(unsigned long paddr, unsigned long end,
+ const unsigned int reg, const unsigned int cache_type)
+{
+ if (!cpu_cache_is_present(cache_type))
+ return;
- while (line < paddr + PAGE_SIZE) {
- mtspr(reg, line);
- line += L1_CACHE_BYTES;
+ while (paddr < end) {
+ mtspr(reg, paddr);
+ paddr += L1_CACHE_BYTES;
}
}
+static void cache_loop_page(struct page *page, const unsigned int reg,
+ const unsigned int cache_type)
+{
+ unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
+ unsigned long end = paddr + PAGE_SIZE;
+
+ paddr &= ~(L1_CACHE_BYTES - 1);
+
+ cache_loop(paddr, end, reg, cache_type);
+}
+
void local_dcache_page_flush(struct page *page)
{
- cache_loop(page, SPR_DCBFR);
+ cache_loop_page(page, SPR_DCBFR, SPR_UPR_DCP);
}
EXPORT_SYMBOL(local_dcache_page_flush);
void local_icache_page_inv(struct page *page)
{
- cache_loop(page, SPR_ICBIR);
+ cache_loop_page(page, SPR_ICBIR, SPR_UPR_ICP);
}
EXPORT_SYMBOL(local_icache_page_inv);
+void local_dcache_range_flush(unsigned long start, unsigned long end)
+{
+ cache_loop(start, end, SPR_DCBFR, SPR_UPR_DCP);
+}
+
+void local_dcache_range_inv(unsigned long start, unsigned long end)
+{
+ cache_loop(start, end, SPR_DCBIR, SPR_UPR_DCP);
+}
+
+void local_icache_range_inv(unsigned long start, unsigned long end)
+{
+ cache_loop(start, end, SPR_ICBIR, SPR_UPR_ICP);
+}
+
void update_cache(struct vm_area_struct *vma, unsigned long address,
pte_t *pte)
{
@@ -58,4 +97,3 @@ void update_cache(struct vm_area_struct *vma, unsigned long address,
sync_icache_dcache(folio_page(folio, nr));
}
}
-
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index d0cb1a0126f9..46b8720db08e 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -35,6 +35,7 @@
#include <asm/fixmap.h>
#include <asm/tlbflush.h>
#include <asm/sections.h>
+#include <asm/cacheflush.h>
int mem_init_done;
@@ -176,8 +177,8 @@ void __init paging_init(void)
barrier();
/* Invalidate instruction caches after code modification */
- mtspr(SPR_ICBIR, 0x900);
- mtspr(SPR_ICBIR, 0xa00);
+ local_icache_block_inv(0x900);
+ local_icache_block_inv(0xa00);
/* New TLB miss handlers and kernel page tables are in now place.
* Make sure that page flags get updated for all pages in TLB by
--
2.48.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v5 3/3] openrisc: Add cacheinfo support
2025-03-29 9:46 [PATCH v5 0/3] openrisc: Add cacheinfo support and introduce new utility functions Sahil Siddiq
2025-03-29 9:46 ` [PATCH v5 1/3] openrisc: Refactor struct cpuinfo_or1k to reduce duplication Sahil Siddiq
2025-03-29 9:46 ` [PATCH v5 2/3] openrisc: Introduce new utility functions to flush and invalidate caches Sahil Siddiq
@ 2025-03-29 9:46 ` Sahil Siddiq
2025-03-29 10:12 ` [PATCH v5 0/3] openrisc: Add cacheinfo support and introduce new utility functions Stafford Horne
3 siblings, 0 replies; 6+ messages in thread
From: Sahil Siddiq @ 2025-03-29 9:46 UTC (permalink / raw)
To: jonas, stefan.kristiansson, shorne; +Cc: sahilcdq, linux-openrisc, linux-kernel
Add cacheinfo support for OpenRISC.
Currently, a few CPU cache attributes pertaining to OpenRISC processors
are exposed along with other unrelated CPU attributes in the procfs file
system (/proc/cpuinfo). However, a few cache attributes remain unexposed.
Provide a mechanism that the generic cacheinfo infrastructure can employ
to expose these attributes via the sysfs file system. These attributes
can then be exposed in /sys/devices/system/cpu/cpuX/cache/indexN. Move
the implementation to pull cache attributes from the processor's
registers from arch/openrisc/kernel/setup.c with a few modifications.
This implementation is based on similar work done for MIPS and LoongArch.
Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Sahil Siddiq <sahilcdq@proton.me>
---
No change from v4 -> v5.
Changes from v3 -> v4:
- arch/openrisc/kernel/cacheinfo.c: Fix build warning detected by
kernel test robot.
Changes from v2 -> v3:
- arch/openrisc/kernel/cacheinfo.c:
1. Use new functions introduced in patch #2.
2. Address review comments regarding coding style.
- arch/openrisc/kernel/setup.c:
(print_cpuinfo): Don't remove detection of UPR register.
arch/openrisc/kernel/Makefile | 2 +-
arch/openrisc/kernel/cacheinfo.c | 104 +++++++++++++++++++++++++++++++
arch/openrisc/kernel/setup.c | 44 +------------
3 files changed, 108 insertions(+), 42 deletions(-)
create mode 100644 arch/openrisc/kernel/cacheinfo.c
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index 79129161f3e0..e4c7d9bdd598 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -7,7 +7,7 @@ extra-y := vmlinux.lds
obj-y := head.o setup.o or32_ksyms.o process.o dma.o \
traps.o time.o irq.o entry.o ptrace.o signal.o \
- sys_call_table.o unwinder.o
+ sys_call_table.o unwinder.o cacheinfo.o
obj-$(CONFIG_SMP) += smp.o sync-timer.o
obj-$(CONFIG_STACKTRACE) += stacktrace.o
diff --git a/arch/openrisc/kernel/cacheinfo.c b/arch/openrisc/kernel/cacheinfo.c
new file mode 100644
index 000000000000..61230545e4ff
--- /dev/null
+++ b/arch/openrisc/kernel/cacheinfo.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * OpenRISC cacheinfo support
+ *
+ * Based on work done for MIPS and LoongArch. All original copyrights
+ * apply as per the original source declaration.
+ *
+ * OpenRISC implementation:
+ * Copyright (C) 2025 Sahil Siddiq <sahilcdq@proton.me>
+ */
+
+#include <linux/cacheinfo.h>
+#include <asm/cpuinfo.h>
+#include <asm/spr.h>
+#include <asm/spr_defs.h>
+
+static inline void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type,
+ unsigned int level, struct cache_desc *cache, int cpu)
+{
+ this_leaf->type = type;
+ this_leaf->level = level;
+ this_leaf->coherency_line_size = cache->block_size;
+ this_leaf->number_of_sets = cache->sets;
+ this_leaf->ways_of_associativity = cache->ways;
+ this_leaf->size = cache->size;
+ cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map);
+}
+
+int init_cache_level(unsigned int cpu)
+{
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+ int leaves = 0, levels = 0;
+ unsigned long upr = mfspr(SPR_UPR);
+ unsigned long iccfgr, dccfgr;
+
+ if (!(upr & SPR_UPR_UP)) {
+ printk(KERN_INFO
+ "-- no UPR register... unable to detect configuration\n");
+ return -ENOENT;
+ }
+
+ if (cpu_cache_is_present(SPR_UPR_DCP)) {
+ dccfgr = mfspr(SPR_DCCFGR);
+ cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
+ cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
+ cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
+ cpuinfo->dcache.size =
+ cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
+ leaves += 1;
+ printk(KERN_INFO
+ "-- dcache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
+ cpuinfo->dcache.size, cpuinfo->dcache.block_size,
+ cpuinfo->dcache.sets, cpuinfo->dcache.ways);
+ } else
+ printk(KERN_INFO "-- dcache disabled\n");
+
+ if (cpu_cache_is_present(SPR_UPR_ICP)) {
+ iccfgr = mfspr(SPR_ICCFGR);
+ cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
+ cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
+ cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
+ cpuinfo->icache.size =
+ cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
+ leaves += 1;
+ printk(KERN_INFO
+ "-- icache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
+ cpuinfo->icache.size, cpuinfo->icache.block_size,
+ cpuinfo->icache.sets, cpuinfo->icache.ways);
+ } else
+ printk(KERN_INFO "-- icache disabled\n");
+
+ if (!leaves)
+ return -ENOENT;
+
+ levels = 1;
+
+ this_cpu_ci->num_leaves = leaves;
+ this_cpu_ci->num_levels = levels;
+
+ return 0;
+}
+
+int populate_cache_leaves(unsigned int cpu)
+{
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+ struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+ int level = 1;
+
+ if (cpu_cache_is_present(SPR_UPR_DCP)) {
+ ci_leaf_init(this_leaf, CACHE_TYPE_DATA, level, &cpuinfo->dcache, cpu);
+ this_leaf->attributes = ((mfspr(SPR_DCCFGR) & SPR_DCCFGR_CWS) >> 8) ?
+ CACHE_WRITE_BACK : CACHE_WRITE_THROUGH;
+ this_leaf++;
+ }
+
+ if (cpu_cache_is_present(SPR_UPR_ICP))
+ ci_leaf_init(this_leaf, CACHE_TYPE_INST, level, &cpuinfo->icache, cpu);
+
+ this_cpu_ci->cpu_map_populated = true;
+
+ return 0;
+}
diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c
index 66207cd7bb9e..a9fb9cc6779e 100644
--- a/arch/openrisc/kernel/setup.c
+++ b/arch/openrisc/kernel/setup.c
@@ -113,21 +113,6 @@ static void print_cpuinfo(void)
return;
}
- if (upr & SPR_UPR_DCP)
- printk(KERN_INFO
- "-- dcache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
- cpuinfo->dcache.size, cpuinfo->dcache.block_size,
- cpuinfo->dcache.sets, cpuinfo->dcache.ways);
- else
- printk(KERN_INFO "-- dcache disabled\n");
- if (upr & SPR_UPR_ICP)
- printk(KERN_INFO
- "-- icache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
- cpuinfo->icache.size, cpuinfo->icache.block_size,
- cpuinfo->icache.sets, cpuinfo->icache.ways);
- else
- printk(KERN_INFO "-- icache disabled\n");
-
if (upr & SPR_UPR_DMP)
printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
@@ -155,7 +140,6 @@ static void print_cpuinfo(void)
void __init setup_cpuinfo(void)
{
struct device_node *cpu;
- unsigned long iccfgr, dccfgr;
int cpu_id = smp_processor_id();
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
@@ -163,20 +147,6 @@ void __init setup_cpuinfo(void)
if (!cpu)
panic("Couldn't find CPU%d in device tree...\n", cpu_id);
- iccfgr = mfspr(SPR_ICCFGR);
- cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
- cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
- cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
- cpuinfo->icache.size =
- cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
-
- dccfgr = mfspr(SPR_DCCFGR);
- cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
- cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
- cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
- cpuinfo->dcache.size =
- cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
-
if (of_property_read_u32(cpu, "clock-frequency",
&cpuinfo->clock_frequency)) {
printk(KERN_WARNING
@@ -293,14 +263,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
unsigned int vr, cpucfgr;
unsigned int avr;
unsigned int version;
+#ifdef CONFIG_SMP
struct cpuinfo_or1k *cpuinfo = v;
+ seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
+#endif
vr = mfspr(SPR_VR);
cpucfgr = mfspr(SPR_CPUCFGR);
-#ifdef CONFIG_SMP
- seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
-#endif
if (vr & SPR_VR_UVRP) {
vr = mfspr(SPR_VR2);
version = vr & SPR_VR2_VER;
@@ -319,14 +289,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
}
seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
- seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache.size);
- seq_printf(m, "dcache block size\t: %d bytes\n",
- cpuinfo->dcache.block_size);
- seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache.ways);
- seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache.size);
- seq_printf(m, "icache block size\t: %d bytes\n",
- cpuinfo->icache.block_size);
- seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache.ways);
seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
--
2.48.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v5 0/3] openrisc: Add cacheinfo support and introduce new utility functions
2025-03-29 9:46 [PATCH v5 0/3] openrisc: Add cacheinfo support and introduce new utility functions Sahil Siddiq
` (2 preceding siblings ...)
2025-03-29 9:46 ` [PATCH v5 3/3] openrisc: Add cacheinfo support Sahil Siddiq
@ 2025-03-29 10:12 ` Stafford Horne
2025-03-29 19:13 ` Sahil Siddiq
3 siblings, 1 reply; 6+ messages in thread
From: Stafford Horne @ 2025-03-29 10:12 UTC (permalink / raw)
To: Sahil Siddiq
Cc: jonas, stefan.kristiansson, sahilcdq, linux-openrisc,
linux-kernel
Thanks for the respin.
I will take this version and put it in linux next to see if any issues come up.
-Stafford
On Sat, Mar 29, 2025 at 03:16:19PM +0530, Sahil Siddiq wrote:
> Hi,
>
> The main purpose of this series is to expose CPU cache attributes for
> OpenRISC in sysfs using the cacheinfo API. The core implementation
> to achieve this is in patch #3. Patch #1 and #2 add certain enhancements
> to simplify the implementation of cacheinfo support.
>
> Patch #1 removes duplication of cache-related data members in struct
> cpuinfo_or1k.
>
> Patch #2 introduces several utility functions. One set of functions is
> used to check if the cache components and SPRs exist before attempting
> to use them. The other set provides a convenient interface to flush or
> invalidate a range of cache blocks.
>
> While testing these changes with QEMU, I realized that the check being
> performed in cpu_cache_is_present() would always get evaluated to true
> when the UPR_UP bit was set. This series fixes this check and addresses
> v4's review comments.
>
> Thanks,
> Sahil
>
> Sahil Siddiq (3):
> openrisc: Refactor struct cpuinfo_or1k to reduce duplication
> openrisc: Introduce new utility functions to flush and invalidate
> caches
> openrisc: Add cacheinfo support
>
> arch/openrisc/include/asm/cacheflush.h | 17 ++++
> arch/openrisc/include/asm/cpuinfo.h | 24 ++++--
> arch/openrisc/kernel/Makefile | 2 +-
> arch/openrisc/kernel/cacheinfo.c | 104 +++++++++++++++++++++++++
> arch/openrisc/kernel/dma.c | 18 +----
> arch/openrisc/kernel/setup.c | 45 +----------
> arch/openrisc/mm/cache.c | 56 ++++++++++---
> arch/openrisc/mm/init.c | 5 +-
> 8 files changed, 196 insertions(+), 75 deletions(-)
> create mode 100644 arch/openrisc/kernel/cacheinfo.c
>
>
> base-commit: ea1413e5b53a8dd4fa7675edb23cdf828bbdce1e
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v5 0/3] openrisc: Add cacheinfo support and introduce new utility functions
2025-03-29 10:12 ` [PATCH v5 0/3] openrisc: Add cacheinfo support and introduce new utility functions Stafford Horne
@ 2025-03-29 19:13 ` Sahil Siddiq
0 siblings, 0 replies; 6+ messages in thread
From: Sahil Siddiq @ 2025-03-29 19:13 UTC (permalink / raw)
To: Stafford Horne
Cc: jonas, stefan.kristiansson, sahilcdq, linux-openrisc,
linux-kernel
Hi,
On 3/29/25 3:42 PM, Stafford Horne wrote:
> Thanks for the respin.
>
> I will take this version and put it in linux next to see if any issues come up.
>
> -Stafford
Sounds good. Let me know if any more changes are required.
> On Sat, Mar 29, 2025 at 03:16:19PM +0530, Sahil Siddiq wrote:
>> Hi,
>>
>> The main purpose of this series is to expose CPU cache attributes for
>> OpenRISC in sysfs using the cacheinfo API. The core implementation
>> to achieve this is in patch #3. Patch #1 and #2 add certain enhancements
>> to simplify the implementation of cacheinfo support.
>>
>> Patch #1 removes duplication of cache-related data members in struct
>> cpuinfo_or1k.
>>
>> Patch #2 introduces several utility functions. One set of functions is
>> used to check if the cache components and SPRs exist before attempting
>> to use them. The other set provides a convenient interface to flush or
>> invalidate a range of cache blocks.
>>
>> While testing these changes with QEMU, I realized that the check being
>> performed in cpu_cache_is_present() would always get evaluated to true
>> when the UPR_UP bit was set. This series fixes this check and addresses
>> v4's review comments.
>>
>> Thanks,
>> Sahil
>>
>> Sahil Siddiq (3):
>> openrisc: Refactor struct cpuinfo_or1k to reduce duplication
>> openrisc: Introduce new utility functions to flush and invalidate
>> caches
>> openrisc: Add cacheinfo support
>>
>> arch/openrisc/include/asm/cacheflush.h | 17 ++++
>> arch/openrisc/include/asm/cpuinfo.h | 24 ++++--
>> arch/openrisc/kernel/Makefile | 2 +-
>> arch/openrisc/kernel/cacheinfo.c | 104 +++++++++++++++++++++++++
>> arch/openrisc/kernel/dma.c | 18 +----
>> arch/openrisc/kernel/setup.c | 45 +----------
>> arch/openrisc/mm/cache.c | 56 ++++++++++---
>> arch/openrisc/mm/init.c | 5 +-
>> 8 files changed, 196 insertions(+), 75 deletions(-)
>> create mode 100644 arch/openrisc/kernel/cacheinfo.c
>>
>>
>> base-commit: ea1413e5b53a8dd4fa7675edb23cdf828bbdce1e
>> --
>> 2.48.1
>>
Thanks,
Sahil
^ permalink raw reply [flat|nested] 6+ messages in thread