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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4efe6c525sm11773058f8f.23.2025.06.01.08.38.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jun 2025 08:38:50 -0700 (PDT) From: Stafford Horne To: GDB patches Cc: Linux OpenRISC , Stafford Horne Subject: [PATCH] or1k: Add support for numcores and coreid sprs Date: Sun, 1 Jun 2025 16:38:46 +0100 Message-ID: <20250601153846.2284325-1-shorne@gmail.com> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-openrisc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit These are needed when running GCC tests for newlib toolchains built with multicore support. Without these SPRs we get the following warnings when running tests. spawn or1k-elf-run ./20000112-1.exe^M WARNING: l.mfspr with invalid SPR address 0x80^M WARNING: l.mfspr with invalid SPR address 0x81^M WARNING: l.mfspr with invalid SPR address 0x81^M WARNING: l.mfspr with invalid SPR address 0x81^M Support is added by defining the SPRs in the cgen machine definition and regenerating the machine code. In or1k/or1k.c we initialize NUMCORES to 1 and COREID to 0 as the sim has only one CPU. In or1k/traps.c we allow returning the NUMCORES and COREID spr values in the mfspr function. Signed-off-by: Stafford Horne --- cpu/or1kcommon.cpu | 2 + opcodes/or1k-desc.c | 2 + opcodes/or1k-desc.h | 547 ++++++++++++++++++++++---------------------- sim/or1k/cpu.c | 32 +++ sim/or1k/cpu.h | 14 ++ sim/or1k/or1k.c | 4 + sim/or1k/traps.c | 2 + 7 files changed, 330 insertions(+), 273 deletions(-) diff --git a/cpu/or1kcommon.cpu b/cpu/or1kcommon.cpu index 9f102c93a18..7f91954e570 100644 --- a/cpu/or1kcommon.cpu +++ b/cpu/or1kcommon.cpu @@ -243,6 +243,8 @@ (.unsplice (.map (.pmacro (n) (.splice SYS (.sym "ESR" n) (.add n #x40) (.str "Exception supervision register " n))) (.iota #x10))) + (SYS COREID #x080 "Core identifier register") + (SYS NUMCORES #x081 "Number of cores register") (.unsplice (.map (.pmacro (n) (.splice SYS (.sym "GPR" n) (.add n #x400) (.str "General purpose register " n))) (.iota #x200))) diff --git a/opcodes/or1k-desc.c b/opcodes/or1k-desc.c index 9b8aa08699f..90db200fc6c 100644 --- a/opcodes/or1k-desc.c +++ b/opcodes/or1k-desc.c @@ -302,6 +302,8 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] = { "h-sys-esr13", HW_H_SYS_ESR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<