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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490454ea134sm103216805e9.8.2026.05.22.22.36.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2026 22:36:47 -0700 (PDT) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne Subject: [PATCH 0/3] OpenRISC Fixes for jump_label SMP Syncing Date: Sat, 23 May 2026 06:36:15 +0100 Message-ID: <20260523053624.630443-1-shorne@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-openrisc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On OpenRISC I noticed our jump_label implementation based on arm64 uses kick_all_cpus_sync() to force remote cores to pick up static_key updates. The call to kick_all_cpus_sync() on OpenRISC does run IPIs on remote cores, but it does not have any guarantees about instruction cache invalidation. The jump_label code seems to work fine and passes tests, but I had suspicions that this was incorrect. My suspicion was correct, and I was able to reproduce issues where static_keys on remote cores were left stale after jump_label updates using a custom test [0]. This series fixes the issues by triggering remote icache invalidation after jump_label text patching is done. [0] https://github.com/stffrdhrn/or1k-utils/tree/master/tests/smp_static_key_test Stafford Horne (3): openrisc: Cache invalidation cleanup openrisc: Add full instruction cache invalidate functions openrisc: Fix jump_label smp syncing arch/openrisc/include/asm/cacheflush.h | 4 ++++ arch/openrisc/kernel/head.S | 10 ---------- arch/openrisc/kernel/jump_label.c | 2 +- arch/openrisc/kernel/patching.c | 3 +++ arch/openrisc/kernel/smp.c | 21 +++++++++++++++++++++ arch/openrisc/mm/cache.c | 16 ++++++++++++++++ 6 files changed, 45 insertions(+), 11 deletions(-) -- 2.53.0