Re: [Questions] Inquiry about OpenRISC Multi-Core Support Status

[Sahil Siddiq <icegambit91@gmail.com>]

Hi Gary,

I'll try to answer as many queries as best as I can, and leave the rest to be
answered by more knowledgeable members in the community.

On 7/15/25 9:30 AM, Gary Lau wrote:
> Dear OpenRISC developers and community,
> 
> I’m reaching out to inquire about the current status of multi-core support in OpenRISC. Could you please share some details on:
> 1. What is the maximum number of OpenRISC cores currently supported in the Linux kernel?

I see that there's an option to set anywhere between 2 and 32 (both inclusive)
CPUs in the config, with 2 being the default. [1]

> 2. Which specific or1k core implementation(s) are being used for multi-core support (e.g., mor1kx, marocchino etc.)?

According to their READMEs, mor1kx [2] and marocchino [3] both have options
for SMP. Note that marocchino is a rewrite of mor1kx Cappuccino. Cappuccino
is 1 of 3 pipeline implementations in mor1kx. You can read about them further
here [4].

Maybe someone can expand on this answer.

> 3. How many cores have been successfully tested and validated, either in real hardware or simulation environments?
> 4. Which simulators (e.g., QEMU, or1ksim, etc.) support multi-core OpenRISC emulation, and what are their limitations?

I don't think or1ksim supports it based on the documentation [5]. I think
it's best if someone confirms this.

However, I see QEMU has support for SMP. [6][7][8]

Again, I am not sure what its limitations are.

> 5. What are the recommended versions of Linux kernel and GCC toolchain for multi-core OpenRISC development?
> 6. Are there any available documentation or reference materials regarding OpenRISC SMP/multi-core implementation?

Section 10 of the architecture manual might be what you are looking for. [9]

> 7. Are there any particular considerations or limitations I should be aware of when working with multi-core OpenRISC systems?
> 
> Any insights, experiences, or pointers to relevant resources would be greatly appreciated. Thank you for your time and contributions to the OpenRISC ecosystem.
> 
> Best regards,
> Gary

Thanks,
Sahil

[1] https://github.com/torvalds/linux/blob/master/arch/openrisc/Kconfig#L182
[2] https://github.com/openrisc/mor1kx
[3] https://github.com/openrisc/or1k_marocchino
[4] https://github.com/openrisc/mor1kx/blob/master/doc/mor1kx.asciidoc (CPU Pipeline Implementations)
[5] https://github.com/openrisc/or1ksim/blob/or1k-master/doc/or1ksim.texi#L1780
[6] https://wiki.qemu.org/Documentation/Platforms/OpenRISC (Last updated in 2022)
[7] https://gitlab.com/qemu-project/qemu/-/blob/master/docs/system/openrisc/virt.rst
[8] https://gitlab.com/qemu-project/qemu/-/blob/master/docs/system/openrisc/or1k-sim.rst
[9] https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf