* [PATCH v3 1/3] openrisc: Refactor struct cpuinfo_or1k to reduce duplication
2025-03-23 19:55 [PATCH v3 0/3] openrisc: Add cacheinfo support and introduce new utility functions Sahil Siddiq
@ 2025-03-23 19:55 ` Sahil Siddiq
2025-03-26 16:50 ` Stafford Horne
2025-03-23 19:55 ` [PATCH v3 2/3] openrisc: Introduce new utility functions to flush and invalidate caches Sahil Siddiq
2025-03-23 19:55 ` [PATCH v3 3/3] openrisc: Add cacheinfo support Sahil Siddiq
2 siblings, 1 reply; 9+ messages in thread
From: Sahil Siddiq @ 2025-03-23 19:55 UTC (permalink / raw)
To: jonas, stefan.kristiansson, shorne; +Cc: sahilcdq, linux-openrisc, linux-kernel
The "cpuinfo_or1k" structure currently has identical data members for
different cache components.
Remove these fields out of struct cpuinfo_or1k and into its own struct.
This reduces duplication while keeping cpuinfo_or1k extensible so more
cache descriptors can be added in the future.
Also add a new field "sets" to the new structure.
Signed-off-by: Sahil Siddiq <sahilcdq@proton.me>
---
Changes from v1/v2 -> v3:
- arch/openrisc/kernel/setup.c:
(print_cpuinfo):
1. Cascade changes made to struct cpuinfo_or1k.
2. These lines are ultimately shifted to the new file created in
patch #3.
(setup_cpuinfo): Likewise.
(show_cpuinfo): Likewise.
arch/openrisc/include/asm/cpuinfo.h | 16 +++++-----
arch/openrisc/kernel/setup.c | 45 ++++++++++++++---------------
2 files changed, 31 insertions(+), 30 deletions(-)
diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/asm/cpuinfo.h
index 5e4744153d0e..82f5d4c06314 100644
--- a/arch/openrisc/include/asm/cpuinfo.h
+++ b/arch/openrisc/include/asm/cpuinfo.h
@@ -15,16 +15,18 @@
#ifndef __ASM_OPENRISC_CPUINFO_H
#define __ASM_OPENRISC_CPUINFO_H
+struct cache_desc {
+ u32 size;
+ u32 sets;
+ u32 block_size;
+ u32 ways;
+};
+
struct cpuinfo_or1k {
u32 clock_frequency;
- u32 icache_size;
- u32 icache_block_size;
- u32 icache_ways;
-
- u32 dcache_size;
- u32 dcache_block_size;
- u32 dcache_ways;
+ struct cache_desc icache;
+ struct cache_desc dcache;
u16 coreid;
};
diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c
index be56eaafc8b9..66207cd7bb9e 100644
--- a/arch/openrisc/kernel/setup.c
+++ b/arch/openrisc/kernel/setup.c
@@ -115,16 +115,16 @@ static void print_cpuinfo(void)
if (upr & SPR_UPR_DCP)
printk(KERN_INFO
- "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
- cpuinfo->dcache_size, cpuinfo->dcache_block_size,
- cpuinfo->dcache_ways);
+ "-- dcache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
+ cpuinfo->dcache.size, cpuinfo->dcache.block_size,
+ cpuinfo->dcache.sets, cpuinfo->dcache.ways);
else
printk(KERN_INFO "-- dcache disabled\n");
if (upr & SPR_UPR_ICP)
printk(KERN_INFO
- "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
- cpuinfo->icache_size, cpuinfo->icache_block_size,
- cpuinfo->icache_ways);
+ "-- icache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
+ cpuinfo->icache.size, cpuinfo->icache.block_size,
+ cpuinfo->icache.sets, cpuinfo->icache.ways);
else
printk(KERN_INFO "-- icache disabled\n");
@@ -156,7 +156,6 @@ void __init setup_cpuinfo(void)
{
struct device_node *cpu;
unsigned long iccfgr, dccfgr;
- unsigned long cache_set_size;
int cpu_id = smp_processor_id();
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
@@ -165,18 +164,18 @@ void __init setup_cpuinfo(void)
panic("Couldn't find CPU%d in device tree...\n", cpu_id);
iccfgr = mfspr(SPR_ICCFGR);
- cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
- cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
- cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
- cpuinfo->icache_size =
- cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size;
+ cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
+ cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
+ cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
+ cpuinfo->icache.size =
+ cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
dccfgr = mfspr(SPR_DCCFGR);
- cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
- cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
- cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
- cpuinfo->dcache_size =
- cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size;
+ cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
+ cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
+ cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
+ cpuinfo->dcache.size =
+ cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
if (of_property_read_u32(cpu, "clock-frequency",
&cpuinfo->clock_frequency)) {
@@ -320,14 +319,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
}
seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
- seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size);
+ seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache.size);
seq_printf(m, "dcache block size\t: %d bytes\n",
- cpuinfo->dcache_block_size);
- seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways);
- seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size);
+ cpuinfo->dcache.block_size);
+ seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache.ways);
+ seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache.size);
seq_printf(m, "icache block size\t: %d bytes\n",
- cpuinfo->icache_block_size);
- seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways);
+ cpuinfo->icache.block_size);
+ seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache.ways);
seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
--
2.48.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3 1/3] openrisc: Refactor struct cpuinfo_or1k to reduce duplication
2025-03-23 19:55 ` [PATCH v3 1/3] openrisc: Refactor struct cpuinfo_or1k to reduce duplication Sahil Siddiq
@ 2025-03-26 16:50 ` Stafford Horne
0 siblings, 0 replies; 9+ messages in thread
From: Stafford Horne @ 2025-03-26 16:50 UTC (permalink / raw)
To: Sahil Siddiq
Cc: jonas, stefan.kristiansson, sahilcdq, linux-openrisc,
linux-kernel
On Mon, Mar 24, 2025 at 01:25:42AM +0530, Sahil Siddiq wrote:
> The "cpuinfo_or1k" structure currently has identical data members for
> different cache components.
>
> Remove these fields out of struct cpuinfo_or1k and into its own struct.
> This reduces duplication while keeping cpuinfo_or1k extensible so more
> cache descriptors can be added in the future.
>
> Also add a new field "sets" to the new structure.
>
> Signed-off-by: Sahil Siddiq <sahilcdq@proton.me>
This looks ok to me.
> ---
> Changes from v1/v2 -> v3:
> - arch/openrisc/kernel/setup.c:
> (print_cpuinfo):
> 1. Cascade changes made to struct cpuinfo_or1k.
> 2. These lines are ultimately shifted to the new file created in
> patch #3.
> (setup_cpuinfo): Likewise.
> (show_cpuinfo): Likewise.
>
> arch/openrisc/include/asm/cpuinfo.h | 16 +++++-----
> arch/openrisc/kernel/setup.c | 45 ++++++++++++++---------------
> 2 files changed, 31 insertions(+), 30 deletions(-)
>
> diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/asm/cpuinfo.h
> index 5e4744153d0e..82f5d4c06314 100644
> --- a/arch/openrisc/include/asm/cpuinfo.h
> +++ b/arch/openrisc/include/asm/cpuinfo.h
> @@ -15,16 +15,18 @@
> #ifndef __ASM_OPENRISC_CPUINFO_H
> #define __ASM_OPENRISC_CPUINFO_H
>
> +struct cache_desc {
> + u32 size;
> + u32 sets;
> + u32 block_size;
> + u32 ways;
> +};
> +
> struct cpuinfo_or1k {
> u32 clock_frequency;
>
> - u32 icache_size;
> - u32 icache_block_size;
> - u32 icache_ways;
> -
> - u32 dcache_size;
> - u32 dcache_block_size;
> - u32 dcache_ways;
> + struct cache_desc icache;
> + struct cache_desc dcache;
>
> u16 coreid;
> };
> diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c
> index be56eaafc8b9..66207cd7bb9e 100644
> --- a/arch/openrisc/kernel/setup.c
> +++ b/arch/openrisc/kernel/setup.c
> @@ -115,16 +115,16 @@ static void print_cpuinfo(void)
>
> if (upr & SPR_UPR_DCP)
> printk(KERN_INFO
> - "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
> - cpuinfo->dcache_size, cpuinfo->dcache_block_size,
> - cpuinfo->dcache_ways);
> + "-- dcache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
> + cpuinfo->dcache.size, cpuinfo->dcache.block_size,
> + cpuinfo->dcache.sets, cpuinfo->dcache.ways);
> else
> printk(KERN_INFO "-- dcache disabled\n");
> if (upr & SPR_UPR_ICP)
> printk(KERN_INFO
> - "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
> - cpuinfo->icache_size, cpuinfo->icache_block_size,
> - cpuinfo->icache_ways);
> + "-- icache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
> + cpuinfo->icache.size, cpuinfo->icache.block_size,
> + cpuinfo->icache.sets, cpuinfo->icache.ways);
> else
> printk(KERN_INFO "-- icache disabled\n");
>
> @@ -156,7 +156,6 @@ void __init setup_cpuinfo(void)
> {
> struct device_node *cpu;
> unsigned long iccfgr, dccfgr;
> - unsigned long cache_set_size;
> int cpu_id = smp_processor_id();
> struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
>
> @@ -165,18 +164,18 @@ void __init setup_cpuinfo(void)
> panic("Couldn't find CPU%d in device tree...\n", cpu_id);
>
> iccfgr = mfspr(SPR_ICCFGR);
> - cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
> - cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
> - cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
> - cpuinfo->icache_size =
> - cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size;
> + cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
> + cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
> + cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
> + cpuinfo->icache.size =
> + cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
>
> dccfgr = mfspr(SPR_DCCFGR);
> - cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
> - cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
> - cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
> - cpuinfo->dcache_size =
> - cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size;
> + cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
> + cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
> + cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
> + cpuinfo->dcache.size =
> + cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
>
> if (of_property_read_u32(cpu, "clock-frequency",
> &cpuinfo->clock_frequency)) {
> @@ -320,14 +319,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
> seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
> }
> seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
> - seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size);
> + seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache.size);
> seq_printf(m, "dcache block size\t: %d bytes\n",
> - cpuinfo->dcache_block_size);
> - seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways);
> - seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size);
> + cpuinfo->dcache.block_size);
> + seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache.ways);
> + seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache.size);
> seq_printf(m, "icache block size\t: %d bytes\n",
> - cpuinfo->icache_block_size);
> - seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways);
> + cpuinfo->icache.block_size);
> + seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache.ways);
> seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
> 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
> 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 2/3] openrisc: Introduce new utility functions to flush and invalidate caches
2025-03-23 19:55 [PATCH v3 0/3] openrisc: Add cacheinfo support and introduce new utility functions Sahil Siddiq
2025-03-23 19:55 ` [PATCH v3 1/3] openrisc: Refactor struct cpuinfo_or1k to reduce duplication Sahil Siddiq
@ 2025-03-23 19:55 ` Sahil Siddiq
2025-03-26 17:11 ` Stafford Horne
2025-03-23 19:55 ` [PATCH v3 3/3] openrisc: Add cacheinfo support Sahil Siddiq
2 siblings, 1 reply; 9+ messages in thread
From: Sahil Siddiq @ 2025-03-23 19:55 UTC (permalink / raw)
To: jonas, stefan.kristiansson, shorne; +Cc: sahilcdq, linux-openrisc, linux-kernel
According to the OpenRISC architecture manual, the dcache and icache may
not be present. When these caches are present, the invalidate and flush
registers may be absent. The current implementation does not perform
checks to verify their presence before utilizing cache registers, or
invalidating and flushing cache blocks.
Introduce new functions to detect the presence of cache components and
related special-purpose registers.
There are a few places where a range of addresses have to be flushed or
invalidated and the implementation is duplicated. Introduce new utility
functions and macros that generalize this implementation and reduce
duplication.
Signed-off-by: Sahil Siddiq <sahilcdq@proton.me>
---
Changes from v2 -> v3:
- arch/openrisc/include/asm/cacheflush.h: Declare new functions and macros.
- arch/openrisc/include/asm/cpuinfo.h: Implement new functions.
(cpu_cache_is_present):
1. The implementation of this function was strewn all over the place in
the previous versions.
2. Fix condition. The condition in the previous version was incorrect.
(cb_inv_flush_is_implemented): New function.
- arch/openrisc/kernel/dma.c: Use new functions.
- arch/openrisc/mm/cache.c:
(cache_loop): Extend function.
(local_*_page_*): Use new cache_loop interface.
(local_*_range_*): Implement new functions.
- arch/openrisc/mm/init.c: Use new functions.
arch/openrisc/include/asm/cacheflush.h | 17 +++++++++
arch/openrisc/include/asm/cpuinfo.h | 42 +++++++++++++++++++++
arch/openrisc/kernel/dma.c | 18 ++-------
arch/openrisc/mm/cache.c | 52 ++++++++++++++++++++++----
arch/openrisc/mm/init.c | 5 ++-
5 files changed, 110 insertions(+), 24 deletions(-)
diff --git a/arch/openrisc/include/asm/cacheflush.h b/arch/openrisc/include/asm/cacheflush.h
index 984c331ff5f4..0e60af486ec1 100644
--- a/arch/openrisc/include/asm/cacheflush.h
+++ b/arch/openrisc/include/asm/cacheflush.h
@@ -23,6 +23,9 @@
*/
extern void local_dcache_page_flush(struct page *page);
extern void local_icache_page_inv(struct page *page);
+extern void local_dcache_range_flush(unsigned long start, unsigned long end);
+extern void local_dcache_range_inv(unsigned long start, unsigned long end);
+extern void local_icache_range_inv(unsigned long start, unsigned long end);
/*
* Data cache flushing always happen on the local cpu. Instruction cache
@@ -38,6 +41,20 @@ extern void local_icache_page_inv(struct page *page);
extern void smp_icache_page_inv(struct page *page);
#endif /* CONFIG_SMP */
+/*
+ * Even if the actual block size is larger than L1_CACHE_BYTES, paddr
+ * can be incremented by L1_CACHE_BYTES. When paddr is written to the
+ * invalidate register, the entire cache line encompassing this address
+ * is invalidated. Each subsequent reference to the same cache line will
+ * not affect the invalidation process.
+ */
+#define local_dcache_block_flush(addr) \
+ local_dcache_range_flush(addr, addr + L1_CACHE_BYTES)
+#define local_dcache_block_inv(addr) \
+ local_dcache_range_inv(addr, addr + L1_CACHE_BYTES)
+#define local_icache_block_inv(addr) \
+ local_icache_range_inv(addr, addr + L1_CACHE_BYTES)
+
/*
* Synchronizes caches. Whenever a cpu writes executable code to memory, this
* should be called to make sure the processor sees the newly written code.
diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/asm/cpuinfo.h
index 82f5d4c06314..7839c41152af 100644
--- a/arch/openrisc/include/asm/cpuinfo.h
+++ b/arch/openrisc/include/asm/cpuinfo.h
@@ -15,6 +15,9 @@
#ifndef __ASM_OPENRISC_CPUINFO_H
#define __ASM_OPENRISC_CPUINFO_H
+#include <asm/spr.h>
+#include <asm/spr_defs.h>
+
struct cache_desc {
u32 size;
u32 sets;
@@ -34,4 +37,43 @@ struct cpuinfo_or1k {
extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
extern void setup_cpuinfo(void);
+/*
+ * Check if the cache component exists.
+ */
+static inline bool cpu_cache_is_present(const unsigned int cache_type)
+{
+ unsigned long upr = mfspr(SPR_UPR);
+
+ return !!(upr & (SPR_UPR_UP | cache_type));
+}
+
+/*
+ * Check if the cache block flush/invalidate register is implemented for the
+ * cache component.
+ */
+static inline bool cb_inv_flush_is_implemented(const unsigned int reg,
+ const unsigned int cache_type)
+{
+ unsigned long cfgr;
+
+ if (cache_type == SPR_UPR_DCP) {
+ cfgr = mfspr(SPR_DCCFGR);
+ if (reg == SPR_DCBFR)
+ return !!(cfgr & SPR_DCCFGR_CBFRI);
+
+ if (reg == SPR_DCBIR)
+ return !!(cfgr & SPR_DCCFGR_CBIRI);
+ }
+
+ /*
+ * The cache block flush register is not implemented for the instruction cache.
+ */
+ if (cache_type == SPR_UPR_ICP) {
+ cfgr = mfspr(SPR_ICCFGR);
+ return !!(cfgr & SPR_ICCFGR_CBIRI);
+ }
+
+ return false;
+}
+
#endif /* __ASM_OPENRISC_CPUINFO_H */
diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c
index b3edbb33b621..3a7b5baaa450 100644
--- a/arch/openrisc/kernel/dma.c
+++ b/arch/openrisc/kernel/dma.c
@@ -17,6 +17,7 @@
#include <linux/pagewalk.h>
#include <asm/cpuinfo.h>
+#include <asm/cacheflush.h>
#include <asm/spr_defs.h>
#include <asm/tlbflush.h>
@@ -24,9 +25,6 @@ static int
page_set_nocache(pte_t *pte, unsigned long addr,
unsigned long next, struct mm_walk *walk)
{
- unsigned long cl;
- struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
-
pte_val(*pte) |= _PAGE_CI;
/*
@@ -36,8 +34,7 @@ page_set_nocache(pte_t *pte, unsigned long addr,
flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
/* Flush page out of dcache */
- for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size)
- mtspr(SPR_DCBFR, cl);
+ local_dcache_range_flush(__pa(addr), __pa(next));
return 0;
}
@@ -98,21 +95,14 @@ void arch_dma_clear_uncached(void *cpu_addr, size_t size)
void arch_sync_dma_for_device(phys_addr_t addr, size_t size,
enum dma_data_direction dir)
{
- unsigned long cl;
- struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
-
switch (dir) {
case DMA_TO_DEVICE:
/* Flush the dcache for the requested range */
- for (cl = addr; cl < addr + size;
- cl += cpuinfo->dcache_block_size)
- mtspr(SPR_DCBFR, cl);
+ local_dcache_range_flush(addr, addr + size);
break;
case DMA_FROM_DEVICE:
/* Invalidate the dcache for the requested range */
- for (cl = addr; cl < addr + size;
- cl += cpuinfo->dcache_block_size)
- mtspr(SPR_DCBIR, cl);
+ local_dcache_range_inv(addr, addr + size);
break;
default:
/*
diff --git a/arch/openrisc/mm/cache.c b/arch/openrisc/mm/cache.c
index eb43b73f3855..aca64c5a20b3 100644
--- a/arch/openrisc/mm/cache.c
+++ b/arch/openrisc/mm/cache.c
@@ -14,31 +14,67 @@
#include <asm/spr_defs.h>
#include <asm/cache.h>
#include <asm/cacheflush.h>
+#include <asm/cpuinfo.h>
#include <asm/tlbflush.h>
-static __always_inline void cache_loop(struct page *page, const unsigned int reg)
+static __always_inline void cache_loop(struct page *page, unsigned long *start,
+ unsigned long *end, const unsigned int reg,
+ const unsigned int cache_type)
{
- unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
- unsigned long line = paddr & ~(L1_CACHE_BYTES - 1);
+ unsigned long paddr, next;
- while (line < paddr + PAGE_SIZE) {
- mtspr(reg, line);
- line += L1_CACHE_BYTES;
+ if (!cpu_cache_is_present(cache_type))
+ return;
+
+ if (!cb_inv_flush_is_implemented(reg, cache_type))
+ return;
+
+ if (page) {
+ paddr = page_to_pfn(page) << PAGE_SHIFT;
+ next = paddr + PAGE_SIZE;
+ paddr &= ~(L1_CACHE_BYTES - 1);
+ } else if (start && end) {
+ paddr = *start;
+ next = *end;
+ } else {
+ printk(KERN_ERR "Missing start and/or end address.\n");
+ return;
+ }
+
+ while (paddr < next) {
+ mtspr(reg, paddr);
+ paddr += L1_CACHE_BYTES;
}
}
void local_dcache_page_flush(struct page *page)
{
- cache_loop(page, SPR_DCBFR);
+ cache_loop(page, NULL, NULL, SPR_DCBFR, SPR_UPR_DCP);
}
EXPORT_SYMBOL(local_dcache_page_flush);
void local_icache_page_inv(struct page *page)
{
- cache_loop(page, SPR_ICBIR);
+ cache_loop(page, NULL, NULL, SPR_ICBIR, SPR_UPR_ICP);
}
EXPORT_SYMBOL(local_icache_page_inv);
+void local_dcache_range_flush(unsigned long start, unsigned long end)
+{
+ cache_loop(NULL, &start, &end, SPR_DCBFR, SPR_UPR_DCP);
+}
+
+void local_dcache_range_inv(unsigned long start, unsigned long end)
+{
+ cache_loop(NULL, &start, &end, SPR_DCBIR, SPR_UPR_DCP);
+}
+
+void local_icache_range_inv(unsigned long start, unsigned long end)
+{
+ cache_loop(NULL, &start, &end, SPR_ICBIR, SPR_UPR_ICP);
+}
+
+
void update_cache(struct vm_area_struct *vma, unsigned long address,
pte_t *pte)
{
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index d0cb1a0126f9..46b8720db08e 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -35,6 +35,7 @@
#include <asm/fixmap.h>
#include <asm/tlbflush.h>
#include <asm/sections.h>
+#include <asm/cacheflush.h>
int mem_init_done;
@@ -176,8 +177,8 @@ void __init paging_init(void)
barrier();
/* Invalidate instruction caches after code modification */
- mtspr(SPR_ICBIR, 0x900);
- mtspr(SPR_ICBIR, 0xa00);
+ local_icache_block_inv(0x900);
+ local_icache_block_inv(0xa00);
/* New TLB miss handlers and kernel page tables are in now place.
* Make sure that page flags get updated for all pages in TLB by
--
2.48.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3 2/3] openrisc: Introduce new utility functions to flush and invalidate caches
2025-03-23 19:55 ` [PATCH v3 2/3] openrisc: Introduce new utility functions to flush and invalidate caches Sahil Siddiq
@ 2025-03-26 17:11 ` Stafford Horne
2025-03-28 19:40 ` Sahil Siddiq
0 siblings, 1 reply; 9+ messages in thread
From: Stafford Horne @ 2025-03-26 17:11 UTC (permalink / raw)
To: Sahil Siddiq
Cc: jonas, stefan.kristiansson, sahilcdq, linux-openrisc,
linux-kernel
On Mon, Mar 24, 2025 at 01:25:43AM +0530, Sahil Siddiq wrote:
> According to the OpenRISC architecture manual, the dcache and icache may
> not be present. When these caches are present, the invalidate and flush
> registers may be absent. The current implementation does not perform
> checks to verify their presence before utilizing cache registers, or
> invalidating and flushing cache blocks.
>
> Introduce new functions to detect the presence of cache components and
> related special-purpose registers.
>
> There are a few places where a range of addresses have to be flushed or
> invalidated and the implementation is duplicated. Introduce new utility
> functions and macros that generalize this implementation and reduce
> duplication.
>
> Signed-off-by: Sahil Siddiq <sahilcdq@proton.me>
> ---
> Changes from v2 -> v3:
> - arch/openrisc/include/asm/cacheflush.h: Declare new functions and macros.
> - arch/openrisc/include/asm/cpuinfo.h: Implement new functions.
> (cpu_cache_is_present):
> 1. The implementation of this function was strewn all over the place in
> the previous versions.
> 2. Fix condition. The condition in the previous version was incorrect.
> (cb_inv_flush_is_implemented): New function.
> - arch/openrisc/kernel/dma.c: Use new functions.
> - arch/openrisc/mm/cache.c:
> (cache_loop): Extend function.
> (local_*_page_*): Use new cache_loop interface.
> (local_*_range_*): Implement new functions.
> - arch/openrisc/mm/init.c: Use new functions.
>
> arch/openrisc/include/asm/cacheflush.h | 17 +++++++++
> arch/openrisc/include/asm/cpuinfo.h | 42 +++++++++++++++++++++
> arch/openrisc/kernel/dma.c | 18 ++-------
> arch/openrisc/mm/cache.c | 52 ++++++++++++++++++++++----
> arch/openrisc/mm/init.c | 5 ++-
> 5 files changed, 110 insertions(+), 24 deletions(-)
>
> diff --git a/arch/openrisc/include/asm/cacheflush.h b/arch/openrisc/include/asm/cacheflush.h
> index 984c331ff5f4..0e60af486ec1 100644
> --- a/arch/openrisc/include/asm/cacheflush.h
> +++ b/arch/openrisc/include/asm/cacheflush.h
> @@ -23,6 +23,9 @@
> */
> extern void local_dcache_page_flush(struct page *page);
> extern void local_icache_page_inv(struct page *page);
> +extern void local_dcache_range_flush(unsigned long start, unsigned long end);
> +extern void local_dcache_range_inv(unsigned long start, unsigned long end);
> +extern void local_icache_range_inv(unsigned long start, unsigned long end);
>
> /*
> * Data cache flushing always happen on the local cpu. Instruction cache
> @@ -38,6 +41,20 @@ extern void local_icache_page_inv(struct page *page);
> extern void smp_icache_page_inv(struct page *page);
> #endif /* CONFIG_SMP */
>
> +/*
> + * Even if the actual block size is larger than L1_CACHE_BYTES, paddr
> + * can be incremented by L1_CACHE_BYTES. When paddr is written to the
> + * invalidate register, the entire cache line encompassing this address
> + * is invalidated. Each subsequent reference to the same cache line will
> + * not affect the invalidation process.
> + */
> +#define local_dcache_block_flush(addr) \
> + local_dcache_range_flush(addr, addr + L1_CACHE_BYTES)
> +#define local_dcache_block_inv(addr) \
> + local_dcache_range_inv(addr, addr + L1_CACHE_BYTES)
> +#define local_icache_block_inv(addr) \
> + local_icache_range_inv(addr, addr + L1_CACHE_BYTES)
> +
> /*
> * Synchronizes caches. Whenever a cpu writes executable code to memory, this
> * should be called to make sure the processor sees the newly written code.
> diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/asm/cpuinfo.h
> index 82f5d4c06314..7839c41152af 100644
> --- a/arch/openrisc/include/asm/cpuinfo.h
> +++ b/arch/openrisc/include/asm/cpuinfo.h
> @@ -15,6 +15,9 @@
> #ifndef __ASM_OPENRISC_CPUINFO_H
> #define __ASM_OPENRISC_CPUINFO_H
>
> +#include <asm/spr.h>
> +#include <asm/spr_defs.h>
> +
> struct cache_desc {
> u32 size;
> u32 sets;
> @@ -34,4 +37,43 @@ struct cpuinfo_or1k {
> extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
> extern void setup_cpuinfo(void);
>
> +/*
> + * Check if the cache component exists.
> + */
> +static inline bool cpu_cache_is_present(const unsigned int cache_type)
> +{
> + unsigned long upr = mfspr(SPR_UPR);
> +
> + return !!(upr & (SPR_UPR_UP | cache_type));
> +}
> +
> +/*
> + * Check if the cache block flush/invalidate register is implemented for the
> + * cache component.
> + */
> +static inline bool cb_inv_flush_is_implemented(const unsigned int reg,
> + const unsigned int cache_type)
> +{
> + unsigned long cfgr;
> +
> + if (cache_type == SPR_UPR_DCP) {
> + cfgr = mfspr(SPR_DCCFGR);
> + if (reg == SPR_DCBFR)
> + return !!(cfgr & SPR_DCCFGR_CBFRI);
> +
> + if (reg == SPR_DCBIR)
> + return !!(cfgr & SPR_DCCFGR_CBIRI);
> + }
> +
> + /*
> + * The cache block flush register is not implemented for the instruction cache.
> + */
> + if (cache_type == SPR_UPR_ICP) {
> + cfgr = mfspr(SPR_ICCFGR);
> + return !!(cfgr & SPR_ICCFGR_CBIRI);
> + }
> +
> + return false;
> +}
Could these 2 functions move to cache.c?
> #endif /* __ASM_OPENRISC_CPUINFO_H */
> diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c
> index b3edbb33b621..3a7b5baaa450 100644
> --- a/arch/openrisc/kernel/dma.c
> +++ b/arch/openrisc/kernel/dma.c
> @@ -17,6 +17,7 @@
> #include <linux/pagewalk.h>
>
> #include <asm/cpuinfo.h>
> +#include <asm/cacheflush.h>
> #include <asm/spr_defs.h>
> #include <asm/tlbflush.h>
>
> @@ -24,9 +25,6 @@ static int
> page_set_nocache(pte_t *pte, unsigned long addr,
> unsigned long next, struct mm_walk *walk)
> {
> - unsigned long cl;
> - struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
> -
> pte_val(*pte) |= _PAGE_CI;
>
> /*
> @@ -36,8 +34,7 @@ page_set_nocache(pte_t *pte, unsigned long addr,
> flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
>
> /* Flush page out of dcache */
> - for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size)
> - mtspr(SPR_DCBFR, cl);
> + local_dcache_range_flush(__pa(addr), __pa(next));
>
> return 0;
> }
> @@ -98,21 +95,14 @@ void arch_dma_clear_uncached(void *cpu_addr, size_t size)
> void arch_sync_dma_for_device(phys_addr_t addr, size_t size,
> enum dma_data_direction dir)
> {
> - unsigned long cl;
> - struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
> -
> switch (dir) {
> case DMA_TO_DEVICE:
> /* Flush the dcache for the requested range */
> - for (cl = addr; cl < addr + size;
> - cl += cpuinfo->dcache_block_size)
> - mtspr(SPR_DCBFR, cl);
> + local_dcache_range_flush(addr, addr + size);
> break;
> case DMA_FROM_DEVICE:
> /* Invalidate the dcache for the requested range */
> - for (cl = addr; cl < addr + size;
> - cl += cpuinfo->dcache_block_size)
> - mtspr(SPR_DCBIR, cl);
> + local_dcache_range_inv(addr, addr + size);
> break;
> default:
> /*
> diff --git a/arch/openrisc/mm/cache.c b/arch/openrisc/mm/cache.c
> index eb43b73f3855..aca64c5a20b3 100644
> --- a/arch/openrisc/mm/cache.c
> +++ b/arch/openrisc/mm/cache.c
> @@ -14,31 +14,67 @@
> #include <asm/spr_defs.h>
> #include <asm/cache.h>
> #include <asm/cacheflush.h>
> +#include <asm/cpuinfo.h>
> #include <asm/tlbflush.h>
>
> -static __always_inline void cache_loop(struct page *page, const unsigned int reg)
> +static __always_inline void cache_loop(struct page *page, unsigned long *start,
> + unsigned long *end, const unsigned int reg,
> + const unsigned int cache_type)
> {
> - unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
> - unsigned long line = paddr & ~(L1_CACHE_BYTES - 1);
> + unsigned long paddr, next;
>
> - while (line < paddr + PAGE_SIZE) {
> - mtspr(reg, line);
> - line += L1_CACHE_BYTES;
> + if (!cpu_cache_is_present(cache_type))
> + return;
> +
> + if (!cb_inv_flush_is_implemented(reg, cache_type))
> + return;
This check may be a bit overkill, but OK.
> + if (page) {
> + paddr = page_to_pfn(page) << PAGE_SHIFT;
> + next = paddr + PAGE_SIZE;
> + paddr &= ~(L1_CACHE_BYTES - 1);
> + } else if (start && end) {
> + paddr = *start;
> + next = *end;
Overloading the one function with page and start/end seems a bit messy.
It may be nicer to have 2 functions:
cache_loop_page(page, reg, cache_type) {
unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
unsiogned long end = paddr + PAGE_SIZE;
paddr &= ~(L1_CACHE_BYTES - 1);
cache_loop(paddr, end, reg, cache_type);
}
cache_loop(start, end, reg, cache_type)
> + } else {
> + printk(KERN_ERR "Missing start and/or end address.\n");
> + return;
Then this could be removed.
> + }
> +
> + while (paddr < next) {
> + mtspr(reg, paddr);
> + paddr += L1_CACHE_BYTES;
> }
> }
>
> void local_dcache_page_flush(struct page *page)
> {
> - cache_loop(page, SPR_DCBFR);
> + cache_loop(page, NULL, NULL, SPR_DCBFR, SPR_UPR_DCP);
> }
> EXPORT_SYMBOL(local_dcache_page_flush);
>
> void local_icache_page_inv(struct page *page)
> {
> - cache_loop(page, SPR_ICBIR);
> + cache_loop(page, NULL, NULL, SPR_ICBIR, SPR_UPR_ICP);
> }
> EXPORT_SYMBOL(local_icache_page_inv);
>
> +void local_dcache_range_flush(unsigned long start, unsigned long end)
> +{
> + cache_loop(NULL, &start, &end, SPR_DCBFR, SPR_UPR_DCP);
> +}
> +
> +void local_dcache_range_inv(unsigned long start, unsigned long end)
> +{
> + cache_loop(NULL, &start, &end, SPR_DCBIR, SPR_UPR_DCP);
> +}
> +
> +void local_icache_range_inv(unsigned long start, unsigned long end)
> +{
> + cache_loop(NULL, &start, &end, SPR_ICBIR, SPR_UPR_ICP);
> +}
> +
> +
> void update_cache(struct vm_area_struct *vma, unsigned long address,
> pte_t *pte)
> {
> diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
> index d0cb1a0126f9..46b8720db08e 100644
> --- a/arch/openrisc/mm/init.c
> +++ b/arch/openrisc/mm/init.c
> @@ -35,6 +35,7 @@
> #include <asm/fixmap.h>
> #include <asm/tlbflush.h>
> #include <asm/sections.h>
> +#include <asm/cacheflush.h>
>
> int mem_init_done;
>
> @@ -176,8 +177,8 @@ void __init paging_init(void)
> barrier();
>
> /* Invalidate instruction caches after code modification */
> - mtspr(SPR_ICBIR, 0x900);
> - mtspr(SPR_ICBIR, 0xa00);
> + local_icache_block_inv(0x900);
> + local_icache_block_inv(0xa00);
OK.
> /* New TLB miss handlers and kernel page tables are in now place.
> * Make sure that page flags get updated for all pages in TLB by
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v3 2/3] openrisc: Introduce new utility functions to flush and invalidate caches
2025-03-26 17:11 ` Stafford Horne
@ 2025-03-28 19:40 ` Sahil Siddiq
0 siblings, 0 replies; 9+ messages in thread
From: Sahil Siddiq @ 2025-03-28 19:40 UTC (permalink / raw)
To: Stafford Horne
Cc: jonas, stefan.kristiansson, sahilcdq, linux-openrisc,
linux-kernel
Hi,
Thank you for the review.
On 3/26/25 10:41 PM, Stafford Horne wrote:
> On Mon, Mar 24, 2025 at 01:25:43AM +0530, Sahil Siddiq wrote:
>> According to the OpenRISC architecture manual, the dcache and icache may
>> not be present. When these caches are present, the invalidate and flush
>> registers may be absent. The current implementation does not perform
>> checks to verify their presence before utilizing cache registers, or
>> invalidating and flushing cache blocks.
>>
>> Introduce new functions to detect the presence of cache components and
>> related special-purpose registers.
>>
>> There are a few places where a range of addresses have to be flushed or
>> invalidated and the implementation is duplicated. Introduce new utility
>> functions and macros that generalize this implementation and reduce
>> duplication.
>>
>> Signed-off-by: Sahil Siddiq <sahilcdq@proton.me>
>> ---
>> Changes from v2 -> v3:
>> - arch/openrisc/include/asm/cacheflush.h: Declare new functions and macros.
>> - arch/openrisc/include/asm/cpuinfo.h: Implement new functions.
>> (cpu_cache_is_present):
>> 1. The implementation of this function was strewn all over the place in
>> the previous versions.
>> 2. Fix condition. The condition in the previous version was incorrect.
>> (cb_inv_flush_is_implemented): New function.
>> - arch/openrisc/kernel/dma.c: Use new functions.
>> - arch/openrisc/mm/cache.c:
>> (cache_loop): Extend function.
>> (local_*_page_*): Use new cache_loop interface.
>> (local_*_range_*): Implement new functions.
>> - arch/openrisc/mm/init.c: Use new functions.
>>
>> arch/openrisc/include/asm/cacheflush.h | 17 +++++++++
>> arch/openrisc/include/asm/cpuinfo.h | 42 +++++++++++++++++++++
>> arch/openrisc/kernel/dma.c | 18 ++-------
>> arch/openrisc/mm/cache.c | 52 ++++++++++++++++++++++----
>> arch/openrisc/mm/init.c | 5 ++-
>> 5 files changed, 110 insertions(+), 24 deletions(-)
>>
>> diff --git a/arch/openrisc/include/asm/cacheflush.h b/arch/openrisc/include/asm/cacheflush.h
>> index 984c331ff5f4..0e60af486ec1 100644
>> --- a/arch/openrisc/include/asm/cacheflush.h
>> +++ b/arch/openrisc/include/asm/cacheflush.h
>> @@ -23,6 +23,9 @@
>> */
>> extern void local_dcache_page_flush(struct page *page);
>> extern void local_icache_page_inv(struct page *page);
>> +extern void local_dcache_range_flush(unsigned long start, unsigned long end);
>> +extern void local_dcache_range_inv(unsigned long start, unsigned long end);
>> +extern void local_icache_range_inv(unsigned long start, unsigned long end);
>>
>> /*
>> * Data cache flushing always happen on the local cpu. Instruction cache
>> @@ -38,6 +41,20 @@ extern void local_icache_page_inv(struct page *page);
>> extern void smp_icache_page_inv(struct page *page);
>> #endif /* CONFIG_SMP */
>>
>> +/*
>> + * Even if the actual block size is larger than L1_CACHE_BYTES, paddr
>> + * can be incremented by L1_CACHE_BYTES. When paddr is written to the
>> + * invalidate register, the entire cache line encompassing this address
>> + * is invalidated. Each subsequent reference to the same cache line will
>> + * not affect the invalidation process.
>> + */
>> +#define local_dcache_block_flush(addr) \
>> + local_dcache_range_flush(addr, addr + L1_CACHE_BYTES)
>> +#define local_dcache_block_inv(addr) \
>> + local_dcache_range_inv(addr, addr + L1_CACHE_BYTES)
>> +#define local_icache_block_inv(addr) \
>> + local_icache_range_inv(addr, addr + L1_CACHE_BYTES)
>> +
>> /*
>> * Synchronizes caches. Whenever a cpu writes executable code to memory, this
>> * should be called to make sure the processor sees the newly written code.
>> diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/asm/cpuinfo.h
>> index 82f5d4c06314..7839c41152af 100644
>> --- a/arch/openrisc/include/asm/cpuinfo.h
>> +++ b/arch/openrisc/include/asm/cpuinfo.h
>> @@ -15,6 +15,9 @@
>> #ifndef __ASM_OPENRISC_CPUINFO_H
>> #define __ASM_OPENRISC_CPUINFO_H
>>
>> +#include <asm/spr.h>
>> +#include <asm/spr_defs.h>
>> +
>> struct cache_desc {
>> u32 size;
>> u32 sets;
>> @@ -34,4 +37,43 @@ struct cpuinfo_or1k {
>> extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
>> extern void setup_cpuinfo(void);
>>
>> +/*
>> + * Check if the cache component exists.
>> + */
>> +static inline bool cpu_cache_is_present(const unsigned int cache_type)
>> +{
>> + unsigned long upr = mfspr(SPR_UPR);
>> +
>> + return !!(upr & (SPR_UPR_UP | cache_type));
>> +}
>> +
>> +/*
>> + * Check if the cache block flush/invalidate register is implemented for the
>> + * cache component.
>> + */
>> +static inline bool cb_inv_flush_is_implemented(const unsigned int reg,
>> + const unsigned int cache_type)
>> +{
>> + unsigned long cfgr;
>> +
>> + if (cache_type == SPR_UPR_DCP) {
>> + cfgr = mfspr(SPR_DCCFGR);
>> + if (reg == SPR_DCBFR)
>> + return !!(cfgr & SPR_DCCFGR_CBFRI);
>> +
>> + if (reg == SPR_DCBIR)
>> + return !!(cfgr & SPR_DCCFGR_CBIRI);
>> + }
>> +
>> + /*
>> + * The cache block flush register is not implemented for the instruction cache.
>> + */
>> + if (cache_type == SPR_UPR_ICP) {
>> + cfgr = mfspr(SPR_ICCFGR);
>> + return !!(cfgr & SPR_ICCFGR_CBIRI);
>> + }
>> +
>> + return false;
>> +}
>
> Could these 2 functions move to cache.c?
Sure, I'll do that.
>> #endif /* __ASM_OPENRISC_CPUINFO_H */
>> diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c
>> index b3edbb33b621..3a7b5baaa450 100644
>> --- a/arch/openrisc/kernel/dma.c
>> +++ b/arch/openrisc/kernel/dma.c
>> @@ -17,6 +17,7 @@
>> #include <linux/pagewalk.h>
>>
>> #include <asm/cpuinfo.h>
>> +#include <asm/cacheflush.h>
>> #include <asm/spr_defs.h>
>> #include <asm/tlbflush.h>
>>
>> @@ -24,9 +25,6 @@ static int
>> page_set_nocache(pte_t *pte, unsigned long addr,
>> unsigned long next, struct mm_walk *walk)
>> {
>> - unsigned long cl;
>> - struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
>> -
>> pte_val(*pte) |= _PAGE_CI;
>>
>> /*
>> @@ -36,8 +34,7 @@ page_set_nocache(pte_t *pte, unsigned long addr,
>> flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
>>
>> /* Flush page out of dcache */
>> - for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size)
>> - mtspr(SPR_DCBFR, cl);
>> + local_dcache_range_flush(__pa(addr), __pa(next));
>>
>> return 0;
>> }
>> @@ -98,21 +95,14 @@ void arch_dma_clear_uncached(void *cpu_addr, size_t size)
>> void arch_sync_dma_for_device(phys_addr_t addr, size_t size,
>> enum dma_data_direction dir)
>> {
>> - unsigned long cl;
>> - struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
>> -
>> switch (dir) {
>> case DMA_TO_DEVICE:
>> /* Flush the dcache for the requested range */
>> - for (cl = addr; cl < addr + size;
>> - cl += cpuinfo->dcache_block_size)
>> - mtspr(SPR_DCBFR, cl);
>> + local_dcache_range_flush(addr, addr + size);
>> break;
>> case DMA_FROM_DEVICE:
>> /* Invalidate the dcache for the requested range */
>> - for (cl = addr; cl < addr + size;
>> - cl += cpuinfo->dcache_block_size)
>> - mtspr(SPR_DCBIR, cl);
>> + local_dcache_range_inv(addr, addr + size);
>> break;
>> default:
>> /*
>> diff --git a/arch/openrisc/mm/cache.c b/arch/openrisc/mm/cache.c
>> index eb43b73f3855..aca64c5a20b3 100644
>> --- a/arch/openrisc/mm/cache.c
>> +++ b/arch/openrisc/mm/cache.c
>> @@ -14,31 +14,67 @@
>> #include <asm/spr_defs.h>
>> #include <asm/cache.h>
>> #include <asm/cacheflush.h>
>> +#include <asm/cpuinfo.h>
>> #include <asm/tlbflush.h>
>>
>> -static __always_inline void cache_loop(struct page *page, const unsigned int reg)
>> +static __always_inline void cache_loop(struct page *page, unsigned long *start,
>> + unsigned long *end, const unsigned int reg,
>> + const unsigned int cache_type)
>> {
>> - unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
>> - unsigned long line = paddr & ~(L1_CACHE_BYTES - 1);
>> + unsigned long paddr, next;
>>
>> - while (line < paddr + PAGE_SIZE) {
>> - mtspr(reg, line);
>> - line += L1_CACHE_BYTES;
>> + if (!cpu_cache_is_present(cache_type))
>> + return;
>> +
>> + if (!cb_inv_flush_is_implemented(reg, cache_type))
>> + return;
>
> This check may be a bit overkill, but OK.
I thought I would implement this because I was not sure of what would happen
when attempting to read from these registers in a processor that didn't have
them.
>> + if (page) {
>> + paddr = page_to_pfn(page) << PAGE_SHIFT;
>> + next = paddr + PAGE_SIZE;
>> + paddr &= ~(L1_CACHE_BYTES - 1);
>> + } else if (start && end) {
>> + paddr = *start;
>> + next = *end;
>
> Overloading the one function with page and start/end seems a bit messy.
>
> It may be nicer to have 2 functions:
>
> cache_loop_page(page, reg, cache_type) {
> unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
> unsiogned long end = paddr + PAGE_SIZE;
> paddr &= ~(L1_CACHE_BYTES - 1);
> cache_loop(paddr, end, reg, cache_type);
> }
>
> cache_loop(start, end, reg, cache_type)
>
>> + } else {
>> + printk(KERN_ERR "Missing start and/or end address.\n");
>> + return;
>
> Then this could be removed.
I agree. This is cleaner. I'll make the relevant changes.
Thanks,
Sahil
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] openrisc: Add cacheinfo support
2025-03-23 19:55 [PATCH v3 0/3] openrisc: Add cacheinfo support and introduce new utility functions Sahil Siddiq
2025-03-23 19:55 ` [PATCH v3 1/3] openrisc: Refactor struct cpuinfo_or1k to reduce duplication Sahil Siddiq
2025-03-23 19:55 ` [PATCH v3 2/3] openrisc: Introduce new utility functions to flush and invalidate caches Sahil Siddiq
@ 2025-03-23 19:55 ` Sahil Siddiq
2025-03-23 22:52 ` kernel test robot
2025-03-26 17:13 ` Stafford Horne
2 siblings, 2 replies; 9+ messages in thread
From: Sahil Siddiq @ 2025-03-23 19:55 UTC (permalink / raw)
To: jonas, stefan.kristiansson, shorne; +Cc: sahilcdq, linux-openrisc, linux-kernel
Add cacheinfo support for OpenRISC.
Currently, a few CPU cache attributes pertaining to OpenRISC processors
are exposed along with other unrelated CPU attributes in the procfs file
system (/proc/cpuinfo). However, a few cache attributes remain unexposed.
Provide a mechanism that the generic cacheinfo infrastructure can employ
to expose these attributes via the sysfs file system. These attributes
can then be exposed in /sys/devices/system/cpu/cpuX/cache/indexN. Move
the implementation to pull cache attributes from the processor's
registers from arch/openrisc/kernel/setup.c with a few modifications.
This implementation is based on similar work done for MIPS and LoongArch.
Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Sahil Siddiq <sahilcdq@proton.me>
---
Changes from v2 -> v3:
- arch/openrisc/kernel/cacheinfo.c:
1. Use new functions introduced in patch #2.
2. Address review comments regarding coding style.
- arch/openrisc/kernel/setup.c:
(print_cpuinfo): Don't remove detection of UPR register.
arch/openrisc/kernel/Makefile | 2 +-
arch/openrisc/kernel/cacheinfo.c | 104 +++++++++++++++++++++++++++++++
arch/openrisc/kernel/setup.c | 38 -----------
3 files changed, 105 insertions(+), 39 deletions(-)
create mode 100644 arch/openrisc/kernel/cacheinfo.c
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index 79129161f3e0..e4c7d9bdd598 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -7,7 +7,7 @@ extra-y := vmlinux.lds
obj-y := head.o setup.o or32_ksyms.o process.o dma.o \
traps.o time.o irq.o entry.o ptrace.o signal.o \
- sys_call_table.o unwinder.o
+ sys_call_table.o unwinder.o cacheinfo.o
obj-$(CONFIG_SMP) += smp.o sync-timer.o
obj-$(CONFIG_STACKTRACE) += stacktrace.o
diff --git a/arch/openrisc/kernel/cacheinfo.c b/arch/openrisc/kernel/cacheinfo.c
new file mode 100644
index 000000000000..61230545e4ff
--- /dev/null
+++ b/arch/openrisc/kernel/cacheinfo.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * OpenRISC cacheinfo support
+ *
+ * Based on work done for MIPS and LoongArch. All original copyrights
+ * apply as per the original source declaration.
+ *
+ * OpenRISC implementation:
+ * Copyright (C) 2025 Sahil Siddiq <sahilcdq@proton.me>
+ */
+
+#include <linux/cacheinfo.h>
+#include <asm/cpuinfo.h>
+#include <asm/spr.h>
+#include <asm/spr_defs.h>
+
+static inline void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type,
+ unsigned int level, struct cache_desc *cache, int cpu)
+{
+ this_leaf->type = type;
+ this_leaf->level = level;
+ this_leaf->coherency_line_size = cache->block_size;
+ this_leaf->number_of_sets = cache->sets;
+ this_leaf->ways_of_associativity = cache->ways;
+ this_leaf->size = cache->size;
+ cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map);
+}
+
+int init_cache_level(unsigned int cpu)
+{
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+ int leaves = 0, levels = 0;
+ unsigned long upr = mfspr(SPR_UPR);
+ unsigned long iccfgr, dccfgr;
+
+ if (!(upr & SPR_UPR_UP)) {
+ printk(KERN_INFO
+ "-- no UPR register... unable to detect configuration\n");
+ return -ENOENT;
+ }
+
+ if (cpu_cache_is_present(SPR_UPR_DCP)) {
+ dccfgr = mfspr(SPR_DCCFGR);
+ cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
+ cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
+ cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
+ cpuinfo->dcache.size =
+ cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
+ leaves += 1;
+ printk(KERN_INFO
+ "-- dcache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
+ cpuinfo->dcache.size, cpuinfo->dcache.block_size,
+ cpuinfo->dcache.sets, cpuinfo->dcache.ways);
+ } else
+ printk(KERN_INFO "-- dcache disabled\n");
+
+ if (cpu_cache_is_present(SPR_UPR_ICP)) {
+ iccfgr = mfspr(SPR_ICCFGR);
+ cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
+ cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
+ cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
+ cpuinfo->icache.size =
+ cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
+ leaves += 1;
+ printk(KERN_INFO
+ "-- icache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
+ cpuinfo->icache.size, cpuinfo->icache.block_size,
+ cpuinfo->icache.sets, cpuinfo->icache.ways);
+ } else
+ printk(KERN_INFO "-- icache disabled\n");
+
+ if (!leaves)
+ return -ENOENT;
+
+ levels = 1;
+
+ this_cpu_ci->num_leaves = leaves;
+ this_cpu_ci->num_levels = levels;
+
+ return 0;
+}
+
+int populate_cache_leaves(unsigned int cpu)
+{
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+ struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+ int level = 1;
+
+ if (cpu_cache_is_present(SPR_UPR_DCP)) {
+ ci_leaf_init(this_leaf, CACHE_TYPE_DATA, level, &cpuinfo->dcache, cpu);
+ this_leaf->attributes = ((mfspr(SPR_DCCFGR) & SPR_DCCFGR_CWS) >> 8) ?
+ CACHE_WRITE_BACK : CACHE_WRITE_THROUGH;
+ this_leaf++;
+ }
+
+ if (cpu_cache_is_present(SPR_UPR_ICP))
+ ci_leaf_init(this_leaf, CACHE_TYPE_INST, level, &cpuinfo->icache, cpu);
+
+ this_cpu_ci->cpu_map_populated = true;
+
+ return 0;
+}
diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c
index 66207cd7bb9e..caac492d045e 100644
--- a/arch/openrisc/kernel/setup.c
+++ b/arch/openrisc/kernel/setup.c
@@ -113,21 +113,6 @@ static void print_cpuinfo(void)
return;
}
- if (upr & SPR_UPR_DCP)
- printk(KERN_INFO
- "-- dcache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
- cpuinfo->dcache.size, cpuinfo->dcache.block_size,
- cpuinfo->dcache.sets, cpuinfo->dcache.ways);
- else
- printk(KERN_INFO "-- dcache disabled\n");
- if (upr & SPR_UPR_ICP)
- printk(KERN_INFO
- "-- icache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
- cpuinfo->icache.size, cpuinfo->icache.block_size,
- cpuinfo->icache.sets, cpuinfo->icache.ways);
- else
- printk(KERN_INFO "-- icache disabled\n");
-
if (upr & SPR_UPR_DMP)
printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
@@ -155,7 +140,6 @@ static void print_cpuinfo(void)
void __init setup_cpuinfo(void)
{
struct device_node *cpu;
- unsigned long iccfgr, dccfgr;
int cpu_id = smp_processor_id();
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
@@ -163,20 +147,6 @@ void __init setup_cpuinfo(void)
if (!cpu)
panic("Couldn't find CPU%d in device tree...\n", cpu_id);
- iccfgr = mfspr(SPR_ICCFGR);
- cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
- cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
- cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
- cpuinfo->icache.size =
- cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
-
- dccfgr = mfspr(SPR_DCCFGR);
- cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
- cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
- cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
- cpuinfo->dcache.size =
- cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
-
if (of_property_read_u32(cpu, "clock-frequency",
&cpuinfo->clock_frequency)) {
printk(KERN_WARNING
@@ -319,14 +289,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
}
seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
- seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache.size);
- seq_printf(m, "dcache block size\t: %d bytes\n",
- cpuinfo->dcache.block_size);
- seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache.ways);
- seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache.size);
- seq_printf(m, "icache block size\t: %d bytes\n",
- cpuinfo->icache.block_size);
- seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache.ways);
seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
--
2.48.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3 3/3] openrisc: Add cacheinfo support
2025-03-23 19:55 ` [PATCH v3 3/3] openrisc: Add cacheinfo support Sahil Siddiq
@ 2025-03-23 22:52 ` kernel test robot
2025-03-26 17:13 ` Stafford Horne
1 sibling, 0 replies; 9+ messages in thread
From: kernel test robot @ 2025-03-23 22:52 UTC (permalink / raw)
To: Sahil Siddiq, jonas, stefan.kristiansson, shorne
Cc: oe-kbuild-all, sahilcdq, linux-openrisc, linux-kernel
Hi Sahil,
kernel test robot noticed the following build warnings:
[auto build test WARNING on ea1413e5b53a8dd4fa7675edb23cdf828bbdce1e]
url: https://github.com/intel-lab-lkp/linux/commits/Sahil-Siddiq/openrisc-Refactor-struct-cpuinfo_or1k-to-reduce-duplication/20250324-035738
base: ea1413e5b53a8dd4fa7675edb23cdf828bbdce1e
patch link: https://lore.kernel.org/r/20250323195544.152948-4-sahilcdq%40proton.me
patch subject: [PATCH v3 3/3] openrisc: Add cacheinfo support
config: openrisc-allnoconfig (https://download.01.org/0day-ci/archive/20250324/202503240635.ir63jqTI-lkp@intel.com/config)
compiler: or1k-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250324/202503240635.ir63jqTI-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503240635.ir63jqTI-lkp@intel.com/
All warnings (new ones prefixed by >>):
arch/openrisc/kernel/setup.c: In function 'show_cpuinfo':
>> arch/openrisc/kernel/setup.c:266:30: warning: unused variable 'cpuinfo' [-Wunused-variable]
266 | struct cpuinfo_or1k *cpuinfo = v;
| ^~~~~~~
vim +/cpuinfo +266 arch/openrisc/kernel/setup.c
9d02a4283e9ce4 Jonas Bonn 2011-06-04 260
9d02a4283e9ce4 Jonas Bonn 2011-06-04 261 static int show_cpuinfo(struct seq_file *m, void *v)
9d02a4283e9ce4 Jonas Bonn 2011-06-04 262 {
8e6d08e0a15e7d Stefan Kristiansson 2014-05-11 263 unsigned int vr, cpucfgr;
8e6d08e0a15e7d Stefan Kristiansson 2014-05-11 264 unsigned int avr;
8e6d08e0a15e7d Stefan Kristiansson 2014-05-11 265 unsigned int version;
8e6d08e0a15e7d Stefan Kristiansson 2014-05-11 @266 struct cpuinfo_or1k *cpuinfo = v;
9d02a4283e9ce4 Jonas Bonn 2011-06-04 267
9d02a4283e9ce4 Jonas Bonn 2011-06-04 268 vr = mfspr(SPR_VR);
8e6d08e0a15e7d Stefan Kristiansson 2014-05-11 269 cpucfgr = mfspr(SPR_CPUCFGR);
8e6d08e0a15e7d Stefan Kristiansson 2014-05-11 270
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v3 3/3] openrisc: Add cacheinfo support
2025-03-23 19:55 ` [PATCH v3 3/3] openrisc: Add cacheinfo support Sahil Siddiq
2025-03-23 22:52 ` kernel test robot
@ 2025-03-26 17:13 ` Stafford Horne
1 sibling, 0 replies; 9+ messages in thread
From: Stafford Horne @ 2025-03-26 17:13 UTC (permalink / raw)
To: Sahil Siddiq
Cc: jonas, stefan.kristiansson, sahilcdq, linux-openrisc,
linux-kernel
On Mon, Mar 24, 2025 at 01:25:44AM +0530, Sahil Siddiq wrote:
> Add cacheinfo support for OpenRISC.
>
> Currently, a few CPU cache attributes pertaining to OpenRISC processors
> are exposed along with other unrelated CPU attributes in the procfs file
> system (/proc/cpuinfo). However, a few cache attributes remain unexposed.
>
> Provide a mechanism that the generic cacheinfo infrastructure can employ
> to expose these attributes via the sysfs file system. These attributes
> can then be exposed in /sys/devices/system/cpu/cpuX/cache/indexN. Move
> the implementation to pull cache attributes from the processor's
> registers from arch/openrisc/kernel/setup.c with a few modifications.
>
> This implementation is based on similar work done for MIPS and LoongArch.
>
> Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
>
> Signed-off-by: Sahil Siddiq <sahilcdq@proton.me>
Other than the test robot's complaint about the unused variable this looks ok to
me.
-Stafford
> ---
> Changes from v2 -> v3:
> - arch/openrisc/kernel/cacheinfo.c:
> 1. Use new functions introduced in patch #2.
> 2. Address review comments regarding coding style.
> - arch/openrisc/kernel/setup.c:
> (print_cpuinfo): Don't remove detection of UPR register.
>
> arch/openrisc/kernel/Makefile | 2 +-
> arch/openrisc/kernel/cacheinfo.c | 104 +++++++++++++++++++++++++++++++
> arch/openrisc/kernel/setup.c | 38 -----------
> 3 files changed, 105 insertions(+), 39 deletions(-)
> create mode 100644 arch/openrisc/kernel/cacheinfo.c
>
> diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
> index 79129161f3e0..e4c7d9bdd598 100644
> --- a/arch/openrisc/kernel/Makefile
> +++ b/arch/openrisc/kernel/Makefile
> @@ -7,7 +7,7 @@ extra-y := vmlinux.lds
>
> obj-y := head.o setup.o or32_ksyms.o process.o dma.o \
> traps.o time.o irq.o entry.o ptrace.o signal.o \
> - sys_call_table.o unwinder.o
> + sys_call_table.o unwinder.o cacheinfo.o
>
> obj-$(CONFIG_SMP) += smp.o sync-timer.o
> obj-$(CONFIG_STACKTRACE) += stacktrace.o
> diff --git a/arch/openrisc/kernel/cacheinfo.c b/arch/openrisc/kernel/cacheinfo.c
> new file mode 100644
> index 000000000000..61230545e4ff
> --- /dev/null
> +++ b/arch/openrisc/kernel/cacheinfo.c
> @@ -0,0 +1,104 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * OpenRISC cacheinfo support
> + *
> + * Based on work done for MIPS and LoongArch. All original copyrights
> + * apply as per the original source declaration.
> + *
> + * OpenRISC implementation:
> + * Copyright (C) 2025 Sahil Siddiq <sahilcdq@proton.me>
> + */
> +
> +#include <linux/cacheinfo.h>
> +#include <asm/cpuinfo.h>
> +#include <asm/spr.h>
> +#include <asm/spr_defs.h>
> +
> +static inline void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type,
> + unsigned int level, struct cache_desc *cache, int cpu)
> +{
> + this_leaf->type = type;
> + this_leaf->level = level;
> + this_leaf->coherency_line_size = cache->block_size;
> + this_leaf->number_of_sets = cache->sets;
> + this_leaf->ways_of_associativity = cache->ways;
> + this_leaf->size = cache->size;
> + cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map);
> +}
> +
> +int init_cache_level(unsigned int cpu)
> +{
> + struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
> + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
> + int leaves = 0, levels = 0;
> + unsigned long upr = mfspr(SPR_UPR);
> + unsigned long iccfgr, dccfgr;
> +
> + if (!(upr & SPR_UPR_UP)) {
> + printk(KERN_INFO
> + "-- no UPR register... unable to detect configuration\n");
> + return -ENOENT;
> + }
> +
> + if (cpu_cache_is_present(SPR_UPR_DCP)) {
> + dccfgr = mfspr(SPR_DCCFGR);
> + cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
> + cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
> + cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
> + cpuinfo->dcache.size =
> + cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
> + leaves += 1;
> + printk(KERN_INFO
> + "-- dcache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
> + cpuinfo->dcache.size, cpuinfo->dcache.block_size,
> + cpuinfo->dcache.sets, cpuinfo->dcache.ways);
> + } else
> + printk(KERN_INFO "-- dcache disabled\n");
> +
> + if (cpu_cache_is_present(SPR_UPR_ICP)) {
> + iccfgr = mfspr(SPR_ICCFGR);
> + cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
> + cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
> + cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
> + cpuinfo->icache.size =
> + cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
> + leaves += 1;
> + printk(KERN_INFO
> + "-- icache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
> + cpuinfo->icache.size, cpuinfo->icache.block_size,
> + cpuinfo->icache.sets, cpuinfo->icache.ways);
> + } else
> + printk(KERN_INFO "-- icache disabled\n");
> +
> + if (!leaves)
> + return -ENOENT;
> +
> + levels = 1;
> +
> + this_cpu_ci->num_leaves = leaves;
> + this_cpu_ci->num_levels = levels;
> +
> + return 0;
> +}
> +
> +int populate_cache_leaves(unsigned int cpu)
> +{
> + struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
> + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
> + struct cacheinfo *this_leaf = this_cpu_ci->info_list;
> + int level = 1;
> +
> + if (cpu_cache_is_present(SPR_UPR_DCP)) {
> + ci_leaf_init(this_leaf, CACHE_TYPE_DATA, level, &cpuinfo->dcache, cpu);
> + this_leaf->attributes = ((mfspr(SPR_DCCFGR) & SPR_DCCFGR_CWS) >> 8) ?
> + CACHE_WRITE_BACK : CACHE_WRITE_THROUGH;
> + this_leaf++;
> + }
> +
> + if (cpu_cache_is_present(SPR_UPR_ICP))
> + ci_leaf_init(this_leaf, CACHE_TYPE_INST, level, &cpuinfo->icache, cpu);
> +
> + this_cpu_ci->cpu_map_populated = true;
> +
> + return 0;
> +}
> diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c
> index 66207cd7bb9e..caac492d045e 100644
> --- a/arch/openrisc/kernel/setup.c
> +++ b/arch/openrisc/kernel/setup.c
> @@ -113,21 +113,6 @@ static void print_cpuinfo(void)
> return;
> }
>
> - if (upr & SPR_UPR_DCP)
> - printk(KERN_INFO
> - "-- dcache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
> - cpuinfo->dcache.size, cpuinfo->dcache.block_size,
> - cpuinfo->dcache.sets, cpuinfo->dcache.ways);
> - else
> - printk(KERN_INFO "-- dcache disabled\n");
> - if (upr & SPR_UPR_ICP)
> - printk(KERN_INFO
> - "-- icache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
> - cpuinfo->icache.size, cpuinfo->icache.block_size,
> - cpuinfo->icache.sets, cpuinfo->icache.ways);
> - else
> - printk(KERN_INFO "-- icache disabled\n");
> -
> if (upr & SPR_UPR_DMP)
> printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
> 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
> @@ -155,7 +140,6 @@ static void print_cpuinfo(void)
> void __init setup_cpuinfo(void)
> {
> struct device_node *cpu;
> - unsigned long iccfgr, dccfgr;
> int cpu_id = smp_processor_id();
> struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
>
> @@ -163,20 +147,6 @@ void __init setup_cpuinfo(void)
> if (!cpu)
> panic("Couldn't find CPU%d in device tree...\n", cpu_id);
>
> - iccfgr = mfspr(SPR_ICCFGR);
> - cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
> - cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
> - cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
> - cpuinfo->icache.size =
> - cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
> -
> - dccfgr = mfspr(SPR_DCCFGR);
> - cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
> - cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
> - cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
> - cpuinfo->dcache.size =
> - cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
> -
> if (of_property_read_u32(cpu, "clock-frequency",
> &cpuinfo->clock_frequency)) {
> printk(KERN_WARNING
> @@ -319,14 +289,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
> seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
> }
> seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
> - seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache.size);
> - seq_printf(m, "dcache block size\t: %d bytes\n",
> - cpuinfo->dcache.block_size);
> - seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache.ways);
> - seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache.size);
> - seq_printf(m, "icache block size\t: %d bytes\n",
> - cpuinfo->icache.block_size);
> - seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache.ways);
> seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
> 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
> 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
> --
> 2.48.1
>
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