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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47d7f703a8csm308010895e9.13.2026.01.11.08.39.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jan 2026 08:39:22 -0800 (PST) Date: Sun, 11 Jan 2026 16:39:22 +0000 From: Stafford Horne To: Bartosz Golaszewski Cc: LKML , Linux OpenRISC Subject: Re: (subset) [PATCH v2 0/5] OpenRISC de0 nano single and multicore boards Message-ID: References: <20251217080843.70621-1-shorne@gmail.com> <176606559331.6520.4498279930581822500.b4-ty@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-openrisc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <176606559331.6520.4498279930581822500.b4-ty@oss.qualcomm.com> On Thu, Dec 18, 2025 at 02:46:48PM +0100, Bartosz Golaszewski wrote: > > On Wed, 17 Dec 2025 08:08:26 +0000, Stafford Horne wrote: > > Since v1: > > - Use proper schema in gpio-mmio suggsted by Conor Dooley > > - Remove 0 clock-frequency definitions in dtsi file > > > > The patches add support for OpenRISC systems running on the De0 Nano FPGA > > development board. We have two SoCs which are available here: > > > > [...] > > Tweaked the commit message a bit and applied, thanks! > > [1/5] dt-bindings: Add compatible string opencores,gpio to gpio-mmio > commit: f48b5e8bc2e1344f588cc730082aed6ccc5a6b3e Hi Bartosz, After discussion [1] with Linus W and Geert U on this patch we agreed it would be best to drop this old patch and replace with a patch to add "opencores,gpio" to the binding and the driver. I have sent two new patches for that. Can you please consider dropping this original patch from your queue and replacing with the new? If you prefer me to post these in a different way I can do that too. [1] https://lore.kernel.org/lkml/CAD++jLm1u9ChqsftwvbOptiG3Qo2KWxPjqN2snOVuZDYuVST5Q@mail.gmail.com/ -Stafford