From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: opensbi@lists.infradead.org
Subject: [PATCH v2 0/3] RISC-V Smstateen support
Date: Tue, 5 Apr 2022 16:15:38 +0530 [thread overview]
Message-ID: <20220405104541.13185-1-mchitale@ventanamicro.com> (raw)
This series adds support for the Smstateen specification which provides
a mechanism to plug potential covert channels which are opened by extensions
which add to processor state that may not get context-switched. Currently
access to AIA registers and *envcfg registers is controlled via
smstateen.
Changes in v2:
- Rebase on latest master branch
- Fix RV32 compilation issue
- Fix indentation issue
Mayuresh Chitale (3):
lib: sbi: Add Smstateen extension defines
lib: sbi: Detect Smstateen CSRs at boot-time
lib: irqchip/imsic: configure mstateen
include/sbi/riscv_encoding.h | 44 ++++++++++++++++++++++++++++++++++++
include/sbi/sbi_hart.h | 4 +++-
lib/sbi/sbi_hart.c | 31 +++++++++++++++++++++++++
3 files changed, 78 insertions(+), 1 deletion(-)
--
2.17.1
next reply other threads:[~2022-04-05 10:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-05 10:45 Mayuresh Chitale [this message]
2022-04-05 10:45 ` [PATCH v2 1/3] lib: sbi: Add Smstateen extension defines Mayuresh Chitale
2022-04-05 10:45 ` [PATCH v2 2/3] lib: sbi: Detect Smstateen CSRs at boot-time Mayuresh Chitale
2022-04-05 15:55 ` Xiang W
2022-04-05 10:45 ` [PATCH v2 3/3] lib: irqchip/imsic: configure mstateen Mayuresh Chitale
2022-04-05 11:05 ` [PATCH v2 0/3] RISC-V Smstateen support Mayuresh Chitale
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