From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mayuresh Chitale Date: Tue, 5 Apr 2022 16:15:41 +0530 Subject: [PATCH v2 3/3] lib: irqchip/imsic: configure mstateen In-Reply-To: <20220405104541.13185-1-mchitale@ventanamicro.com> References: <20220405104541.13185-1-mchitale@ventanamicro.com> Message-ID: <20220405104541.13185-4-mchitale@ventanamicro.com> List-Id: To: opensbi@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit When mstateen registers are implemented, the AIA related configurations need to be done in mstateen for the IMSIC initialization to succeed. Signed-off-by: Mayuresh Chitale --- lib/sbi/sbi_hart.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index db08eaf..604e0b4 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -98,6 +98,12 @@ static void mstatus_init(struct sbi_scratch *scratch) mstateen_val |= SMSTATEEN0_HSENVCFG; else mstateen_val &= ~SMSTATEEN0_HSENVCFG; + if (sbi_hart_has_feature(scratch, SBI_HART_HAS_AIA)) + mstateen_val |= (SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT | + SMSTATEEN0_IMSIC); + else + mstateen_val &= ~(SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT | + SMSTATEEN0_IMSIC); csr_write(CSR_MSTATEEN0, mstateen_val); #if __riscv_xlen == 32 csr_write(CSR_MSTATEEN0H, mstateen_val >> 32); -- 2.17.1