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From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: opensbi@lists.infradead.org
Subject: [PATCH v3 3/3] lib: irqchip/imsic: configure mstateen
Date: Wed,  6 Apr 2022 22:27:41 +0530	[thread overview]
Message-ID: <20220406165741.663-4-mchitale@ventanamicro.com> (raw)
In-Reply-To: <20220406165741.663-1-mchitale@ventanamicro.com>

When mstateen registers are implemented, the AIA related
configurations need to be done in mstateen for the IMSIC
initialization to succeed.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
 lib/sbi/sbi_hart.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index b0edf38..7b602c3 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -98,6 +98,12 @@ static void mstatus_init(struct sbi_scratch *scratch)
 			mstateen_val |= SMSTATEEN0_HSENVCFG;
 		else
 			mstateen_val &= ~SMSTATEEN0_HSENVCFG;
+		if (sbi_hart_has_feature(scratch, SBI_HART_HAS_AIA))
+			mstateen_val |= (SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT |
+					SMSTATEEN0_IMSIC);
+		else
+			mstateen_val &= ~(SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT |
+					SMSTATEEN0_IMSIC);
 		csr_write(CSR_MSTATEEN0, mstateen_val);
 #if __riscv_xlen == 32
 		csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
-- 
2.17.1



  parent reply	other threads:[~2022-04-06 16:57 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-06 16:57 [PATCH v3 0/3] RISC-V Smstateen support Mayuresh Chitale
2022-04-06 16:57 ` [PATCH v3 1/3] lib: sbi: Add Smstateen extension defines Mayuresh Chitale
2022-04-07  9:53   ` Xiang W
2022-04-11  3:11   ` Anup Patel
2022-04-06 16:57 ` [PATCH v3 2/3] lib: sbi: Detect Smstateen CSRs at boot-time Mayuresh Chitale
2022-04-07  9:54   ` Xiang W
2022-04-11  3:12   ` Anup Patel
2022-04-06 16:57 ` Mayuresh Chitale [this message]
2022-04-07  9:55   ` [PATCH v3 3/3] lib: irqchip/imsic: configure mstateen Xiang W
2022-04-11  3:12   ` Anup Patel

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