From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu Chien Peter Lin Date: Thu, 30 Nov 2023 20:42:03 +0800 Subject: [PATCH v4 05/15] platform: include: andes45: Add PMU related CSR defines In-Reply-To: <20231130124213.2590640-1-peterlin@andestech.com> References: <20231130124213.2590640-1-peterlin@andestech.com> Message-ID: <20231130124213.2590640-6-peterlin@andestech.com> List-Id: To: opensbi@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Add CSR definitions for Andes PMU extension. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar --- Changes v1 -> v2: - Rename andes_pmu() -> has_andes_pmu() Changes v2 -> v3: - Include Anup's RB tag Changes v3 -> v4: - Include RB tags --- platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h index f570994..ce31617 100644 --- a/platform/generic/include/andes/andes45.h +++ b/platform/generic/include/andes/andes45.h @@ -12,6 +12,17 @@ #define CSR_MDCM_CFG 0xfc1 #define CSR_MMSC_CFG 0xfc2 +/* Machine Trap Related Registers */ +#define CSR_MSLIDELEG 0x7d5 + +/* Counter Related Registers */ +#define CSR_MCOUNTERWEN 0x7ce +#define CSR_MCOUNTERINTEN 0x7cf +#define CSR_MCOUNTERMASK_M 0x7d1 +#define CSR_MCOUNTERMASK_S 0x7d2 +#define CSR_MCOUNTERMASK_U 0x7d3 +#define CSR_MCOUNTEROVF 0x7d4 + #define MICM_CFG_ISZ_OFFSET 6 #define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET) @@ -26,4 +37,19 @@ #define MCACHE_CTL_CCTL_SUEN_OFFSET 8 #define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET) +/* Performance monitor */ +#define MMSC_CFG_PMNDS_MASK (1 << 15) +#define MIP_PMOVI (1 << 18) + +#ifndef __ASSEMBLER__ + +#define has_andes_pmu() \ +({ \ + (((csr_read(CSR_MMSC_CFG) & \ + MMSC_CFG_PMNDS_MASK) \ + && misa_extension('S')) ? true : false); \ +}) + +#endif /* __ASSEMBLER__ */ + #endif /* _RISCV_ANDES45_H */ -- 2.34.1