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Mon, 19 May 2025 14:59:08 -0700 (PDT) Received: from localhost.localdomain ([50.175.154.178]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2320418f249sm46386625ad.215.2025.05.19.14.59.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 14:59:08 -0700 (PDT) From: Chao-ying Fu X-Google-Original-From: Chao-ying Fu To: opensbi@lists.infradead.org Cc: Chao-ying Fu Subject: [PATCH v5 07/10] Initialize MIPS custom PMA registers Date: Mon, 19 May 2025 14:58:44 -0700 Message-ID: <20250519215848.27569-8-cfu@mips.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250519_145910_098114_D701A702 X-CRM114-Status: GOOD ( 12.03 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org Before PMP set up, we need to set up MIPS custom PMA registers to have correct cacheable or uncacheable execution for pmp regions. Signed-off-by: Chao-ying Fu --- lib/sbi/riscv_asm.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index c7d75ac..7eb02cf 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -12,6 +12,9 @@ #include #include #include +#ifdef CONFIG_PLATFORM_MIPS_P8700 +#include +#endif /* determine CPU extension, return non-zero support */ int misa_extension_imp(char ext) @@ -119,6 +122,9 @@ unsigned long csr_read_num(int csr_num) unsigned long ret = 0; switch (csr_num) { +#ifdef CONFIG_PLATFORM_MIPS_P8700 + switchcase_csr_read_16(CSR_MIPSPMACFG0, ret) +#endif switchcase_csr_read_16(CSR_PMPCFG0, ret) switchcase_csr_read_64(CSR_PMPADDR0, ret) switchcase_csr_read(CSR_MCYCLE, ret) @@ -199,6 +205,9 @@ void csr_write_num(int csr_num, unsigned long val) switchcase_csr_write_32(__csr_num + 32, __val) switch (csr_num) { +#ifdef CONFIG_PLATFORM_MIPS_P8700 + switchcase_csr_write_16(CSR_MIPSPMACFG0, val) +#endif switchcase_csr_write_16(CSR_PMPCFG0, val) switchcase_csr_write_64(CSR_PMPADDR0, val) switchcase_csr_write(CSR_MCYCLE, val) @@ -301,6 +310,29 @@ int is_pmp_entry_mapped(unsigned long entry) return false; } +#ifdef CONFIG_PLATFORM_MIPS_P8700 +extern unsigned long _fw_start; +static void pma_set(unsigned int n, unsigned long addr) +{ + int pmacfg_csr, pmacfg_shift; + unsigned long cfgmask; + unsigned long pmacfg, cca; + + pmacfg_csr = (CSR_MIPSPMACFG0 + (n >> 2)) & ~1; + pmacfg_shift = (n & 7) << 3; + cfgmask = ~(0xffUL << pmacfg_shift); + + /* Read pmacfg to change cacheability */ + pmacfg = (csr_read_num(pmacfg_csr) & cfgmask); + if (addr >= (unsigned long)&_fw_start) + cca = CCA_CACHE_ENABLE | PMA_SPECULATION; + else + cca = CCA_CACHE_DISABLE; + pmacfg |= ((cca << pmacfg_shift) & ~cfgmask); + csr_write_num(pmacfg_csr, pmacfg); +} +#endif + int pmp_set(unsigned int n, unsigned long prot, unsigned long addr, unsigned long log2len) { @@ -312,6 +344,10 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr, if (n >= PMP_COUNT || log2len > __riscv_xlen || log2len < PMP_SHIFT) return SBI_EINVAL; +#ifdef CONFIG_PLATFORM_MIPS_P8700 + pma_set(n, addr); +#endif + /* calculate PMP register and offset */ #if __riscv_xlen == 32 pmpcfg_csr = CSR_PMPCFG0 + (n >> 2); -- 2.47.1 -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi