Re: [PATCH] lib: Allow custom CSRs in csr_read_num() and csr_write_num()

Anup Patel
2025-10-21T14:12:55Z

On Tue, Sep 30, 2025 at 9:02 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> Some of the platforms use platform specific CSR access functions for
> configuring implementation specific CSRs (such as PMA registers).
>
> Extend the common csr_read_num() and csr_write_num() to allow custom
> CSRs so that platform specific CSR access functions are not needed.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> include/sbi/riscv_encoding.h | 34 ++++++++
> lib/sbi/riscv_asm.c | 135 ++++++++++++++++++-----------
> platform/generic/andes/andes_pma.c | 90 ++-----------------
> platform/generic/mips/p8700.c | 76 +---------------
> 4 files changed, 127 insertions(+), 208 deletions(-)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index 40a854e3..61e4b635 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -783,6 +783,40 @@
> #define CSR_VTYPE 0xc21
> #define CSR_VLENB 0xc22
>
> +/* Custom CSR ranges */
> +#define CSR_CUSTOM0_U_RW_BASE 0x800
> +#define CSR_CUSTOM0_U_RW_COUNT 0x100
> +
> +#define CSR_CUSTOM1_U_RO_BASE 0xCC0
> +#define CSR_CUSTOM1_U_RO_COUNT 0x040
> +
> +#define CSR_CUSTOM2_S_RW_BASE 0x5C0
> +#define CSR_CUSTOM2_S_RW_COUNT 0x040
> +
> +#define CSR_CUSTOM3_S_RW_BASE 0x9C0
> +#define CSR_CUSTOM3_S_RW_COUNT 0x040
> +
> +#define CSR_CUSTOM4_S_RO_BASE 0xDC0
> +#define CSR_CUSTOM4_S_RO_COUNT 0x040
> +
> +#define CSR_CUSTOM5_HS_RW_BASE 0x6C0
> +#define CSR_CUSTOM5_HS_RW_COUNT 0x040
> +
> +#define CSR_CUSTOM6_HS_RW_BASE 0xAC0
> +#define CSR_CUSTOM6_HS_RW_COUNT 0x040
> +
> +#define CSR_CUSTOM7_HS_RO_BASE 0xEC0
> +#define CSR_CUSTOM7_HS_RO_COUNT 0x040
> +
> +#define CSR_CUSTOM8_M_RW_BASE 0x7C0
> +#define CSR_CUSTOM8_M_RW_COUNT 0x040
> +
> +#define CSR_CUSTOM9_M_RW_BASE 0xBC0
> +#define CSR_CUSTOM9_M_RW_COUNT 0x040
> +
> +#define CSR_CUSTOM10_M_RO_BASE 0xFC0
> +#define CSR_CUSTOM10_M_RO_COUNT 0x040
> +
> /* ===== Trap/Exception Causes ===== */
>
> #define CAUSE_MISALIGNED_FETCH 0x0
> diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c
> index c7d75ac0..3e44320f 100644
> --- a/lib/sbi/riscv_asm.c
> +++ b/lib/sbi/riscv_asm.c
> @@ -93,77 +93,91 @@ void misa_string(int xlen, char *out, unsigned int out_sz)
>
> unsigned long csr_read_num(int csr_num)
> {
> -#define switchcase_csr_read(__csr_num, __val) \
> +#define switchcase_csr_read(__csr_num) \
> case __csr_num: \
> - __val = csr_read(__csr_num); \
> - break;
> -#define switchcase_csr_read_2(__csr_num, __val) \
> - switchcase_csr_read(__csr_num + 0, __val) \
> - switchcase_csr_read(__csr_num + 1, __val)
> -#define switchcase_csr_read_4(__csr_num, __val) \
> - switchcase_csr_read_2(__csr_num + 0, __val) \
> - switchcase_csr_read_2(__csr_num + 2, __val)
> -#define switchcase_csr_read_8(__csr_num, __val) \
> - switchcase_csr_read_4(__csr_num + 0, __val) \
> - switchcase_csr_read_4(__csr_num + 4, __val)
> -#define switchcase_csr_read_16(__csr_num, __val) \
> - switchcase_csr_read_8(__csr_num + 0, __val) \
> - switchcase_csr_read_8(__csr_num + 8, __val)
> -#define switchcase_csr_read_32(__csr_num, __val) \
> - switchcase_csr_read_16(__csr_num + 0, __val) \
> - switchcase_csr_read_16(__csr_num + 16, __val)
> -#define switchcase_csr_read_64(__csr_num, __val) \
> - switchcase_csr_read_32(__csr_num + 0, __val) \
> - switchcase_csr_read_32(__csr_num + 32, __val)
> -
> - unsigned long ret = 0;
> + return csr_read(__csr_num);
> +#define switchcase_csr_read_2(__csr_num) \
> + switchcase_csr_read(__csr_num + 0) \
> + switchcase_csr_read(__csr_num + 1)
> +#define switchcase_csr_read_4(__csr_num) \
> + switchcase_csr_read_2(__csr_num + 0) \
> + switchcase_csr_read_2(__csr_num + 2)
> +#define switchcase_csr_read_8(__csr_num) \
> + switchcase_csr_read_4(__csr_num + 0) \
> + switchcase_csr_read_4(__csr_num + 4)
> +#define switchcase_csr_read_16(__csr_num) \
> + switchcase_csr_read_8(__csr_num + 0) \
> + switchcase_csr_read_8(__csr_num + 8)
> +#define switchcase_csr_read_32(__csr_num) \
> + switchcase_csr_read_16(__csr_num + 0) \
> + switchcase_csr_read_16(__csr_num + 16)
> +#define switchcase_csr_read_64(__csr_num) \
> + switchcase_csr_read_32(__csr_num + 0) \
> + switchcase_csr_read_32(__csr_num + 32)
> +#define switchcase_csr_read_128(__csr_num) \
> + switchcase_csr_read_64(__csr_num + 0) \
> + switchcase_csr_read_64(__csr_num + 64)
> +#define switchcase_csr_read_256(__csr_num) \
> + switchcase_csr_read_128(__csr_num + 0) \
> + switchcase_csr_read_128(__csr_num + 128)
>
> switch (csr_num) {
> - switchcase_csr_read_16(CSR_PMPCFG0, ret)
> - switchcase_csr_read_64(CSR_PMPADDR0, ret)
> - switchcase_csr_read(CSR_MCYCLE, ret)
> - switchcase_csr_read(CSR_MINSTRET, ret)
> - switchcase_csr_read(CSR_MHPMCOUNTER3, ret)
> - switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret)
> - switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret)
> - switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret)
> - switchcase_csr_read(CSR_MCOUNTINHIBIT, ret)
> - switchcase_csr_read(CSR_MCYCLECFG, ret)
> - switchcase_csr_read(CSR_MINSTRETCFG, ret)
> - switchcase_csr_read(CSR_MHPMEVENT3, ret)
> - switchcase_csr_read_4(CSR_MHPMEVENT4, ret)
> - switchcase_csr_read_8(CSR_MHPMEVENT8, ret)
> - switchcase_csr_read_16(CSR_MHPMEVENT16, ret)
> + switchcase_csr_read_16(CSR_PMPCFG0)
> + switchcase_csr_read_64(CSR_PMPADDR0)
> + switchcase_csr_read(CSR_MCYCLE)
> + switchcase_csr_read(CSR_MINSTRET)
> + switchcase_csr_read(CSR_MHPMCOUNTER3)
> + switchcase_csr_read_4(CSR_MHPMCOUNTER4)
> + switchcase_csr_read_8(CSR_MHPMCOUNTER8)
> + switchcase_csr_read_16(CSR_MHPMCOUNTER16)
> + switchcase_csr_read(CSR_MCOUNTINHIBIT)
> + switchcase_csr_read(CSR_MCYCLECFG)
> + switchcase_csr_read(CSR_MINSTRETCFG)
> + switchcase_csr_read(CSR_MHPMEVENT3)
> + switchcase_csr_read_4(CSR_MHPMEVENT4)
> + switchcase_csr_read_8(CSR_MHPMEVENT8)
> + switchcase_csr_read_16(CSR_MHPMEVENT16)
> #if __riscv_xlen == 32
> - switchcase_csr_read(CSR_MCYCLEH, ret)
> - switchcase_csr_read(CSR_MINSTRETH, ret)
> - switchcase_csr_read(CSR_MHPMCOUNTER3H, ret)
> - switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret)
> - switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret)
> - switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret)
> + switchcase_csr_read(CSR_MCYCLEH)
> + switchcase_csr_read(CSR_MINSTRETH)
> + switchcase_csr_read(CSR_MHPMCOUNTER3H)
> + switchcase_csr_read_4(CSR_MHPMCOUNTER4H)
> + switchcase_csr_read_8(CSR_MHPMCOUNTER8H)
> + switchcase_csr_read_16(CSR_MHPMCOUNTER16H)
> /**
> * The CSR range M[CYCLE, INSTRET]CFGH are available only if smcntrpmf
> * extension is present. The caller must ensure that.
> */
> - switchcase_csr_read(CSR_MCYCLECFGH, ret)
> - switchcase_csr_read(CSR_MINSTRETCFGH, ret)
> + switchcase_csr_read(CSR_MCYCLECFGH)
> + switchcase_csr_read(CSR_MINSTRETCFGH)
> /**
> * The CSR range MHPMEVENT[3-16]H are available only if sscofpmf
> * extension is present. The caller must ensure that.
> */
> - switchcase_csr_read(CSR_MHPMEVENT3H, ret)
> - switchcase_csr_read_4(CSR_MHPMEVENT4H, ret)
> - switchcase_csr_read_8(CSR_MHPMEVENT8H, ret)
> - switchcase_csr_read_16(CSR_MHPMEVENT16H, ret)
> + switchcase_csr_read(CSR_MHPMEVENT3H)
> + switchcase_csr_read_4(CSR_MHPMEVENT4H)
> + switchcase_csr_read_8(CSR_MHPMEVENT8H)
> + switchcase_csr_read_16(CSR_MHPMEVENT16H)
> #endif
> + switchcase_csr_read_256(CSR_CUSTOM0_U_RW_BASE)
> + switchcase_csr_read_64(CSR_CUSTOM1_U_RO_BASE)
> + switchcase_csr_read_64(CSR_CUSTOM2_S_RW_BASE)
> + switchcase_csr_read_64(CSR_CUSTOM3_S_RW_BASE)
> + switchcase_csr_read_64(CSR_CUSTOM4_S_RO_BASE)
> + switchcase_csr_read_64(CSR_CUSTOM5_HS_RW_BASE)
> + switchcase_csr_read_64(CSR_CUSTOM6_HS_RW_BASE)
> + switchcase_csr_read_64(CSR_CUSTOM7_HS_RO_BASE)
> + switchcase_csr_read_64(CSR_CUSTOM8_M_RW_BASE)
> + switchcase_csr_read_64(CSR_CUSTOM9_M_RW_BASE)
> + switchcase_csr_read_64(CSR_CUSTOM10_M_RO_BASE)
>
> default:
> sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
> - break;
> + return 0;
> }
>
> - return ret;
> -
> +#undef switchcase_csr_read_256
> +#undef switchcase_csr_read_128
> #undef switchcase_csr_read_64
> #undef switchcase_csr_read_32
> #undef switchcase_csr_read_16
> @@ -197,6 +211,12 @@ void csr_write_num(int csr_num, unsigned long val)
> #define switchcase_csr_write_64(__csr_num, __val) \
> switchcase_csr_write_32(__csr_num + 0, __val) \
> switchcase_csr_write_32(__csr_num + 32, __val)
> +#define switchcase_csr_write_128(__csr_num, __val) \
> + switchcase_csr_write_64(__csr_num + 0, __val) \
> + switchcase_csr_write_64(__csr_num + 64, __val)
> +#define switchcase_csr_write_256(__csr_num, __val) \
> + switchcase_csr_write_128(__csr_num + 0, __val) \
> + switchcase_csr_write_128(__csr_num + 128, __val)
>
> switch (csr_num) {
> switchcase_csr_write_16(CSR_PMPCFG0, val)
> @@ -228,12 +248,21 @@ void csr_write_num(int csr_num, unsigned long val)
> switchcase_csr_write_4(CSR_MHPMEVENT4, val)
> switchcase_csr_write_8(CSR_MHPMEVENT8, val)
> switchcase_csr_write_16(CSR_MHPMEVENT16, val)
> + switchcase_csr_write_256(CSR_CUSTOM0_U_RW_BASE, val)
> + switchcase_csr_write_64(CSR_CUSTOM2_S_RW_BASE, val)
> + switchcase_csr_write_64(CSR_CUSTOM3_S_RW_BASE, val)
> + switchcase_csr_write_64(CSR_CUSTOM5_HS_RW_BASE, val)
> + switchcase_csr_write_64(CSR_CUSTOM6_HS_RW_BASE, val)
> + switchcase_csr_write_64(CSR_CUSTOM8_M_RW_BASE, val)
> + switchcase_csr_write_64(CSR_CUSTOM9_M_RW_BASE, val)
>
> default:
> sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
> break;
> }
>
> +#undef switchcase_csr_write_256
> +#undef switchcase_csr_write_128
> #undef switchcase_csr_write_64
> #undef switchcase_csr_write_32
> #undef switchcase_csr_write_16
> diff --git a/platform/generic/andes/andes_pma.c b/platform/generic/andes/andes_pma.c
> index eeeb110e..ba9a35bb 100644
> --- a/platform/generic/andes/andes_pma.c
> +++ b/platform/generic/andes/andes_pma.c
> @@ -17,78 +17,6 @@
> #include <sbi/sbi_error.h>
> #include <sbi_utils/fdt/fdt_helper.h>
>
> -static unsigned long andes_pma_read_num(unsigned int csr_num)
> -{
> -#define switchcase_csr_read(__csr_num, __val) \
> - case __csr_num: \
> - __val = csr_read(__csr_num); \
> - break;
> -#define switchcase_csr_read_2(__csr_num, __val) \
> - switchcase_csr_read(__csr_num + 0, __val) \
> - switchcase_csr_read(__csr_num + 1, __val)
> -#define switchcase_csr_read_4(__csr_num, __val) \
> - switchcase_csr_read_2(__csr_num + 0, __val) \
> - switchcase_csr_read_2(__csr_num + 2, __val)
> -#define switchcase_csr_read_8(__csr_num, __val) \
> - switchcase_csr_read_4(__csr_num + 0, __val) \
> - switchcase_csr_read_4(__csr_num + 4, __val)
> -#define switchcase_csr_read_16(__csr_num, __val) \
> - switchcase_csr_read_8(__csr_num + 0, __val) \
> - switchcase_csr_read_8(__csr_num + 8, __val)
> -
> - unsigned long ret = 0;
> -
> - switch (csr_num) {
> - switchcase_csr_read_4(CSR_PMACFG0, ret)
> - switchcase_csr_read_16(CSR_PMAADDR0, ret)
> - default:
> - sbi_panic("%s: Unknown Andes PMA CSR %#x", __func__, csr_num);
> - break;
> - }
> -
> - return ret;
> -
> -#undef switchcase_csr_read_16
> -#undef switchcase_csr_read_8
> -#undef switchcase_csr_read_4
> -#undef switchcase_csr_read_2
> -#undef switchcase_csr_read
> -}
> -
> -static void andes_pma_write_num(unsigned int csr_num, unsigned long val)
> -{
> -#define switchcase_csr_write(__csr_num, __val) \
> - case __csr_num: \
> - csr_write(__csr_num, __val); \
> - break;
> -#define switchcase_csr_write_2(__csr_num, __val) \
> - switchcase_csr_write(__csr_num + 0, __val) \
> - switchcase_csr_write(__csr_num + 1, __val)
> -#define switchcase_csr_write_4(__csr_num, __val) \
> - switchcase_csr_write_2(__csr_num + 0, __val) \
> - switchcase_csr_write_2(__csr_num + 2, __val)
> -#define switchcase_csr_write_8(__csr_num, __val) \
> - switchcase_csr_write_4(__csr_num + 0, __val) \
> - switchcase_csr_write_4(__csr_num + 4, __val)
> -#define switchcase_csr_write_16(__csr_num, __val) \
> - switchcase_csr_write_8(__csr_num + 0, __val) \
> - switchcase_csr_write_8(__csr_num + 8, __val)
> -
> - switch (csr_num) {
> - switchcase_csr_write_4(CSR_PMACFG0, val)
> - switchcase_csr_write_16(CSR_PMAADDR0, val)
> - default:
> - sbi_panic("%s: Unknown Andes PMA CSR %#x", __func__, csr_num);
> - break;
> - }
> -
> -#undef switchcase_csr_write_16
> -#undef switchcase_csr_write_8
> -#undef switchcase_csr_write_4
> -#undef switchcase_csr_write_2
> -#undef switchcase_csr_write
> -}
> -
> static inline bool not_napot(unsigned long addr, unsigned long size)
> {
> return ((size & (size - 1)) || (addr & (size - 1)));
> @@ -108,11 +36,11 @@ static char get_pmaxcfg(int entry_id)
>
> #if __riscv_xlen == 64
> pmacfg_addr = CSR_PMACFG0 + ((entry_id / 8) ? 2 : 0);
> - pmacfg_val = andes_pma_read_num(pmacfg_addr);
> + pmacfg_val = csr_read_num(pmacfg_addr);
> pmaxcfg = (char *)&pmacfg_val + (entry_id % 8);
> #elif __riscv_xlen == 32
> pmacfg_addr = CSR_PMACFG0 + (entry_id / 4);
> - pmacfg_val = andes_pma_read_num(pmacfg_addr);
> + pmacfg_val = csr_read_num(pmacfg_addr);
> pmaxcfg = (char *)&pmacfg_val + (entry_id % 4);
> #else
> #error "Unexpected __riscv_xlen"
> @@ -128,17 +56,17 @@ static void set_pmaxcfg(int entry_id, char flags)
>
> #if __riscv_xlen == 64
> pmacfg_addr = CSR_PMACFG0 + ((entry_id / 8) ? 2 : 0);
> - pmacfg_val = andes_pma_read_num(pmacfg_addr);
> + pmacfg_val = csr_read_num(pmacfg_addr);
> pmaxcfg = (char *)&pmacfg_val + (entry_id % 8);
> #elif __riscv_xlen == 32
> pmacfg_addr = CSR_PMACFG0 + (entry_id / 4);
> - pmacfg_val = andes_pma_read_num(pmacfg_addr);
> + pmacfg_val = csr_read_num(pmacfg_addr);
> pmaxcfg = (char *)&pmacfg_val + (entry_id % 4);
> #else
> #error "Unexpected __riscv_xlen"
> #endif
> *pmaxcfg = flags;
> - andes_pma_write_num(pmacfg_addr, pmacfg_val);
> + csr_write_num(pmacfg_addr, pmacfg_val);
> }
>
> static void decode_pmaaddrx(int entry_id, unsigned long *start,
> @@ -152,7 +80,7 @@ static void decode_pmaaddrx(int entry_id, unsigned long *start,
> * size = 2 ^ (k + 3)
> * start = 4 * ($pmaaddr - (size / 8) + 1)
> */
> - pmaaddr = andes_pma_read_num(CSR_PMAADDR0 + entry_id);
> + pmaaddr = csr_read_num(CSR_PMAADDR0 + entry_id);
> k = sbi_ffz(pmaaddr);
> *size = 1 << (k + 3);
> *start = (pmaaddr - (1 << k) + 1) << 2;
> @@ -199,9 +127,9 @@ static unsigned long andes_pma_setup(const struct andes_pma_region *pma_region,
>
> pmaaddr = (addr >> 2) + (size >> 3) - 1;
>
> - andes_pma_write_num(CSR_PMAADDR0 + entry_id, pmaaddr);
> + csr_write_num(CSR_PMAADDR0 + entry_id, pmaaddr);
>
> - return andes_pma_read_num(CSR_PMAADDR0 + entry_id) == pmaaddr ?
> + return csr_read_num(CSR_PMAADDR0 + entry_id) == pmaaddr ?
> pmaaddr : SBI_EINVAL;
> }
>
> @@ -429,7 +357,7 @@ int andes_sbi_free_pma(unsigned long pa)
> continue;
>
> set_pmaxcfg(i, ANDES_PMACFG_ETYP_OFF);
> - andes_pma_write_num(CSR_PMAADDR0 + i, 0);
> + csr_write_num(CSR_PMAADDR0 + i, 0);
>
> return SBI_SUCCESS;
> }
> diff --git a/platform/generic/mips/p8700.c b/platform/generic/mips/p8700.c
> index d3e015ba..a25610a1 100644
> --- a/platform/generic/mips/p8700.c
> +++ b/platform/generic/mips/p8700.c
> @@ -18,78 +18,6 @@
>
> extern void mips_warm_boot(void);
>
> -static unsigned long mips_csr_read_num(int csr_num)
> -{
> -#define switchcase_csr_read(__csr_num, __val) \
> - case __csr_num: \
> - __val = csr_read(__csr_num); \
> - break;
> -#define switchcase_csr_read_2(__csr_num, __val) \
> - switchcase_csr_read(__csr_num + 0, __val) \
> - switchcase_csr_read(__csr_num + 1, __val)
> -#define switchcase_csr_read_4(__csr_num, __val) \
> - switchcase_csr_read_2(__csr_num + 0, __val) \
> - switchcase_csr_read_2(__csr_num + 2, __val)
> -#define switchcase_csr_read_8(__csr_num, __val) \
> - switchcase_csr_read_4(__csr_num + 0, __val) \
> - switchcase_csr_read_4(__csr_num + 4, __val)
> -#define switchcase_csr_read_16(__csr_num, __val) \
> - switchcase_csr_read_8(__csr_num + 0, __val) \
> - switchcase_csr_read_8(__csr_num + 8, __val)
> -
> - unsigned long ret = 0;
> -
> - switch(csr_num) {
> - switchcase_csr_read_16(CSR_MIPSPMACFG0, ret)
> -
> - default:
> - sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
> - break;
> - }
> -
> - return ret;
> -
> -#undef switchcase_csr_read_16
> -#undef switchcase_csr_read_8
> -#undef switchcase_csr_read_4
> -#undef switchcase_csr_read_2
> -#undef switchcase_csr_read
> -}
> -
> -static void mips_csr_write_num(int csr_num, unsigned long val)
> -{
> -#define switchcase_csr_write(__csr_num, __val) \
> - case __csr_num: \
> - csr_write(__csr_num, __val); \
> - break;
> -#define switchcase_csr_write_2(__csr_num, __val) \
> - switchcase_csr_write(__csr_num + 0, __val) \
> - switchcase_csr_write(__csr_num + 1, __val)
> -#define switchcase_csr_write_4(__csr_num, __val) \
> - switchcase_csr_write_2(__csr_num + 0, __val) \
> - switchcase_csr_write_2(__csr_num + 2, __val)
> -#define switchcase_csr_write_8(__csr_num, __val) \
> - switchcase_csr_write_4(__csr_num + 0, __val) \
> - switchcase_csr_write_4(__csr_num + 4, __val)
> -#define switchcase_csr_write_16(__csr_num, __val) \
> - switchcase_csr_write_8(__csr_num + 0, __val) \
> - switchcase_csr_write_8(__csr_num + 8, __val)
> -
> - switch(csr_num) {
> - switchcase_csr_write_16(CSR_MIPSPMACFG0, val)
> -
> - default:
> - sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
> - break;
> - }
> -
> -#undef switchcase_csr_write_16
> -#undef switchcase_csr_write_8
> -#undef switchcase_csr_write_4
> -#undef switchcase_csr_write_2
> -#undef switchcase_csr_write
> -}
> -
> static void mips_p8700_pmp_set(unsigned int n, unsigned long flags,
> unsigned long prot, unsigned long addr,
> unsigned long log2len)
> @@ -103,11 +31,11 @@ static void mips_p8700_pmp_set(unsigned int n, unsigned long flags,
> cfgmask = ~(0xffUL << pmacfg_shift);
>
> /* Read pmacfg to change cacheability */
> - pmacfg = (mips_csr_read_num(pmacfg_csr) & cfgmask);
> + pmacfg = (csr_read_num(pmacfg_csr) & cfgmask);
> cca = (flags & SBI_DOMAIN_MEMREGION_MMIO) ? CCA_CACHE_DISABLE :
> CCA_CACHE_ENABLE | PMA_SPECULATION;
> pmacfg |= ((cca << pmacfg_shift) & ~cfgmask);
> - mips_csr_write_num(pmacfg_csr, pmacfg);
> + csr_write_num(pmacfg_csr, pmacfg);
> }
>
> #if CLUSTERS_IN_PLATFORM > 1
> --
> 2.43.0
>