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Mon, 10 Nov 2025 19:42:40 -0800 (PST) Received: from m91p.airy.home ([172.92.174.155]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-341a68bf37bsm19434060a91.7.2025.11.10.19.42.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 19:42:39 -0800 (PST) From: Bo Gan To: opensbi@lists.infradead.org Cc: linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, gaohan@iscas.ac.cn, samuel@sholland.org Subject: [PATCH 0/3] Initial ESWIN/EIC7700 support Date: Mon, 10 Nov 2025 19:41:08 -0800 Message-Id: <20251111034111.43973-1-ganboing@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251110_194242_875546_E5B0867F X-CRM114-Status: GOOD ( 13.25 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org EIC7700 is the SoC used in HiFive P550 and Milk-V Megrez. This SoC is currently one of the only off-the-shelf board/chips that support H extension, although it's v0.6.1. It also supports pre-ratified N-trace. Add support for it so people can benefit from latest OpenSBI features. The device-tree of HiFive P550 has been upstreamed to Linux: https://lore.kernel.org/all/20250825132427.1618089-1-pinkesh.vaghela@einfochips.com/ However U-boot is not, and there are bugs in vendor U-boot device-tree, and also inconsistencies between the two. Thus, this patch is coded with the upstreamed device-tree as the reference, but tested with the patched vendor U-boot device tree as `FW_FDT_PATH`. The patched vendor U-boot is hosted here: https://github.com/ganboing/u-boot-eic7x/tree/eic7x-dt-fix Refer to PATCH 3/3 for the instructions on building the firmware blob and launch it through UART boot. The major complication of this chip is that it requires certain memory regions to be blocked with PMP entries to prevent speculative execution or HW prefetcher from touching them to avoid bus errors. The logic of handling PMP is therefore enhanced to support TOR entries and allow the platform to override PMP configuration. The platform code then properly set the SoC/Chip specific PMP entries alongside with the ones passed by generic code in lib/. Bo Gan (3): lib: sbi: allow platform to override PMP configuration lib: sbi: Add pmp_set_tor for setting TOR regions platform: generic: eswin: add EIC7700 include/sbi/riscv_asm.h | 4 + include/sbi/sbi_hart.h | 9 ++ include/sbi/sbi_platform.h | 33 +++++ lib/sbi/riscv_asm.c | 75 ++++++++--- lib/sbi/sbi_hart.c | 27 ++-- platform/generic/Kconfig | 5 + platform/generic/configs/defconfig | 1 + platform/generic/eswin/Kconfig | 29 ++++ platform/generic/eswin/eic770x.c | 165 +++++++++++++++++++++++ platform/generic/eswin/objects.mk | 11 ++ platform/generic/include/eswin/eic770x.h | 49 +++++++ 11 files changed, 383 insertions(+), 25 deletions(-) create mode 100644 platform/generic/eswin/Kconfig create mode 100644 platform/generic/eswin/eic770x.c create mode 100644 platform/generic/eswin/objects.mk create mode 100644 platform/generic/include/eswin/eic770x.h -- 2.34.1 -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi